JPS6211530B2 - - Google Patents

Description

[Detailed description of the invention] For example, AGC in a radio receiver's high frequency signal system
The circuit is generally as shown in FIG. 1 or 2.

That is, in the example of FIG. 1, the signal line between the antenna tuning circuit 1 and the mixer circuit 2 is
Transistor Qa is connected, and the collector-emitter impedance of transistor Qa is controlled by the AGC signal to perform shunt AGC. Furthermore, in the example shown in FIG. 2, shunt AGC is performed by similarly controlling the impedances of diodes Da and Db. In addition, the capacitor
Ca and Cb are for DC cut.

However, transistors have V _CE -I _C characteristics as shown in Figure 3, and when V _CE reaches a level above the saturation region, the impedance between the collector and emitter increases rapidly, so the AGC circuit shown in Figure 1 Then, the level of the input signal is
When the level exceeds the saturation region level, the input signal cannot be attenuated, that is, the AGC becomes ineffective.

The AGC circuit shown in Figure 2 does not have such drawbacks and has excellent AGC characteristics, but the AGC signal must be biased by the forward voltage drop of the diodes Da and Db. For,
Capacitor Ca is used to cut the bias voltage.
Since it requires Cb, it becomes difficult to convert it into an IC.

In view of the above points, the present invention aims to provide a level control circuit that has excellent AGC characteristics and can be easily integrated into an IC.

Let's explain one example below.

In FIG. 4, 1 is an antenna tuning circuit, 2 is a mixer circuit, 3 is a local oscillator circuit, 4 is its resonance circuit,
5 is an intermediate frequency amplifier, 6 is a detection circuit, 7 is AGC
This is a signal forming circuit.

And the emitters of transistors Q ₁ and Q ₂ are
It is connected to the constant current source transistor Q ₃ to form a differential amplifier, and the output coil L ₁ of the tuned coil of the tuned circuit 1 is connected to the base of the transistors Q ₁ and Q ₂ .
A voltage is applied to both ends of the transistor Q ₁ , a bias power supply E ₁ is connected to the base of the transistor Q 1 , and the collector of the transistor Q ₂ is connected to the mixer circuit 2 .

Further, the AGC current from the forming circuit 7 is supplied to the bases of the transistors Q ₁₁ and Q ₁₂ , and their emitters are connected to the power supply terminal T ₁ , and the collector of the transistor Q ₁₁ is connected to a transistor with the opposite polarity. It is connected to the collector and base of _Q13 , and its emitter is grounded. Note that the transistors Q ₁₂ and Q ₁₄ constitute first and second current control means. This transistor _Q13 and the transistor _Q14 constitute a current mirror circuit, and the base of the transistor _Q14 is connected to the base of the transistor _Q13 , and the emitter of the transistor _Q14 is grounded.

Furthermore, the collector of transistor Q ₁₂ is connected to the collector and base of transistor Q ₁₅ , and its emitter is connected to a transistor of opposite polarity.
It is connected to the emitter of _Q17 , and its collector and base are connected to the collector of transistor _Q14 . In this case, transistors Q ₁₅ and Q ₁₇ are
and a second impedance element, and also constitute a current mirror circuit with transistors Q ₁₆ and Q ₁₈ , respectively.
The base of Q ₁₆ is connected to the base of transistor Q ₁₅ , the collector is connected to terminal T ₁ , the emitter is connected to the emitter of transistor Q ₁₈ , the base of transistor Q ₁₈ is connected to the base of transistor Q ₁₇ , the collector is grounded. Also, both ends of the output coil L ₁ of the tuned circuit 1 are transistors.
Connected to the emitters of Q ₁₅ and Q ₁₆ .

In addition, transistors Q ₁₁ and Q ₁₃ , Q ₁₂ and Q ₁₄ , Q ₁₅
~Q ₁₈ are assumed to have mutually equal characteristics.

According to such a configuration, the received signal obtained by the tuning circuit 1 is transmitted from the secondary coil L ₁ to the transistor
The signal is supplied to Q ₁ and Q ₂ and differentially amplified, and the amplified output is supplied to the mixer circuit 2.

In this case, shunt AGC is performed by the transistors Q ₁₁ to _{Q 18} on the received signal supplied from the tuning circuit 1 to the transistors Q ₁ and Q ₂ . In other words, collector currents of equal magnitude flow through the transistors Q ₁₁ and Q ₁₂ due to the AGC current from the forming circuit 7, but the transistors
Since Q ₁₃ and Q ₁₄ constitute a current mirror circuit, a collector current equal to the collector current of transistor Q ₁₁ flows through transistor Q ₁₄ , and therefore, the collector current of transistors Q ₁₂ and Q ₁₄ is Since they are equal to each other, as shown in Figure 4,
A current I ₁ proportional to the AGC current flows in the line of transistor Q ₁₂ →transistor Q ₁₅ →transistor Q ₁₇ →transistor Q ₁₄ . In addition, since transistors Q ₁₅ , Q ₁₆ and Q ₁₇ , Q ₁₈ each constitute a current mirror circuit, the collector currents of transistors Q ₁₆ and Q ₁₈ are also equal to each other.
A current I ₂ with a magnitude equal to the current I ₁ flows in the line from transistor Q ₁₆ to transistor Q ₁₈ .

Then, the transistors are connected from the emitters of transistors Q ₁₆ and Q ₁₈ through transistors Q ₁₅ and Q ₁₇ .
When looking at the Q ₁ side, the impedance r is r [Ω] = 26/I ₂ [mA] + 26/h _FE・I ₁
[mA] h _FE is the current amplification factor of Q ₁₆ and Q ₁₈ , and since the second term is sufficiently smaller than the first term, it becomes r [Ω] 〓26/I ₂ [mA]. This equation also shows the relationship between the current flowing through the diodes Da and Db in the circuit of FIG. 2 and their impedance. That is, the circuit of FIG. 4 becomes equivalently as shown in FIG. 5.

Then, when the AGC current changes, the current I ₂ changes correspondingly, and the impedance of the transistors Q ₁₆ and Q ₁₈ changes.

Therefore, the circuit of FIG. 4 works as a shunt AGC (the circuit of FIG. 2) using diodes.

Thus, according to this invention, the shunt AGC
However, in this case, especially according to the present invention, the operation is shunted by a diode.
Since it is equivalent to AGC, AGC will not stop working when a large input is applied, as is the case with AGC in Figure 1. In addition, the operation is shunted by a diode.
Even if it is an AGC, as it is clear from Fig. 4, it does not require a DC cut capacitor, so it can be easily integrated into an IC, and its effects are great.

Furthermore, since it is easy to match the characteristics of transistors Q ₁₆ and Q ₁₈ , the characteristics are the same for positive and negative cycles of the input signal, and distortion can be prevented as much as possible.

Note that in the above description, if the signal level is controlled within a narrow range, resistors may be used in place of the diode-connected transistors Q ₁₅ and Q ₁₇ . This is because each of the diode-connected transistors Q ₁₅ and Q ₁₇ is a variable impedance element whose impedance decreases in response to an increase in supply current, whereas the resistor has a fixed impedance, and due to these impedances. This is because the V _BE of the transistors Q ₁₆ and Q ₁₈ is formed and the signal level is controlled.

[Brief explanation of the drawing]

1 and 2 are connection diagrams of a conventional example, FIG. 3 is a diagram for explaining the same, FIG. 4 is a diagram for explaining an example of the present invention, and FIG. 5 is a diagram for explaining the same. 7 is an AGC signal forming circuit.

Claims (1)

[Claims] 1 A predetermined voltage is supplied between the respective collectors of the first transistor Q ₁₆ and the second transistor Q ₁₈ whose emitters are connected to each other, and the first current control means Q ₁₂ and the first impedance element
Q ₁₅ , the second impedance element Q ₁₇ and the second current control means Q ₁₄ are connected in series in this order, and a predetermined voltage is supplied between the open ends of this series circuit, and the first transistor The base of _Q16 is connected between the first current control means _Q12 and the first impedance element Q15, and the base of _the second transistor _Q18 is connected between the second impedance element _Q17 and the second impedance element Q15. is connected between the current control means _Q14 of the first and second current control means
By interlocking the currents controlled by Q ₁₂ and Q ₁₄ , there is a connection between the emitter of the first transistor Q ₁₆ and the emitter of the second transistor Q ₁₈ , and between the first impedance element Q ₁₅ and the emitter of the second transistor Q 18. A shunt-type level control circuit that controls the level of an input signal supplied between the second impedance element _Q17 and outputs the level-controlled signal from the signal supply point of the input signal.