JPS6211835B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a network disconnection method in a time division switch.

A time division switching system is a T-S switch that is a combination of a time switch T that switches time slots and a space switch S that connects highways.
Structures such as T, S-T-S, and T-S-T-S are known. The time switch T receives data written to the time switch control memory from the common control device,
It has a path memory in which call information is written and read using the output of the channel counter as an address, and the data written in the time switch control memory is used as the write address and the output of the channel counter as the read address. Generally, a time switch equipped with write and sequential read path memories is placed on the output side of a time division switch, but the following problem occurs when the call path is disconnected.

When a call path is disconnected due to the end of a call, etc., the address data written in the time switch control memory is erased, and as a result, the address written in the pass memory during the call is deleted.
No new call information will be written to that address and transmission of call information will be stopped. However, since the read address from the channel counter is continuously supplied, reading from the path memory continues. Therefore, the call information immediately before disconnection remains in the path memory and is read out repeatedly.

By repeatedly reading out the residual data in the path memory, when decoded by the decoding circuit, a DC output is generated at a level determined by the residual data. If a signaling device, for example a conference trunk, which is disturbed by this DC output is connected, it is necessary to provide DC interrupting means. Note that a conference trunk in a time-division exchange converts digital call signals input from multiple input terminals into analog signals in a decoding circuit, mixes them, and distributes them to conference participants connected to the conference trunk. If a high-level DC signal due to residual data is input as described above, it will interfere with the conference call.

Also, if connected to a digital relay line,
Since the residual data is sent out continuously,
Depending on the pattern of the residual data, for example, if the pattern is all “0”, it may be impossible to reproduce the clock at the other station, and if it is all “0”, there may be a problem with the spatial switch. If it is assumed that this is the case, it will operate incorrectly.

Furthermore, when switching the connection of the communication path, there is a drawback that the residual data described above is superimposed on the signal to be newly transmitted, causing noise.

The present invention eliminates the above-mentioned conventional drawbacks, and aims to facilitate the removal of residual data in the path memory when the network is disconnected, and to prevent various disturbances. Examples will be described in detail below.

FIG. 1 is a block diagram of essential parts of an example of a time division switch according to an embodiment of the present invention, where MPX ₁ to MPX _n are multiplexers, IHW ₁ to IHW _n are input highways,
TS ₁₁ ~ TS _1n are primary time switches, SPMF ₁ ~
SPMF _n is path memory, TSM ₁ to TSM _n is time switch control memory, SS is space switch, G ₁₁ to G
_no is gate, HSM ₁ to HSM _n is highway control memory, GHW _a1 to GHW _an , GHW _b1 to GHW _bn is intermediate highway, CTR is channel counter, PADG ₁
~PADG _n is a variable transmission loss insertion and no-speech signal pattern generator, TS ₂₁ ~ _{TS 2n} is a secondary time switch, SPMB ₁ ~SPMB _n is a path memory, DMPX ₁ ~
DMPX _n is a demultiplexer, and OHW ₁ to OHW _n are output highways.

The above-mentioned configuration is of the T-ST type, and the primary time switches TS ₁₁ to TS _1n are for sequential writing and random reading, and the secondary time switches TS ₂₁ to _{TS 2n} are for random writing and sequential reading, and are for pair control. It is a method. For example, when transmitting call information in time slot ta of input highway IHW ₁ to time slot tb of output highway OHW _n , the path memories SPMF ₁ to _{SPMF n} are stored in path memories SPMF 1 to SPMF n according to the output of channel counter _CTR .
The call information for each time slot of IHW _n is written sequentially and is also stored in the time switch control memory.
Address information ta is written by a common control device (not shown) to the address corresponding to time slot ti of TSM ₁ , and address information tb is written to the address corresponding to time slot ti of time switch control memory TSM _n . It can be done.

Therefore, the call information written to address ta of path memory SPMF ₁ is stored in the time switch control memory.
It is read out from TSM ₁ at time slot ti and sent to intermediate highway GHW _a1 . That is, the call information in the time slot ta of the input highway IHW ₁ is input to the space switch SS at the time slot ti of the intermediate highway GHW _a1 .

Space switch SS highway control memory HSM ₁
Control information for gates G ₁₁ to G _no is written in ~HSM _n . For example, at time slot ti,
Control information 1m specifying gate G _1n is written in highway control memory HSM ₁ , and control information m1 specifying gate G _n1 is written in highway control memory HSM 1, and control information 1m specifying gate G n1 is written in the highway control memory HSM ₁ . It is connected to the intermediate highway GHW _bn on the side via the gate G _1n .

The variable transmission loss insertion and no-call signal pattern generators PADG ₁ to PADG _n are for adding a predetermined transmission loss to call information and generating a no-call signal pattern when the network is disconnected, and the details will be described later.

The secondary time switches TS ₂₁ to TS _2n write the call information of the intermediate highways GHW _b1 to _{GHW bn} to the path memories SPMB ₁ to SPMB _n according to the address information from the time switch control memories TSM ₁ to TSM _n. , which reads the output of the channel counter CTR as address information.
The call information in the time slot ti of the GHW _bn is written to the path memory SPMB _n according to the address information tb read out in the time slot ti of the time switch control memory TSM _n , and the output of the channel counter CTR is written in the time slot ti. When tb is indicated, it is read out and sent to outgoing highway OHW _n .

When the network is disconnected, the address information ta and tb of the time switch control memories TSM ₁ and TSM _n are erased by the conventional common control device, so no call information is written to the address tb of the path memory SPM _n . , and the call information immediately before the network was disconnected will remain. However, in the present invention, since a no-call signal pattern is generated and written from the variable transmission loss insertion and no-call signal pattern generator, what is read by the output of the channel counter CTR is the residual data. Instead, it becomes a no-call signal pattern, and after writing, the control signal prohibits writing to that address, so the address information of time switch control memories TSM ₁ and TSM _n
It is no longer necessary to erase ta and tb.

FIG. 2 is a block diagram of the main parts including the variable transmission loss insertion and no-call signal pattern generator PADG, where HWin is the input highway corresponding to the intermediate highway in FIG. 1, PAD is the variable transmission loss insertion device,
PG is a no-call signal pattern generator, DL is a delay circuit, and SPM is the path memory SPMB ₁ to SPMB _n in Figure 1.
Path memory corresponding to , HW _put is out highway,
G is a gate, PM is a control memory, CM is an address holding memory corresponding to time switch control memory TSM ₁ to TSM _n , CTR is a channel counter,
SEL _a , SEL _b are address selectors, CC is common control device, AD is address information, DT is data, WE
is the path memory write signal.

FIG. 3 is a block diagram of an example of the variable transmission loss insertion and no-call signal pattern generator PADG, where HWin is the input highway, ROM ₁ and ROM ₂ are
For example, read-only memory stores output information corresponding to input information so as to give attenuation of -3 dB and -7 dB to call information, PG is a no-call signal pattern generator, SEL is a selector, DEC is a decoder, A ₀ ~ A ₃ is AND circuit, OR is OR circuit, #0
~ #3 is the terminal, (PM), (DL), (SPM)
indicate that they are connected to the control memory PM, delay circuit DL, and path memory SPM, respectively.

Control signal from control memory PM is sent to selector SEL
is decoded by a decoder DEC, and one of the AND circuits A ₀ to _{A 3} is selected. For example, when the decode output is applied to the AND circuit A ₃ , it means that the #3 terminal is selected, and the call information is passed through the AND circuit A ₃ and the OR circuit OR to the path memory SPM without being attenuated. is input. Also, when the decode output is applied to the AND circuit A ₁ , the #1 terminal is selected, and the call information is attenuated by 7 dB by the read-only memory ROM ₂ , and then sent to the AND circuit A ₁ and the OR circuit OR.
is input to the path memory SPM via Also, when the decoded output is added to the AND circuit A ₀ ,
The #0 terminal is selected, and the no-call signal pattern from the no-call signal pattern generator PG is input to the path memory SPM via the AND circuit A ₀ and the OR circuit OR, and is decoded at that time. The output is output as a control signal and the delay circuit
Added to DL.

The control memory PM is written with attenuation specification data corresponding to each time slot from the common control device CC.
The address holding memory CM is also written with the write address of the path memory SPM from the common control device CC, and is read out by the output of the channel counter CTR. Address selector SEL _a , SEL _b
is used to switch between the address when writing data from the aforementioned common control device CC and the address of the output of the channel counter CTR when reading.

When disconnecting the network, first the control memory PM is rewritten under control from the common control unit CC. For example, if a call is being made at time slot ti of input highway HWin, a selector for specifying the amount of attenuation is placed in the address corresponding to time slot ti of control memory PM.
The terminal information of SEL #1 to #3 is written,
When disconnecting the network, this terminal information is rewritten to #0. and time slot ti
is read out and added to selector SEL.
In this selector SEL, the #0 terminal is selected by being decoded by the decoder DEC. That is, the decoded output is added to the AND circuit _A0 . Then, the decoded output becomes a control signal and is applied to the delay circuit DL. This delay circuit DL has a delay time of one frame.

Also, the write signal WE is applied to the path memory SPM via the gate G for each time slot, and call information is written to the address of the path memory SPM according to the address information from the address holding memory CM. As mentioned above, when the #0 terminal of the selector SEL is selected in the time slot ti, the no-call signal pattern from the no-call signal pattern generator PG is added to the path memory SPM, and at this time the control signal from the selector SEL is added to the path memory SPM. is not set as an inhibit input to gate G by delay circuit DL, so a no-call signal pattern is written to the address read from address holding memory CM at time slot ti of path memory SPM. From the next frame onwards, the output of the delay circuit DL at time slot ti becomes "1" by the control signal.
Therefore, writing WE is prohibited by gate G, and the path memory in that time slot ti
Writing to SPM is prohibited. Therefore, the information read by the output of the channel counter CTR becomes a no-call signal pattern, and after the aforementioned no-call signal pattern is written, the network is disconnected.

The above embodiment is a variable transmission loss insertion device PAD
Although the no-call signal pattern is added to the path memory SPM using the selector SEL, the no-call signal pattern generator PG may be provided independently.

As explained above, the present invention writes the no-call signal pattern for only one frame into the path memory SPM when the network is disconnected, and the remaining data when the network is disconnected becomes the no-call signal. Therefore, even if the signal is decoded by the decoding circuit, there will be no possibility that the signal will become a DC high level signal, and therefore network switching noise will also be reduced. Also, only the control order of the disconnection control circuit, that is, the control memory from the common control device CC in the embodiment
By simply rewriting the PM, a no-call signal pattern is written, and a control signal delayed by one frame by the delay circuit DL prohibits writing to the address of the path memory SPM where the no-call signal pattern was written. It is possible to prevent noise from occurring when the network is disconnected.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a time division switch according to an embodiment of the present invention, Fig. 2 is a block diagram of main parts of an embodiment of the present invention, and Fig. 3 is a block diagram of a variable transmission loss insertion and no-call signal pattern generator. FIG. 3 is an example block diagram. TS ₁₁ to _{TS 1n} are primary time switches, SS is a spatial switch, TS ₂₁ to _{TS 2n} are secondary time switches,
PADG ₁ to _{PADG n} are variable transmission loss insertion and no-call signal pattern generators, PAD is variable transmission loss insertion device, PG is no-call signal pattern generator, DL
is a delay circuit, SPM is a path memory, PM is a control memory, CM is an address holding memory, CTR is a channel counter, and SEL _a and SEL _b are address selectors.

Claims (1)

[Claims] 1. In a time-division exchange equipped with a time switch having a path memory for writing and reading call information by random writing and sequential reading on the outgoing side, a no-call signal pattern generator;
A delay circuit is provided to delay the control signal by one frame when the no-call signal pattern generating device is specified, and when the network is disconnected, the no-call signal pattern generating device is specified and the no-call signal pattern is transmitted to the call information. , and the control signal delayed by the delay circuit prohibits writing to the address of the path memory to which the no-call signal pattern was written in subsequent frames. Work cutting method.