JPS6212920B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a drive circuit for a liquid crystal display device that displays multi-digit information in two stages, upper and lower. Traditionally, electronic desktop calculators (hereinafter referred to as calculators)
Generally, the liquid crystal display device used in
As shown in the figure, a liquid crystal 3 is interposed between two glass substrates 1 and 2, a counter electrode 4 made of aluminum or the like is provided on the inner surface of one glass substrate 1, and segment electrodes a, 2 are provided on the other glass substrate 2. b, c,...
...H was provided, and characters such as numbers were displayed by applying a voltage between the electrodes. When displaying character information such as multi-digit numbers using such a liquid crystal display device, as shown in FIG. 1b, segment electrodes a, b, The electrodes c, d, e, f, g and the decimal point electrode h are formed of a transparent conductive material such as indium oxide for the number of display digits, and the same segment electrodes are commonly connected and drawn out. Further, on the other glass substrate 1, counter electrodes 4 for each digit are formed so as to face the segment electrodes. In such a liquid crystal display device, the lead lines of the segment electrodes cannot be drawn out without crossing the mutual connection lines, so it is necessary to provide multilayer wiring in the printed wiring. Furthermore, recently, in order to reduce the number of steps required for such multilayer wiring, a structure in which the counter electrode is formed into a segment shape, as shown in FIG. 1c, has been proposed. A liquid crystal display device configured in this manner is generally used as a display device for calculators, etc., and the liquid crystal display device usually has display elements of 8 to 12 digits arranged in a line.
Because it is time-divisionally displayed, only one piece of information can be displayed at the same time. Therefore, for example, when calculating "A x B", if you key in the numerical information "A", the numerical information "A" will be displayed on the liquid crystal display, and then key input in the order of "x" → "B". Then, when the numerical information "B" is input, the numerical information "A" is stored in a predetermined storage device, the display of "A" is erased, and the numerical information "B" is displayed on the liquid crystal display device. Ta. However, in recent years, there has been a demand for calculators that also have functions for practicing calculations for schoolchildren, etc., and such calculators require all calculations such as numerical information and operation symbols of calculation formulas, such as "A x B". It is preferable to display the formula on a display device, but it is preferable to display the formula on a display device.
A liquid crystal display device with digits arranged in a single row cannot perform this function. Therefore, it is conceivable to simply arrange two identical liquid crystal display devices one above the other and display the operands and operands on the top and bottom, respectively, but if you do this, the electrodes of the liquid crystal display device Since the number of lead lines is twice that of the conventional display device, the control circuit thereof is also required twice as much as that of the conventional display device, which increases the cost of the device itself and causes a decrease in reliability. Another method is to form the upper and lower display devices in one piece and connect the same segments in common.
Although it is possible to reduce the number of terminals mentioned above,
If the same segment electrodes in the lower row are connected, the electrode for connecting the opposing electrode and the electrode for connecting the segment electrodes will intersect at a position other than the segment electrodes. Therefore, connect the connecting terminals of the liquid crystal display device in the same direction. As a result, connection terminals must be provided on both sides of the display device, and the number of terminals cannot be reduced significantly. Therefore, in order to eliminate the above-mentioned conventional problems when performing upper and lower two-stage display using a liquid crystal display device, the present invention provides display segment electrodes arranged in the upper and lower two stages. A counter electrode facing the segment electrode via a liquid crystal is also formed in a segment shape,
The wiring structure of these segment electrodes and counter electrodes is such that the respective connections do not intersect and each connection terminal can be pulled out in the same direction, and a drive circuit that satisfactorily drives a liquid crystal display device having such a wiring structure. It provides: The present invention will be explained in detail below with reference to the drawings. Second
Figures a and b show an example of a wiring structure of a display device in which upper and lower display devices are integrally formed according to the present invention.
However, the display device shown in FIGS. 2a and 2b is a display device of an electronic desktop calculator equipped with a calculation practice function, and an electrode "〓" for displaying operation symbols is located in front of the numerical information display section. Figure a shows the connection structure of segment electrodes,
Segment electrodes a to h arranged in the upper and lower two stages are formed on the surface of the glass substrate using a transparent metal thin film such as indium oxide by vapor deposition and photoetching for each digit of the upper and lower stages. There is. The connection terminals of the display segment electrodes formed in this manner are commonly connected to the upper and lower rows, and are divided into four groups and drawn out for each digit. Specifically, the upper b, c, h segments and the lower h segment are the first group A, the upper g, d segments and the lower a, b segments are the second group B, and the upper a , f segments and the lower e and d segments are connected as a fourth group D, and the upper e segment and the lower f, g, and c segments are connected as a third group C. Figure b shows the connection structure of the counter electrodes, and the segment-shaped counter electrodes a to h arranged in the upper and lower stages are made of a transparent metal film such as indium oxide or aluminum on the surface of the rear glass substrate. A metal film for electrodes is formed by a vapor deposition method or a printing method, and this counter electrode is coated on the surface of the glass substrate so as to cover the display segment electrode portions of all digits. The connection terminals of the counter electrodes formed in this manner are laterally divided into four groups and drawn out. Specifically, the upper stage a, b, e, and g segments are the first group _H1 , and the upper stage c,
The d, f segments and the lower f segment are the second group _H2 , the upper h segment and the lower a, e, g segments are the third group _H3 , and the lower b, c, d, h segments The opposite electrodes of each digit are connected as a fourth group _H4 . FIG. 3 is a block diagram of a control circuit in a drive circuit according to the present invention for driving a liquid crystal display device connected as described above. In the figure, 5 is a register for upper display, 6 is a 4-bit buffer for upper display, 7 is a decoder for upper display, 8 is a register for lower display,
9 is a 4-bit buffer for lower display, 10 is a decoder for lower display, 11 _{A to D} are OR gates, 12 _{A to D}
13 is a display buffer register, 13 _{A to D} are segment drivers, 14 is a binary counter that generates signals α and β that control the generation of upper and lower segment electrode group selection signals, 15 is a counter electrode selection signal generation circuit, A to D are selection signals for selecting the segment electrode groups, _A1 to _A6 , _B1 to _B6 , _C1 to _C6 ,
D ₁ to _{D 6} are selection signals for selecting the first to fourth groups of the segment electrodes described above corresponding to the respective digits. The contents of the upper and lower display registers 5 and 8 are 4-bit buffers 6 and 9 and decoders 7 and 10.
Segment electrode group selection signals A to D via
is converted to This conversion is performed based on the signal information of α and β. In this case, upper display register 5
The contents of are decoded by the upper display decoder 7, and the contents of the lower display register 8 are decoded by the lower display decoder 10, and then through OR gates _11A to _11D ,
The signals are input to and stored in the respective buffer registers _12A to _12D . The above buffer register 12 _A ~
The segment electrode group selection signals of each digit stored in _12D are sent to segment drivers _13A to 1.
_3D and converted into voltages that are actually applied to each segment electrode. The binary counter 14 generates the α and β signals and at the same time is inputted as a reference signal to the counter electrode selection signal generation circuit 15, which generates the first to fourth group selection signals H ₁ to H ₄ of the counter electrodes. In this embodiment, the upper and lower display decoders 7 and 10 select the numerical information of the 4-bit buffers 6 and 9 for each of the first to fourth groups of segment electrodes, as shown in Tables 1 and 2 below. Signals A, B,
Convert to C and D and output.

【table】

[Table] The above Tables 1 and 2 show the results of the first to fourth groups of segment electrodes at the time when the first to fourth groups H ₁ to H ₄ of counter electrodes formed in a segment shape are occurring. This indicates that when (A to D) are input and stored in the buffer registers _12A to _12D under the conditions shown in Tables 1 and 2, a desired number (0 to 9) can be displayed. Based on the time chart in Figure 4 below, “1
We will explain how to display the numerical value "1" on the upper display section and the numerical value "2" on the lower display section when calculating "+2". First, use the key input means (not shown) to display the numerical value "1". When inputted, the code "0001" of numerical value "1" is inputted to the upper display register 5, and is simultaneously introduced into the 4-bit buffer 6.
The numerical information introduced into the 4-bit buffer 6 is input to the upper display decoder 7, which generates segment electrode group selection signals A to D in accordance with the binary signals α and β. This upper stage display decoder 7 selects the first group of counter electrodes at the time "" in FIG. 4 according to Table 1. Information A ₁ of the display segment electrode group to be displayed at the time H ₁ is selected.
=1, _A2 to _A6 =0 to the buffer register _12A via the OR gate _11A , _B1 to _B6 =0 to the buffer register _12B via the OR gate _11B ,
C ₁ to C ₆ = 0 is sent to the buffer register 12 _C via the OR gate 11 _C , and D ₁ to _{D 6} = 0 is sent to the OR gate 11.
It is stored in the buffer register _12D via _D.
In this way, the display information is stored in the buffer registers 12 _{A to D} , and the b segment in the _first digit (left end) in the upper row of FIG. indicate. In addition _{, the} second group of _counter electrodes is selected at time "" in _{FIG .} buffer register 12 _A
Then, B ₁ to B ₆ =0 are sent to the buffer register 12 _B via the OR gate 11 _B , C ₁ to C ₆ =0 are sent to the buffer register 12 _C via the OR gate 11 _C , and D ₁ to
D ₆ =0 is stored in the buffer register _12D via the OR gate _11D . and the second counter electrode
At time H ₂ to select the group of , display the c segment in the first digit (left end) in the upper row of Figure 2 a. In addition, the third group of counter electrodes is selected at the time "" _{in FIG .
H3} to store in the buffer registers _12A to _12D and select the third group of counter electrodes via H3.
The information will be displayed at the time of . Process the signals sequentially as described above to display the numerical value "1" on the upper display section, then input the addition instruction key "+" to display "+" on the operation symbol display section shown in Figure 2.
Show symbols. Next, when numerical information "2" is input, the code "0010" for the numerical value "2" is input to the lower display register 8, and at the same time, the code "0010" is input to the 4-bit buffer 6 and the information "0010" is input to the lower display decoder 10. is input, and the segment electrode group selection signal A~
Generates D. In this decoder 10, the second
According to the table, the information "0010" is decoded at the time "", and A ₁ to A ₆ = 0, B ₁ to B ₆ = 0, C ₁ to _{C 6} =
0, D ₁ to D ₆ =0 respectively to OR gate 11 _A to 1
_1D , and stored in buffer registers _12A to _12D . Similarly, A ₁ to A ₆ at time “”
= 0, B ₁ = 1・B ₂ ~ _{B 6} =0, C ₁ =1・C ₂ ~ _{C 6} =
0, D ₁ = 1・D ₂ to _{D 6} = 0 are stored in the buffer registers 12 _A to 12 _D in the same way as above, and at the time
A ₁ to _{A 6} = 0, B ₁ = 1・B ₂ to _{B 6} = 0, C ₁ to _{C 6} =
0, D ₁ = 1・D ₂ to _{D 6} = 0 as buffer register 1
_2A to _12D . In this way, each segment electrode group selection signal stored in the buffer registers _12A to _12D is applied between the counter electrode selection signals _H1 to _H4 , resulting in a numerical value "2" being displayed. In this embodiment, the decoder 7 does not decode at the timing of "", and the decoder 10 does not decode at the timing of "". Furthermore, in the above-mentioned embodiments, only the division of segment electrodes and counter electrodes as shown in FIG. Any pattern may be formed as long as it does not intersect or pass between mutual segment electrodes. According to the present invention described in detail above, when a two-stage liquid crystal display device is used in electronic equipment, the control circuit can be configured with approximately half the number of circuits compared to a conventional two-stage liquid crystal display device. Therefore, cost reduction can be achieved.

[Brief explanation of the drawing]

FIGS. 1A, 1B, and 1C are diagrams showing the structure of a conventional liquid crystal display device. FIG. 2 is a diagram showing essential parts of a two-stage display liquid crystal display device according to the present invention. FIG. 3 is a block diagram of the control circuit of the drive circuit of the two-stage display liquid crystal display device of the present invention, and FIG. 4 is a time chart of the main parts of the control circuit. a, b, c, d, e, f, g: segment electrodes, A to D: display segment electrode group selection signal,
_H1 to _H4 : Counter electrode group selection signal.

Claims (1)

[Claims] 1 A two-row multi-digit numerical segment electrode consisting of two rows, an upper row and a lower row, in which a numerical segment-shaped electrode is arranged in each digit, and a numerical segment-shaped electrode arranged in a position opposite to the two-row multi-digit numerical segment electrode. A numerical segment electrode formed by dividing two rows of multi-digit opposing electrodes consisting of electrodes and the corresponding numerical segment electrodes of the upper and lower rows of the two rows of multi-digit numerical segment electrodes into four groups for each digit in the vertical direction and connecting them by wiring. A drive circuit for a liquid crystal display device comprising a wiring means and a counter electrode wiring means formed by dividing the upper and lower counter electrodes of the two-row multi-digit counter electrode into four groups in the horizontal direction and connecting them by wiring, An upper display register that stores numerical information to be displayed on the upper display section, and any one-digit numerical information stored in the upper display register is input and output as a 4-bit segment electrode group selection signal. A decoder for upper display, a register for lower display that stores the numerical information to be displayed on the lower display, and an arbitrary one-digit numerical information stored in the lower display register is inputted and a 4-bit A lower display decoder that outputs a segment electrode group selection signal, four types of OR gates to which corresponding output lines of the upper display decoder and the lower display decoder are connected in pairs, and the four types of OR gates. four types of buffer registers that store respective output information signals, a segment driver that converts the information signals stored in the four types of buffer registers into voltage signals for driving the liquid crystal, and the two-row multi-digit opposing electrodes. a timing signal generation circuit that supplies four types of timing signals to four groups of connection wirings connecting the two groups; and a timing signal generating circuit that supplies four types of timing signals to four groups of connection wirings connecting the two groups, and decodes both the upper display decoder and the lower display decoder according to a signal related to the timing signal. 1. A driving circuit for a liquid crystal display device, comprising: selective decoding control means.