JPS6213638B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer that generates a control signal to turn on or cut off power to a load at any desired time.

An electrical device equipped with this type of timer, such as a coffee extractor, sends a control signal when the stored time, which is arbitrarily set and stored in the timer storage section by operating a time setting switch, and the counted time counted by the clock section match. The configuration is such that a drive command signal is generated and the coffee extraction operation is started based on this, but even when there is no need to perform the coffee extraction operation, the drive command signal is generated every time the counted time of the clock unit matches the memorized time. There are some defects that may occur. For this reason, conventionally, an operation switch is provided to enable and disable the drive command signal, but when the operation switch is set to the enable state, if the time setting switch is touched by mistake, the timer is turned off. When the time stored in the storage unit changes, a problem arises in that a drive command signal is not generated at a desired time, but a drive command signal is generated at an unexpected time and the coffee extraction operation is performed.

The present invention has been made in view of the above circumstances, and its purpose is to prevent the occurrence of a control signal even if the time stored in the time storage section changes due to the fact that the time setting switch is touched by mistake and a control signal is generated at an unexpected time. The purpose is to provide a timed device that can be disabled.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a coffee extractor will be described below with reference to the drawings.

1 is a 100 volt, 60 Hz single-phase AC power supply, and a series circuit consisting of an electric heater 2 serving as a load of a hot water supply system, a thermal switch 3, and a normally open contact 4a of a drive circuit 4 is connected between both terminals of the power supply. ing. In this case, the hot water supply mechanism includes a water storage tank and a heater that is supplied with water from the water storage tank and heated by the electric heater 2 to generate hot water, and the hot water generated by the heater is heated to its boiling pressure. The coffee liquid is extracted by supplying hot water into the case and is stored in a bottle placed on the heater. It is becoming more and more common. Further, the thermal switch 3 is configured to turn on and off by sensing the temperature of the heater.

Now, 5 is a timer, which will be explained below. This timer 5 is constructed by a microcomputer, but for convenience of explanation, it is shown in a block diagram for each function in FIG. Reference numeral 6 denotes a frequency dividing circuit whose input terminals are connected to both terminals of the single-phase AC power supply 1, which shapes, for example, a positive half wave of the single-phase AC power supply voltage into a rectangular wave, and divides the frequency of the rectangular wave. Then, one high-level clock pulse _P6 is sequentially outputted from the output terminal every second. Reference numeral 7 designates a clock setting switch, which, when pressed, is turned on only while the switch is being pressed to generate a high-level clock setting signal _S7 . Reference numeral 8 designates a time limit setting switch, which, when pressed, is turned on only while the switch is being pressed to generate a high-level time setting signal _S8 . 9
is a time setting switch,
When this is pressed, it is turned on only while the pressing operation is being performed, and generates a setting signal _S9 when it is at a high level. Reference numeral 10 denotes a minute setting switch which is a time setting switch, and when pressed, it is turned on only while the pressing operation is being performed to generate a high-level minute setting signal _S10 . The clock setting signal S ₇ , time limit setting signal S ₈ , hour setting signal S ₉ and minute setting signal S ₁₀ are applied to a preset input terminal PR of a subtraction counter 12 via an OR circuit 11.
In this subtraction counter 12, the data input terminal
The numeric signal _S13 of "5" from the numeric storage section 13 is given to DI, the output pulse of the AND circuit 14 is given to the clock pulse input terminal CK, and the data output terminal DO
A data output signal _S12 indicating the count contents from 1 is applied to an input terminal of a zero detection circuit 15. This zero detection circuit 15 outputs a data output signal.
When the content of _S12 is "0", a high level zero detection signal _S15 is generated. The AND circuit 14 has a first input terminal supplied with a clock pulse P ₆ and a second input terminal supplied with a clock setting signal S ₇ , a time limit setting signal S ₈ , an hour setting signal S ₉ and a minute setting signal S _{10 .} is applied via the OR circuit 11 and the inverter circuit 16, and the zero detection signal _S15 is applied to the third input terminal via the inverter circuit 17, and the signals _S7 , _S8 , S ₉ ,
Clock pulse when S ₁₀ and S ₁₅ are not present
It is designed to pass P ₆ as an output pulse. The subtraction counter 12 also receives a clock setting signal via an OR circuit 11 to a preset input terminal PR.
S ₇ , time limit setting signal S ₈ , hour setting signal S ₉ , and minute setting signal S ₁₀ are given, the numerical content "5" of the numerical signal S ₁₃ in the numerical storage section 13 is preset. AND circuit 1 is connected to the clock pulse input terminal CK.
Each time a clock pulse _P6 is applied via P4, a subtractive counting operation is performed. 1
8 is a display type storage circuit whose input terminals Ia,
Trigger pulses from trigger circuits 19, 20 and 21 are applied to Ib and Ic, respectively.
This trigger circuit 19 has a zero detection signal S ₁₅ at its input terminal.
When the clock setting signal S7 is applied to the input terminal, the trigger circuit 20 generates one high-level trigger pulse from the output terminal when the clock setting signal _S7 is applied to the input terminal. The trigger circuit 21 is configured to generate one high-level trigger pulse from its output terminal when the time limit setting signal _S8 is applied to its input terminal. Then, when a trigger pulse is applied to the input terminal Ia, the display type storage circuit 18 memorizes the constant clock display state and generates a high-level constant clock display signal S ₁₈ a from the output terminal Oa. When a trigger pulse is applied to Ib, it remembers that it is in the temporary clock display state and generates a high-level temporary clock display signal _S18b from the output terminal Ob, and when a trigger pulse is applied to the input terminal Ic, it enters the time display state. , and output a high-level time display signal from the output terminal Oc.
S ₁₈ c. 22 is a clock part, which is "1", "2", "3",...
A 24-decimal hour counter 23 that counts from "1" to "24" such as "24" and "1" and "0",
A sexagesimal division counter 24 that counts from "0" to "59" like "1", "2", ... "59", "0"
and a seconds counter 25. Then, the hour counter 23 receives the output pulse of the AND circuit 26 via the OR circuit 27 to the clock pulse input terminal CK, and receives the carry pulse P ₂₄ from the output terminal Oa of the minute counter 24 to perform addition counting. The clock signal _S23 indicating the counting contents is outputted from the output terminal O. In this case, the AND circuit 26
is such that the temporary clock display signal S ₁₈ b is applied to the first input terminal, the hour setting signal S ₉ is applied to the second input terminal, and the clock pulse P ₆ is applied to the third input terminal. Thus, when both the temporary clock display signal _S18b and the hour setting signal _S9 are applied, the clock pulse _P6 is passed as an output pulse. Further, the minute counter 24 receives the output pulse of the AND circuit 28 via the OR circuit 29 to the clock pulse input terminal CK, and receives the carry pulse from the output terminal O of the seconds counter 25.
P ₂₅ is given to perform an addition counting operation, and a minute counting signal S ₂₄ indicating the counting content is output from the output terminal Ob, and when the counting content changes from "59" to "0", The high-level carry pulse _P24 is outputted from the output terminal Oa. In this case, the AND circuit 28 is
A temporary clock display signal S ₁₈ b is applied to the first input terminal, a minute setting signal S ₁₀ is applied to the second input terminal, and a clock pulse P ₆ is applied to the third input terminal; When both the temporary clock display signal _S18b and the minute setting signal _S10 are applied, the clock pulse _P6 is passed as an output pulse. Further, the seconds counter 25 performs an addition counting operation when a clock pulse _P6 is applied to the clock pulse input terminal CK, and when the count changes from "59" to "0", the second counter 25 receives a signal from the output terminal O. 1 high level carry pulse
It is designed to output P ₂₅ . In addition, each clear terminal of the hour counter 23 and minute counter 24
CL is supplied with a high-level initialization signal _S30 from the initialization circuit 30, and when the hour counter 23 is supplied with the initialization signal _S30 , the count content is cleared to "1". , the division counter 24 is cleared so that its count becomes "0" when the initialization signal _S30 is applied. Further, the clock setting signal S ₇ and the initialization signal S ₃₀ are applied to the clear terminal CL of the second counter 25 via the OR circuit 31, and the second counter 25 receives the clock setting signal S ₇ and the initialization signal S 30 via the OR circuit 31. No matter which signal _S30 is applied, the counted contents are cleared to "0". In this case, the initialization circuit 30 outputs a high-level pulse-like initialization signal _S30 at the moment when the timer 5 is powered on. The clock signal S 23 of the hour counter ₂₃ and the minute count signal S 24 of the minute counter ₂₄ are applied to the input terminals Ia and Ib of the display 34 through transfer gate circuits 32 and 33, respectively. It has become
Further, a constant clock display signal S ₁₈ a and a temporary clock display signal S ₁₈ b are both applied to each gate terminal of the transfer gate circuits 32 and 33 via an OR circuit 35. In addition, the display device 34
As shown in FIG. 2, it is composed of a segment-type digital display. 36 is a time storage section, which stores "1", "2", "3", . . .
A 24-decimal hour counter 37 that counts from “1” to “24” such as “24” and “1” and “0”;
A sexagesimal division counter 38 that counts from "0" to "59" like "1", "2", ... "59", "0"
In particular, the hour counter 37 is configured to be able to store "0". The hour counter 37 performs an addition counting operation when the output pulses of the AND circuits 39 and 40 and the carry pulse P 38 from the output terminal Ob of the division counter ₃₈ are applied to the clock pulse input terminal CK via the OR circuit 41. A storage signal _S37 is output from the output terminal O when the counting contents, that is, the storage contents are indicated. Further, the division counter 38 is configured to perform an addition counting operation by receiving the output pulse of the AND circuit 42.
Minute memory signal S ₃₈ indicating the counting content, that is, the memory content
is output from the output terminal Ob, and one high-level carry pulse _P38 is output from the output terminal Oa each time the stored content changes from "59" to "0". 43 is a zero detection circuit which is an absent time detection section, and this has a time storage signal at its input terminal.
_S37 is applied, and when the content of the storage signal _S37 becomes "0", a high level zero detection signal _S43 is output from the output terminal. In the above case, the AND circuit 39
has a time display signal S ₁₈ c applied to its first input terminal, a time setting signal S ₉ applied to its second input terminal, and
The clock pulse _P6 is applied to the third input terminal, and when the time display signal _S18c and the hour setting signal _S9 are both applied, the clock pulse _P6 is applied to the third input terminal.
is designed to pass as an output pulse. Further, the AND circuit 42 has a first input terminal supplied with a time display signal _S18c , a second input terminal supplied with a minute setting signal _S10 , and a third input terminal supplied with a clock pulse _P6 . It is designed to pass the clock pulse _P6 as an output pulse when both the time display signal _S18c and the minute setting signal _S10 are applied. Further, the AND circuit 40 receives a zero detection signal at a first input terminal.
S ₄₃ is applied via the delay circuit 44, and the clock pulse P ₆ from the AND circuit 42 is applied to the second input terminal.
is given, and the zero detection signal S ₄₃
When the clock pulse P6 is given, the clock pulse _P6 is passed as an output pulse. The hour storage signal S 37 from the hour counter ₃₇ and the minute storage signal S _{38 from the minute counter 38} are sent to input terminals Ia and Ib of the display 34 through transfer gate circuits 45 and 46, respectively. The transfer gate circuit 4
Each of gate terminals 5 and 46 receives the time display signal.
S ₁₈ c is now being given. Further, a clock count signal S ₂₃ and a minute count signal from the clock section 22
S ₂₄ is the input terminal Ia and the comparison circuit 47 which is the comparison section.
Ib, and the hour storage signal S ₃₇ and minute storage signal S ₃₈ from the time limit storage section 36 are applied to the comparison circuit 4.
7 input terminals Ic and Id, respectively, and the comparator circuit 47 outputs the counted contents of the clock signal S ₂₃ and the minute counting signal S ₂₄ and the stored contents of the hour storage signal S ₃₇ and the minute storage signal S ₃₈ . When they match, a high-level drive command signal, which is a control signal, is output from output terminal O.
It is designed to output S ₄₇ . Further, this drive command signal _S47 is applied to the first input terminal of an AND circuit 48, and the second input terminal of the AND circuit 48 is connected to the set output of a flip-flop circuit 49, which is a state storage circuit. The allowable signal _S49 , which is a high-level set output signal from the terminal Q, is given, and the AND circuit 48 validates this when the drive command signal _S47 is given while the allowable signal _S49 is given. The high-level output signal is generated and applied to the set input terminal S of the flip-flop circuit 50. When this flip-flop circuit 50 receives a high-level output signal from the AND circuit 48 to the set input terminal S, it is inverted to the set state and outputs a drive signal S ₅₀ as a high-level set output signal from the set output terminal Q. It's summery. This drive signal S ₅₀ is applied to the input terminal of the drive circuit 4, and the drive circuit 4 operates while the drive signal S ₅₀ is applied to turn on the normally open contact 4a. It's getting old.
The flip-flop circuit 50 is reset by receiving a high-level stop signal _S51 from a stop switch 51 to its reset input terminal R, and when the stop switch 51 is pressed, it is reset. It is designed to turn on and output a high-level stop signal _S51 only while the switch is running. On the other hand, the output signal of the AND circuit 52 is applied to the set input terminal S of the flip-flop circuit 49.
The zero detection signal _S43 is applied to the first input terminal via the inverter circuit 53, the time display signal _S18c is applied to the second input terminal, and the operating switch 54 is applied to the third input terminal. A high level operation signal _S54 is given, and when there is no zero detection signal _S43 and both the time display signal _S18c and the operation signal _S54 are given, a high level output is generated. The flip-flop circuit 49 outputs a signal.
is applied to the set input terminal S of the flip-flop circuit 49, thereby inverting the flip-flop circuit 49 to the set state. In this case, when the operation switch 54 is pressed, it is turned on only while it is being pressed and outputs a high-level operation signal _S54 . Further, the output signal from the AND circuit 55 and the clock pulse P ₆ from the AND circuits 39 and 42 are applied to the reset input terminal R of the flip-flop circuit 49 via an OR circuit 56. The zero detection signal _S43 is applied to its first input terminal via the OR circuit 57, and the time display signal _S18c is applied via the inverter circuit 58 and the OR circuit 57, and the second The operation signal _S54 is applied to the input terminal, and the high level is reached when the zero detection signal _S43 and the operation signal _S54 are present, and when there is no time display signal _S18c and the operation signal _S54 is present. It is designed to output an output signal. And the flip-flop circuit 49 is
The high level output signal from the AND circuit 55, the clock pulse _P6 from the AND circuit 39, or the clock pulse _P6 from the AND circuit 42 is sent to the OR circuit 5.
When given through 6, it flips to the reset state;
The output of the permission signal _S49 is then stopped and the drive command signal _S47 is invalidated. Incidentally, the permission signal _S49 of the flip-flop circuit 49 is also applied to a dot indicator 59 disposed close to the indicator 34, as shown in FIG.
The point indicator 59 lights up when the permission signal _S49 is given.

Next, the operation of this embodiment will be explained.

First, when power is applied to the timer 5, the initialization circuit 30 operates and generates an initialization signal.
This initialize signal _S30 is now given to each clear terminal CL of the hour counters 23, ₃₇ , minute counters 24, 38, and seconds counter 25, and the hour counter 2
3 is cleared to "1", and the remaining counters 24,
25, 37 and 38 are cleared to "0". Therefore, at this time, when the time setting switch 8 is pressed and turned on to output the time setting signal S8, this is applied to the trigger circuit ₂₁ , and the trigger circuit 21 sends the trigger pulse to the display type storage circuit 18. The display type storage circuit 18 stores the timed display state and outputs the timed display signal S ₁₈ c from the output terminal Oc. And this timed display signal S ₁₈ c
is applied to the gate terminals of the transfer gate circuits 45 and 46, so the transfer gate circuits 45 and 46 are turned on, and the time storage section 3
6, the hour storage signal S 37 of the hour counter ₃₇ and the minute storage signal S ₃₈ of the minute counter 38 are sent to the display 34 via transfer gate circuits 45 and 46.
As shown in _{FIG .} "0:00" (0:00) is displayed.
On the other hand, the time limit setting signal S8 generated by pressing the time limit setting switch ₈ is applied to the preset input terminal PR of the subtraction counter 12 via the OR circuit 11.
The numerical content "5" of the numerical signal _S13 from 3 is preset. After that, when the pressing operation of the time limit setting switch 8 is released and the time limit setting signal _S8 disappears,
The output signal of the inverter circuit 16 becomes high level, and since the count content of the subtraction counter 12 is "5" at this time, the zero detection circuit 15 does not output the zero detection signal _S15 , and the output signal of the inverter circuit 17 becomes a high level, and therefore, the clock pulse _P6 generated from the frequency divider circuit 6 at a rate of one per second
is now applied to the clock pulse input terminal CK of the subtraction counter 12 via the AND circuit 14, and the subtraction counter 12 outputs "4", "3", "2", . . .
A subtraction operation will be performed as shown below. Thereafter, when the count content of the subtraction counter 12 becomes "0", that is, when 5 seconds have passed since the time limit setting signal _S8 disappears, the zero detection circuit 15 starts outputting the zero detection signal _S15 . Then, the output signal of the inverter circuit 17 becomes low level, and the AND circuit 14 stops passing the clock pulse _P6 , and the subtraction counter 12 stops the subtraction operation with the count content being "0". Also, since the zero detection signal _S15 is given to the trigger circuit 19, the trigger circuit 19 comes to give a trigger pulse to the input terminal Ia of the display type storage circuit 18, and the display type storage circuit 18 is always in the clock display state. This time, the constant clock display signal _S18a is outputted from the output terminal Oa. This constant clock display signal _S18a is given to each gate terminal of the transfer gate circuits 32 and 33 via the OR circuit 35.
is turned on, and the clock signal S ₂₃ of the hour counter 23 and the minute counter 24 in the clock section 22 are activated.
The minute counting signal S ₂₄ is sent to the input terminal Ia of the display 34 and
As shown in _{FIG .}
"AM1:00" (1:00 a.m.) is displayed.

A case in which the time display on the display 34 is set to the current time (for example, 10:15 a.m.) will now be described.
When the clock setting switch 7 is pressed and turned on to output the clock setting signal _S7 , this clock setting signal _S7 is applied to the preset input terminal PR of the subtraction counter 12 via the OR circuit 11 to perform the subtraction. The counter 12 is now preset to "5", and the time setting signal _S7 is sent to the trigger circuit 2.
0, the trigger circuit 20 begins to apply a trigger pulse to the input terminal Ib of the display type storage circuit 18, and the display type storage circuit 18 temporarily stores the clock display state and outputs the trigger pulse from the output terminal Ob. Temporary clock display signal _S18b will be output.
This temporary clock display signal S ₁₈ b is the OR circuit 3
5 to each gate terminal of the transfer gate circuits 32 and 33, the display 34 displays the count contents of the clock count signal S ₂₃ and the minute count signal S ₂₄ in the clock section 22 in the same manner as described above. I will do it. Further, the clock setting signal _S7 is sent to the clear terminal of the seconds counter 25 via the OR circuit 31.
Since the second counter 25 is given to CL, the second counter 25 is cleared to "0". After that, release the pressing operation on clock setting switch 7 and press minute setting switch 1 instead.
When the minute setting signal _S10 is output by pressing 0 and turning it on, this minute setting signal _S10 is applied to the preset input terminal PR of the subtraction counter 12 via the OR circuit 11.
2 is preset to "5" again. Further, the minute setting signal S ₁₀ is supplied to the second input terminal of the AND circuit 28, and at this time, the first input terminal of the AND circuit 28 is supplied with the temporary clock display signal.
Since S ₁₈ b is given, the AND circuit 28 passes the clock pulse P ₆ to the clock pulse input terminal CK of the division counter 24 via the OR circuit 29.
will begin to give. Therefore, the division counter 24
is "1" every time clock pulse P ₆ is given,
The addition counting operation starts as "2", "3", etc., and accordingly, the minute display section of the display 34 also shows "01", "02", "03", etc. Changes are displayed. Then, when the count content of the minute counter 24 reaches "15", the pressing operation of the minute setting switch 10 is released. Next, when the hour setting switch 9 is pressed and turned on to output the hour setting signal _S9 , the setting signal _S9 is sent to the preset input terminal of the subtraction counter 12 via the OR circuit 11.
Since it is given to PR, the subtraction counter 12 is preset to "5" again. Also, hour setting signal S ₉
is now applied to the second input terminal of the AND circuit 26. At this time, since the temporary clock display signal _S18b is applied to the first input terminal of the AND circuit 26, the AND circuit 26 receives the clock pulse P. ₆ to the hour counter 23 via the OR circuit 27.
It is now applied to the clock pulse input terminal CK. Therefore, the hour counter 23 receives the clock pulse.
Every time P ₆ is given, an addition operation is performed like "2", "3", "4", etc., and accordingly, the hour display section of the display 34 also shows "2", "3", etc. ”, “4”,
Changes are displayed as follows. Then, when the count content of the hour counter 23 reaches "10", the pressing operation of the hour setting switch 9 is released. As a result of the above, as shown in FIG. 5, the display 34 shows "AM10:15".
(10:15 a.m.) and the current time will be displayed. When the hour setting signal S ₉ disappears by releasing the pressing operation on the hour setting switch 9, the subtraction counter 12 starts subtracting in the same manner as described above, and after 5 seconds, the display type storage circuit 18
stores the constant clock display state and outputs the constant clock display signal _S18a from the output terminal Oa, thereby turning on the transfer gate circuits 32 and 33. Even if the setting switch 9 and the minute setting switch 10 are pressed by mistake, the clock pulse _P6 will not be applied to the hour counter 23 and minute counter 24. Thereafter, the second counter 25 performs counting operation by sequentially applying the clock pulse _P6 to the clock pulse input terminal CK, and receives a carry pulse every time the count changes from "59" to "0", that is, every minute. P ₂₅ is now output, and the division counter 24 performs counting operation by applying the carry pulse P ₂₅ to the clock pulse input terminal CK via the OR circuit 29, and the count changes from "59" to "0". ”
The hour counter 23 outputs the carry pulse _P24 at the clock pulse input terminal CK, that is, every hour, and the hour counter 23 outputs the carry pulse _P24 at the clock pulse input terminal CK.
7, the clock section 22 performs a counting operation, and the display 34 displays the counted time. And after that,
When the count content of the hour counter 23 becomes "12" and the count content of the minute counter 24 becomes "0",
As shown in FIG. 6, the display 34 displays "PM12:
00" (12:00 a.m.), and the count content of the hour counter 23 is "24" and the minute counter 24 is displayed.
When the count content becomes "0", the display 34
As shown in Figure 7, "AM12:00" (12:00 AM)
Therefore, the time "0:00" (0:00 minutes) stored in the time limit storage section 36 is a non-existent time that does not match the counted time of the clock section 22. Yes, clock count signal S ₂₃ from clock section 22
The comparison circuit 47 that compares the minute count signal S ₂₄ with the hour storage signal S ₃₇ and the minute storage signal S ₃₈ from the time limit storage 36 does not output the drive command signal S ₄₇ .

Now, the case where any time other than the non-existent time is set and stored in the time limit storage section 36 will be described.
When the time limit setting switch 8 is pressed and turned on to output the time limit setting signal _S8 , the subtraction counter 12 is preset to "5" as described above, and the display type storage circuit 18 is in the time limit display state. The time limit display signal _S18c is outputted from the output terminal Oc by memorizing the certain fact, and the transfer gate circuits 45 and 46 are turned on, so that the display section 34 displays the time limit display signal S18c as shown in FIG. The non-existence time stored in the storage unit 36 is “0:00”
(0:00) is displayed. Next, when the minute setting switch 10 is pressed and turned on to output the minute setting signal _S10 , this minute setting signal _S10 is applied to the second input terminal of the AND circuit 42, and at this time, Since the time display signal _S18c is applied to the first input terminal of the AND circuit 42, the AND circuit 42 first receives one clock pulse.
It passes through _P6 and is applied to the clock pulse input terminal CK of the minute counter 38, and the count content of the minute counter 38 becomes "1". Also, the clock pulse P ₆ from the AND circuit 42 is sent to the OR circuit 56.
For example, if the flip-flop circuit 49 is in the set state, it is inverted to the reset state. On the other hand, the clock pulse P ₆ from the AND circuit 42 is applied to the AND circuit 4.
It is now also given to the second input terminal of 0,
At this time, the memory content of the hour counter 37 is "0".
The zero detection circuit 43 generates a zero detection signal S ₄₃ and sends it to the first signal of the AND circuit 40 via the delay circuit 44.
The AND circuit 40 passes the clock pulse P ₆ from the AND circuit 42 and supplies it to the clock pulse input terminal CK of the hour counter 37 via the OR circuit 41. The content will change from "0" to "1". As a result, the display 34
As shown in Figure 8, "AM1:01" (1:01 AM)
minutes). That is, when the first clock pulse _P6 passes through the AND circuit 42, the time stored in the time limit storage section 36 becomes the non-existent time "0:00" (0:00).
minute) to the actual time “AM1:01” (1:01 a.m.)
It will be changed immediately. Thereafter, the clock pulse _P6 is applied to the clock pulse input terminal CK via the AND circuit 42, and the division counter 38 sequentially performs counting operations such as "2", "3", "4", etc. However, the hour counter 37
When the memory content becomes "1" as described above, the zero detection circuit 43 no longer outputs the zero detection signal _S43 , so the clock pulse that has passed through the AND circuit 42
P ₆ is the clock pulse input terminal of the counter 37.
It will not be given to CK. As a result of the above, the time limit storage section 36 changes from "0:00" (0:00) to "0:01" (0:01) every time the clock pulse _P6 is applied.
minutes), "0:02" (0:02 minutes), etc., meaningless counting of non-existent times is no longer necessary. If the minute setting switch 10 is released from the minute setting switch 10 when the count of the minute counter 38 reaches a desired minute value, the desired minute value will be stored in the minute counter 38. After that, turn the hour setting switch 9
Press to turn on the time setting signal.
When S ₉ is output, the setting signal S ₉ is then given to the second input terminal of the AND circuit 39, and at this time, the time display signal S ₁₈ c is supplied to the first input terminal of the AND circuit 39. Therefore, the AND circuit 39 passes the clock pulse P ₆ and applies it to the clock pulse input terminal CK of the hour counter 37 via the OR circuit 41, and the hour counter 37 outputs "2", "3", Counting operations are performed as in "4", . . . . Note that the clock pulse P ₆ from the AND circuit 39 is also applied to the reset input terminal R of the flip-flop circuit 49 via the OR circuit 56. If the pressing operation of the hour setting switch 9 is released when the count content of the hour counter 37 reaches a desired hour value, the desired hour value will be stored in the hour counter 37. Therefore, clock part 2
If you want to perform the coffee extraction operation when the counted time in step 2 matches the stored time in the time limit storage section 36,
The operation signal S54 is output by pressing the operation switch ₅₄ to turn it on within 5 seconds after the pressing operation of the hour setting switch 9 is released. In this case, the AND circuit 52 inputs the zero detection signal to the first input terminal.
Due to the absence of _S43 , a high level output signal of the inverter circuit 53 is given, a time display signal _S18c is given to the second input terminal, and an operation signal _S54 is given to the third input terminal. Therefore, a high level output signal is generated and the flip-flop circuit 4
The flip-flop circuit 49 inverts to the set state and outputs the permission signal _S49 from the set output terminal Q.
This permission signal S ₄₉ is applied to the second input terminal of the AND circuit 48 and at the same time is applied to the dot indicator 59, so that the dot indicator 59 lights up as shown in FIG. 8, indicating the time limit for coffee extraction. Displays that the set has been completed. Thereafter, when 5 seconds have elapsed since the pressing operation of the hour setting switch 9 was released, the subtraction counter 1
2. Due to the operation of the zero detection circuit 15 and the trigger circuit 19, the display type storage circuit 18 remembers that the display is in the constant clock display state, and outputs the constant clock display signal _S18a from the output terminal Oa again. Part 2
2 counting time will be displayed on the display 34. Thereafter, when the counted time of the clock section 22 matches the stored time of the time limit storage section 36, the comparator circuit 47 outputs the drive command signal _S47 , and the first
At this time, the AND circuit 48 outputs a high-level output signal to the set input terminal S of the flip-flop circuit 50 because the allowable signal _S49 is applied to the second input terminal. The flip-flop circuit 50 inverts to the set state and outputs the set output terminal Q.
A drive signal S ₅₀ is output from the drive circuit 4, and based on this, the drive circuit 4 turns on the normally open contact 4a. As a result, the electric heater 2 is energized, and the hot water supply mechanism starts supplying hot water into the coffee extraction case, and the coffee liquid is extracted by the case and sequentially poured into the bottles placed on the heater. It is stored downstream. After that, when all the water in the water storage tank of the hot water supply mechanism is consumed, the coffee liquid extraction is completed, and after that, the electric heater 2 is turned off by turning on and off the bimetal switch 3, and the heating is continued. The bottle on the container is heated, and the coffee liquid inside the bottle is kept warm. still,
When it is desired to stop such heat retention, the stop switch 51 is pressed and turned on to output a stop signal S51, and this stop signal _S51 is sent to the reset input terminal R of the flip- _flop circuit 50.
As a result, the flip-flop circuit 50 is inverted to the reset state and the drive signal S _{50 is}
is no longer output, and the drive circuit 4 turns off the normally open contact 4a.

As is clear from the above explanation, the time limit storage unit 3
When the minute setting switch 10 or the hour setting switch 9 is operated in order to store a desired arbitrary time in the OR circuit 56, the clock pulse _P6 from the AND circuit 42 or 39, which together with the OR circuit 56 constitutes a reset means, is transmitted through the OR circuit 56. This is applied to the reset input terminal R of the flip-flop circuit 49, thereby putting the flip-flop circuit 49 into the reset state, and then by operating the operation switch 54 after completing the operation of storing the desired time setting in the time limit storage section 36. Since the flip-flop circuit 49 is first inverted to the set state and the enable signal _S49 is generated, thereby making the drive command signal _S47 valid, there is no possibility that the minute setting switch 10 and the hour setting switch 9 may be touched by mistake. time limit storage section 36
Whenever the memory time of S49 changes, the flip-flop circuit 49 goes into the reset state and the permission signal _S49 is output.
Therefore, even if the drive command signal _S47 is output at an unexpected time, this will be invalidated and will not actually occur, and the coffee extraction operation will not be performed. It won't happen. For the same reason as mentioned above, while the desired time is being set and stored in the time limit storage section 36, the time during the storage matches the counted time of the clock section 22, and the drive command signal _S47 is output. Even if this happens, this drive command signal _S47 is invalidated by the reset state of the flip-flop circuit 49.

By the way, as described above, when a desired arbitrary time is set and stored in the time limit storage section 36 and the flip-flop circuit 49 is set to the set state to output the permission signal _S49 , the drive command signal _S47 is output from the comparison circuit 47. The coffee extraction operation will be performed every time the coffee is output, but if you want to stop it, perform the following operation. That is, when the display 34 is displaying the counting time of the clock section 22,
When the operation switch 54 is pressed to output the operation signal _S54 , this operation signal _S54 is output to the AND circuit 5.
At this time, the AND circuit 55 inputs the high level output signal of the inverter circuit 58 to the OR circuit 57 because there is no time display signal _S18c at the first input terminal. As a result, a high level output signal is outputted, and this output signal is applied to the reset input terminal R of the flip-flop circuit 49 via the OR circuit 56, and the output signal is applied to the reset input terminal R of the flip-flop circuit 49. 49 enters the reset state and no longer outputs the permission signal _S49 . Therefore, comparison circuit 4
Even if 7 outputs the drive command signal _S47 , the AND circuit 4
The output signal of 8 remains at a low level, and the flip-flop circuit 50 is not inverted to the set state and does not output the drive signal _S50 .

In the above embodiment, the hour setting switch 9 and the minute setting switch 10 are provided as the time setting switches, but for example, only the minute setting switch 10 may be provided, or the fast-forwarding mode which changes one hour per second may be used. It is also possible to provide a delay switch and a delay switch that feeds one minute per second.

In addition, the present invention is not limited to the embodiments described above and shown in the drawings, but may be implemented with appropriate modifications within the scope of the invention, such as being applicable not only to coffee extractors but also to electrical equipment in general. Of course it is possible.

As explained above, the present invention is provided with a clock unit that counts time, a time storage unit in which an arbitrary time is set and stored based on the operation of a time setting switch,
A comparison section is provided that compares the time stored in the time limit storage section with the counted time of the clock section and generates a control signal when they match, and the control signal from this comparison section is enabled in the set state and disabled in the reset state. an operation switch for selectively switching the state storage circuit between a set state and a reset state, and the time setting switch is operated to change the time stored in the time limit storage section. Since the configuration is provided with a reset means that resets the state storage circuit when the time setting switch is touched by mistake, the time stored in the time storage section changes undesirably and the control signal is output at an unexpected time. It is possible to provide a timer device that has an excellent effect of being able to nullify even if the occurrence of the problem occurs.

[Brief explanation of the drawing]

The drawings show an embodiment in which the present invention is applied to a coffee extractor, in which Fig. 1 is an electrical configuration diagram, Fig. 2 is a front view of the display section, and Figs. 3 to 8 show the display section in different display states. This is a diagram equivalent to Figure 2. In the drawing, 2 is an electric heater (load), 4 is a drive circuit, 4a is a normally open contact, 5 is a timer, 6 is a frequency dividing circuit, 7 is a clock setting switch, 8 is a time setting switch, and 9 is an hour setting switch. (time setting switch),
10 is minute setting switch (time setting switch), 1
2 is a subtraction counter, 13 is a numerical value storage unit, 15 is a zero detection circuit, 18 is a display type storage circuit, 22 is a clock unit, 23 is an hour counter, 24 is a minute counter,
25 is a second counter, 30 is an initialization circuit, 34 is a display, 36 is a time storage section, 37 is an hour counter, 38 is a minute counter, 39 and 42
is an AND circuit (reset means), 43 is a zero detection circuit (absence time detection section), 47 is a comparison circuit (comparison section), 49 is a flip-flop circuit (state storage circuit), 54 is an operation switch, and 56 is an OR circuit ( reset means).

Claims (1)

[Claims] 1. A clock section that counts time, a time limit memory section in which an arbitrary time is set and stored based on the operation of a time setting switch, and the time stored in this time limit memory section and the counted time of the clock section are compared to find that they match. a comparator section that generates a control signal when the comparator is set; a state memory circuit that enables the control signal from the comparator section in a set state and disables it in a reset state; A timer comprising: an operation switch for changing the time; and a reset means for setting the state storage circuit to a reset state when the time setting switch is operated to change the time stored in the timer storage section.