JPS6213701B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a false response method during data transfer between a central processing unit and a terminal.

In a large-scale control system, a central processing unit (hereinafter referred to as CPU) controls a large number of terminals, and various data are exchanged between the CPU and the terminals. By the way, if the terminal side reliably receives or sends data from the CPU, it is configured to send a data acknowledgment signal (hereinafter referred to as DTACK signal) to the CPU.
There is a CPU. The CPU uses this DTACK signal to confirm that the terminal has received the data and proceeds to the next step. However, if one of the terminals fails, the DTACK signal will not be returned even if the CPU transfers data to that terminal, so the CPU will
The state of waiting for the DTACK signal continues, and the next processing is not performed. Therefore, if the DTACK signal is not returned within a certain period of time on the CPU side, it is configured to recognize it as an error and perform error processing.
In this case, the disadvantage is that the system comes to a near-stop state, making it impossible to control other terminals.

Furthermore, since the DTACK signal line is wired-OR connected to the response circuit section of each terminal, there is a possibility that the failure may spread to other terminals via the DTACK signal line, depending on the nature of the failure in the terminal.

Furthermore, when high reliability is required, two
A dual mode system is sometimes used in which one CPU is used as the active system and is connected to each terminal, while the other is used as a standby system and performs the same processing as the current system. In such a case, if a CPU that requires a response to the DTACK signal is used, the standby system cannot receive the DTACK signal and therefore cannot be operated by the same program as the active system.

The present invention is aimed at solving these drawbacks, and is designed to send a DTACK signal to the CPU using a false response circuit provided between the CPU and the terminal.

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the general configuration of a large-scale control system, such as a traffic light control system, according to the present invention. In this figure,
Important input devices 2, output devices 3, and memory 4 are connected to the CPU 1 via bus lines including a data bus, an address bus, and control signal lines. It is assumed here that the portions surrounded by broken lines are provided within the same chassis. 5a, 5b, . . . indicate a large number of input/output circuit blocks (hereinafter referred to as I/O blocks) controlled by the CPU 1, and for example, in a traffic light control system, they indicate individual traffic lights. In the present invention, a false response circuit section 6 is provided between the I/O blocks 5a, 5b, . . . and the CPU 1. False response circuit section 6 is CPU1
is implemented in the same chassis as the I/O block, and when one of the I/O blocks 5a, 5b, etc. connected to it is accessed, the
This is to send the DTACK signal back to the CPU1.
The CPU 1, input/output devices 2 and 3, memory 4, and this false response circuit section 6 constitute a main control section 7. FIG. 2 shows a dual-mode system in which two main controllers 7a and 7b are used to perform parallel processing, with one as the active system and the other as the standby system, when high reliability is required. In this case, I/O block 5
A switch circuit 8 is provided between the main controllers 7a, 7b, and the main controllers 7a, 7b, and the switch circuit 8 switches the bus line. Assuming that the main control section 7a is the active system and the main control section 7b is the standby system, each I/O block 5a, 5b, . . . is connected to the main control section 7a by a switch circuit 8. Since each main control section 7a, 7b has a false response circuit section 6 therein, the DTACK signal is obtained from each false response circuit section 6. Therefore, each main control section 7a, 7
b can execute the same program.
If the current main control section 7a fails for some reason, the bus line is switched by the switch circuit 8, and the main control section 7b switches to the I/O blocks 5a, 5b.
It will be connected to...

FIG. 3 is a block diagram showing one embodiment of this false response circuit section 6. In this figure, an address bus 10 given from a CPU 1 is connected to an address decoder 11, and further to a subsequent I/O block 5.
a, 5b...... are connected. The address decoder 11 detects whether any of the subsequent I/O blocks
It generates an output when accessed by CPU 1, and the output is output from AND circuit 12.
given to. A data strobe signal line (hereinafter referred to as a DS signal line) is also connected to the AND circuit 12, and the AND output of these lines is applied to a D flip-flop 13 as a D input. A clock signal is applied to the clock input terminal T of the D flip-flop 13, and its Q output is applied to the delay circuit 1.
4 to the AND circuit 15. The delay circuit 14 is provided to correspond to various I/O blocks having different response times. The AND circuit 15 outputs the logical product of the output of the delay circuit 14 and the DS signal.
This is transmitted to the CPU 1 as a DTACK signal.
In this way, the address bus 10, data bus 16, and other control signal lines 17 such as read/write signals other than the DTACK signal line are directly connected to the I/O block 5.
It is transmitted to a, 5b...

Next, the operation of the false response circuit section 6 will be explained with reference to the waveform diagram of FIG. When the CPU 1 accesses an I/O block connected via the false response circuit section 6, for example, the I/O block 5a, the address is decoded by the address decoder 11 and the output is output as shown in FIG. 4a. circuit 1
given to 2. Subsequently, after a short delay, the DS signal is applied to the AND circuit 12, and the AND output is applied to the D input of the D flip-flop 13. Assuming that a fast clock pulse is applied to the D flip-flop 13, the Q output of the D flip-flop 13 is obtained with a delay of the clock period as shown in FIG. 4c. This Q output is sent to the delay circuit 14 for a predetermined time T.
It is transmitted to the AND circuit 15 after a delay of . The logical product of this delayed signal and the DS signal is transmitted to the CPU 1 as a DTACK signal as shown in FIG. 4d. Therefore, the CPU 1 assumes that the DTACK signal has been received from the I/O block 5a and proceeds to the next step. In this way, the false response circuit section 6 generates the DTACK signal instead of the I/O block and transmits it to the CPU 1.

As described in detail above, in the present invention, a false response circuit is connected to the bus line, and I/O blocks that are unimportant from the perspective of the entire system are connected to the CPU via this false response circuit. Therefore, even if these I/O blocks fail or the power to the I/O block is turned off for maintenance or inspection, and the I/O block cannot actually be controlled by the CPU, the false response circuit section is always I/O
Instead of the block, a DTACK signal is generated and sent to the CPU. Therefore, even in cases like this
Processing by the CPU can continue, eliminating the risk of the entire system stopping. If the I/O block is faulty, the CPU will
A failure can be determined based on the data returned from the block. Also, in the dual mode system shown in FIG. 2, if a false response circuit is provided in each main control section, both can be operated by the same program.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing the configuration of a control system according to the present invention, FIG. 3 is a block diagram showing an embodiment of the false response circuit section, and FIGS.
d is a waveform diagram showing waveforms of each part of the false response circuit section. 1...CPU, 5a, 5b...I/O block, 6...False response circuit section, 10...Address bus, 11...Address decoder, 13...D flip-flop, 14...Delay circuit.

Claims (1)

[Claims] The control system includes a central processing unit and an input/output circuit block connected via one bus line, and a part of the input/output circuit block is connected to the central processing unit via a false response circuit section. In the system, the false response circuit section includes an address decoder that outputs an output when an input/output circuit block connected thereto is accessed, and based on the output, provides a data confirmation signal to the central processing unit. A false response method for a control system characterized by: 2. The false response system for a control system according to claim 1, wherein the central processing unit and the false response circuit section are mounted in the same chassis.