JPS6213816B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply structure for semiconductor wafers, and more particularly to a power supply structure for semiconductor wafers suitable for conductive aging performed at the wafer level of semiconductors.

2. Description of the Related Art Semiconductor components such as ICs are used in large quantities in electronic computers and the like. Therefore, in order to improve the reliability of equipment, it is essential to improve the reliability of the semiconductor components used. Generally, semiconductor parts go through various sorting and inspection processes during the manufacturing process and are shipped at a certain level of quality. However, if even higher reliability is required, after the parts are assembled, the manufacturer or user We conduct a screening process called ``electrification aging'' to identify and remove early defective products due to manufacturing defects in order to improve reliability.

However, in the conventional energization aging method, aging is carried out after the parts are assembled or after the parts are installed on a printed circuit board, etc., so when a defect occurs, there is waste such as discarding or replacing the finished part. , depending on the yield, the cost will rise considerably. Another drawback is that the external dimensions of the aged product become large, and testing equipment becomes large-scale in order to conduct tests in large quantities.

In order to solve these drawbacks, it would be very effective if semiconductors could be subjected to electrical aging at the wafer level. However, in the past, there was no good means for simultaneously supplying power to each chip on a semiconductor wafer, so energization aging had to be carried out after the parts were completed.

An object of the present invention is to provide a power supply structure suitable for energization aging of semiconductor wafers.

In general, one semiconductor wafer is made up of several hundred or more chips, and in order to perform wafer-level current aging, it is necessary to simultaneously supply power to the power supply terminals of each chip. In this case, it is very difficult to supply power to the power supply terminals of each chip using a mechanical probe due to space limitations. In order to solve the above-mentioned problems, the present invention provides a method for supplying power to individual IC chips from the wiring pattern inside the wafer after supplying power to the power supply pattern provided around the wafer all at once via a socket.

FIG. 1 shows a semiconductor wafer suitable for the power supply system of the present invention. Around the periphery of the silicon wafer 1, a power supply pattern 4 for receiving power from the outside is wired in an arc shape, and on top of that is a plurality of power supply patterns 5 for making good contact with the socket contacts. It is provided. It is preferable that the power supply pad 5 be made thicker than the power supply pattern section 4. The power supply pattern 5 and the IC chip 2 are connected by a power supply line 6, which is connected to the power terminal of each IC chip.

FIG. 2 shows a power supply method according to the present invention. A storage groove 7a for storing a contactor 7 is provided in a frame-shaped housing 6 made of an insulator. The contactor 7 is made of a metal material with a circular cross section and has an arcuate shape matching the shape of the power supply pattern 4 on the silicon wafer. The material of the contact is indium, lead, etc. to avoid damaging the silicon wafer.
A soft metal such as is preferable. The silicon wafer 1 is positioned and placed on the contact 7 with the wiring surface facing down. The silicon wafer 1 is pressed from its back side by a pressing plate 8 to which a buffer member 9 made of silicone rubber or the like is attached, and comes into contact with the contact 7 at the power supply pad 5 portion. The pressing plate 7 is the spring member 1
It is fixed to the housing 6 at 0.

According to the present invention, since the current aging of semiconductor chips can be performed on a wafer basis, the following effects can be obtained.

(1) Since initial defects are removed before IC package assembly, the yield after post-processing is improved and costs can be reduced. Particularly in large-scale LSIs, it is extremely effective, including chip replacement work.

(2) The work itself is efficient because many chips can be energized and aged at the same time.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a silicon wafer suitable for implementing the present invention, and FIG. 2 is a plan view and a sectional view showing a power supply structure for a semiconductor wafer according to the present invention. 1... Silicon wafer, 2... IC chip, 3...
Parting line, 4...Power supply pattern, 5...Power supply part, 6
... Power supply line, 7... Contact, 8... Pressing plate, 9... Buffer member, 10... Spring member.

Claims (1)

[Claims] 1. A pair of arc-shaped contacts that are pressed and electrically contacted by a power supply pattern provided around the surface of a semiconductor wafer, and a frame-shaped insulating housing that accommodates and positions the contacts and the semiconductor wafer.
A power supply structure for a semiconductor wafer, characterized in that power is supplied to the semiconductor wafer by a socket comprising a contactor and a pressing member for pressing the semiconductor wafer.