JPS6214990B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clamp circuit that performs a clamping operation on a pedestal level or a sync level of a video signal.

Generally, this type of clamp circuit is used in a sync separation device to separate a sync signal from a video signal, and ensures that the sync separation operation is performed correctly when the sync signal is obtained by slicing the video signal at a predetermined slice level. In order to do this, it is used to clamp the above video signal at a predetermined clamp level.

FIG. 1 is a block diagram showing the configuration of a synchronous separator equipped with a typical pedestal clamp circuit that is conventionally known as this type of clamp circuit.

That is, in the conventional example shown in FIG. Therefore, the above-mentioned input video signal is sliced at a predetermined slice level to separate the synchronization signal and output from the signal output terminal 4.

The clamp circuit 2 includes a sync separator 5 that separates a sync signal by slicing the input video signal from the first signal input terminal 1 at a predetermined slice level; A pulse generator 6 that generates a clamp pulse according to a synchronization signal obtained in advance, and a second signal input terminal 7
a gate section 8 whose gate is opened and closed by a dropout detection signal supplied from the gate section 8;
and a clamp section 9 that performs pedestal clamping on the input video signal from the first signal input terminal 1 in response to the clamp pulse supplied via the clamp section 9.

Here, an input video signal as shown in FIG. _2A , in which signal disturbance occurs during period T1 due to dropout in a VTR (not shown), is supplied to the first signal input terminal 1, and A dropout signal as shown in FIG. FIGS. 2A to 2F show time charts for explaining the operation of the clamp circuit 2 configured as described above.

That is, in the synchronization separation section 5, a synchronization signal as shown in FIG. 2B is obtained by slicing the input video signal shown in FIG. 2A at a predetermined slice level _L1 . Note that the synchronization signal obtained by the synchronization separation unit 5 is generated by detecting the disturbance in the input video signal during the period T ₁ and containing an error signal at the timings shown as t ₁ and t ₂ in FIG. 2B. I get used to it. Therefore, in the pulse generator 6 operated by the synchronization signal including the above error signal, as shown in _FIG . Accordingly, error pulses are generated at timings t ₁ ′ and t ₂ ′. This error pulse is guarded in the gate section ₈ by a dropout detection signal as shown in _FIG .
A clamp pulse containing no error pulse is supplied as shown in Figure E. Therefore, the above-mentioned clamp part 9
Then, a pedestal clamp operation is performed and a video signal as shown in FIG. 2F is supplied to the above-mentioned sync separation circuit 3.

In the above synchronous separation circuit 3, as shown in FIG.
By slicing the video signal shown in FIG. ₂ at a predetermined slice level L2, the synchronization signal can be correctly separated.

By the way, in the conventional clamp circuit 2 as described above, when the dropout detection signal is supplied to the gate section 8 later than the period _T2 , the time charts shown in FIGS. 3A to 3F are As shown, there is a problem in that the input video signal cannot be properly pedestally clamped due to malfunction. That is, FIGS. 3A to 3F show respective signals corresponding to FIGS. 2A to 2F above, and from the period T ₁ in which the input video signal shown in FIG. 3A is disturbed. is also a period delayed by time T ₀
This is the case when the dropout detection signal is supplied to the second signal input terminal 7 at T ₂ ' as shown in FIG. 3D. In this case, the error pulse included in the clamp pulse from the pulse generator 6 cannot be completely guarded at the gate section 8, so as shown in FIG.
As shown in FIG. 2, a clamp pulse containing an error pulse at the timing t ₁ ' is supplied to the clamp section 9. Therefore, in the clamp section 9, the portions of the input video signal other than the pedestal portion are clamped to a predetermined clamp level at timing t ₁ ' due to the above-mentioned error pulse. The clamping operation after the above-mentioned mis-clamping cannot be performed correctly, and as shown in FIG. 3F, a video signal that has not been properly pedestally clamped is supplied to the above-mentioned sync separation circuit 3. Even if the video signal shown in FIG. 3F is sliced at a predetermined slice level _L2 in the synchronization separation circuit 3, the synchronization signal cannot be separated correctly.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention provides a clamp circuit that can prevent malfunctions due to disturbances in input video signals and can always perform correct clamp operations.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings showing one embodiment.

The specific circuit configuration of one embodiment of the synchronous separation device configured using the clamp circuit according to the present invention is explained in the fourth example.
The basic configuration of this embodiment is shown in the block diagram of FIG. 5.

In this embodiment, an input video signal from a VTR (not shown) is supplied from a first signal input terminal 10 to a clamp section 12 and a synchronization separation section 13 via a buffer amplification transistor 11.

Note that the above input video signal disturbance occurs during period T ₁₀
FIG. 6A is a time chart for explaining the operation in this embodiment as occurring during the operation.
to FIG. 6M.

The synchronous separation unit 13 includes a clamper formed by two diodes 14 and 15 and a transistor 16, and a slicer formed by a comparator 17, and after clamping the input video signal with the clamper, Separate the synchronization signal by slicing it with a slicer. 6th
The signal obtained by the synchronization separation unit ₁₃ from the input video signal as shown in FIG.
Contains error signals at t ₁₁ and t ₁₂ .

A synchronization signal containing an error signal obtained from the synchronization separation section 13 is supplied to a gate pulse generation section 18 and a window control section 19.

The gate pulse generator 18 is a first monostable multivibrator 20 that is triggered by a signal supplied from the synchronous separator 13.
and a second monostable multivibrator 21 that is triggered by the Q output signal from this first monostable multivibrator 20, and the output signal from this second monostable multivibrator 21 is supplied to the base. The collector of the transistor 22 outputs a gate pulse as shown in FIG. 6C. The gate pulse obtained from the gate pulse generator 18 has a timing corresponding to the pedestal portion of the input video signal obtained when the first monostable multivibrator 20 is triggered by the synchronization signal.
The timing obtained by triggering the first monostable multivibrator 20 by the above error signal at the gate pulse at _t10 '
It includes error pulses at t ₁₁ ′ and t ₁₂ ′.

In addition, the window control section 19 operates a first monostable multivibrator 23 that is triggered by a signal supplied from the synchronization separation section 13.
Then, the second monostable multivibrator 24 is triggered by the output signal from the first monostable multivibrator 23, and the Q output signal from the second monostable multivibrator 24 becomes logic "1". a counter 25 that counts the output signal from the first monostable multivibrator 23 during the period when
A decoder 26 decodes the counting output signal from the counter 25, and the decoded output signal from the decoder 26 is supplied as a data signal via a delay circuit 27, and the second
A D-type flip-flop 28 is supplied with the output signal from the monostable multivibrator 24 as a clock signal. In this embodiment, the first monostable multivibrator 23 is triggered for each signal from the synchronous separator 13.
It is designed to output a pulse signal with a pulse width of 100ns. The output signal obtained from this first monostable multivibrator 23 is shown in FIG.
Shown below. Further, the second monostable multivibrator 24 has a time constant determined so as to output a pulse signal with a pulse width slightly smaller than 1H (0.8H in this embodiment), and the synchronous separator 24 The first corresponding to each synchronization signal from 13
6E is triggered every time the output signal from the monostable multivibrator 23 falls.
It outputs a Q output signal as shown in FIG. Furthermore, the above-mentioned counter 25 detects the rising edge of the output signal from the first monostable multivibrator 23 during a period of 0.8 when the Q output signal from the above-mentioned second monostable multivibrator 24 is at logic "1". A decoded output signal as shown in FIG. 6F is obtained from the datacoder 26 which counts the count output signal from the counter 25 and decodes the count output signal from the counter 25. Therefore, the D-type flip-flop 28, to which the decoded output signal is delayed as shown in FIG. 6G via the delay circuit 27 and supplied as a data signal, outputs a wind pulse as shown in FIG. 6H. I will do it.

Further, a transfer pulse generating section 30 constituted by a monostable multivibrator 29 that is triggered by the fall of the Q output signal of the second monostable multivibrator 24 of the window control section 19 is shown in FIG. A transfer pulse with a pulse width of 0.1H as shown in is generated.

Furthermore, a gate unit 32 consisting of a NAND gate 31 to which the transfer pulse obtained by the transfer pulse generation unit 30 and the window pulse obtained by the window control unit 19 are supplied is configured to prevent disturbances from occurring in the input video signal. The first transfer pulse generated after the period _T10 is guarded, and a transfer command pulse as shown in FIG. 6J is output.

Additionally, a clamp section 12 to which the input video signal from the first signal input terminal 10 is supplied is provided.
are the first and second collectors connected to each other.
The second transistor 34 is composed of a DC shifter consisting of transistors 33 and 34.
The above input video signal is supplied to the first storage section 37 via the pedestal gate section 36 in response to a clamp control signal from the control section 35 supplied to the base of the pedestal gate section 36 . In the pedestal gate section 36, a gate transistor 38 is turned on by a gate pulse from the gate pulse generating section 18. Therefore, the first storage section 3 described above
7, the gate of the pedestal gate section 36 is opened even by the error pulse included in the gate pulse, so that a signal level as shown in FIG. 6K is stored.

This first storage section 37 is formed by a capacitor 39 and first and second transistors 40 and 41 for storing the signal level of the input video signal supplied through the pedestal gate section 36. It consists of a balanced amplifier and the above capacitor 3.
The signal level stored in 9 is supplied to the transfer section 42 via the above-mentioned buffer amplifier.

The transfer unit 42 receives a transfer command pulse obtained through the gate unit 32 from the transistor 43.
The signal level stored in the first storage section 37 is transferred to the second storage section for each transfer pulse. 45. The second storage section 45 stores the signal level transferred via the transfer section 42 using a capacitor 46 . Then, the second storage unit 4 described above
A control signal corresponding to the signal level stored in step 5 is obtained from the control section 35, and this control signal is supplied to the above-mentioned clamp section 12.

Therefore, in the embodiment with the above-mentioned configuration,
As shown in FIG. 6K, even if the signal level stored in the first storage unit 37 fluctuates due to disturbances in the input video signal, after the period T ₁₀ during which disturbances occur in the input video signal, The sixth transfer pulse obtained by guarding the first transfer pulse generated in the gate section 32
Since the signal level stored in the first storage section 37 is transferred to the second storage section 45 via the transfer section 42 which performs a transfer operation according to the transfer command pulse as shown in FIG. This second storage section 45
As shown in FIG. 6L, the signal level stored in is such that there is no level fluctuation due to the above-mentioned disturbance of the input video signal. Therefore, the clamp section 12, which operates with the signal level of the control signal corresponding to the signal level stored in the second storage section 45 as the clamp level, correctly clamps the input video signal at the above clamp level. By doing this, a video signal as shown in FIG. 6M can be obtained.

The input video signal clamped by the clamp unit 12 in this manner is subjected to synchronous separation by the synchronous separation circuit 48 consisting of a slicer formed by the comparator 47, and the signal output terminal 49
Therefore, it is possible to construct a synchronization separation device that can obtain a stable synchronization signal and perform correct synchronization separation operation.

Furthermore, in this embodiment,
A dropout detection signal obtained by slicing a frequency-modulated video signal obtained by a VTR at a predetermined level after envelope detection is supplied to the wind error detection section 51 via the second signal input terminal 50. The detection output signal obtained by the wind error detection section 51 is supplied to the gate section 32 described above. This wind error detection section 51 is connected to a first
a D-type flip-flop 52, and a second D-type flip-flop 53 to which the output signal from the monostable multivibrator 29 of the transfer pulse generator 30 is supplied as a clock signal.
and an AND gate 54 to which the output signal from the first D-type flip-flop 52 and the dropout detection signal are supplied. Note that the first D-type flip-flop 52 is cleared at the fall of the output signal from the second D-type flip-flop 53, and
The second D-type flip-flop 53 is cleared at the rising edge of the Q output signal from the first D-type flip-flop 52. Furthermore, the first and second D-type flip-flops 52, 5
Logic "H" data is always applied to each D input terminal of the circuit 3.

The window error detection unit 51 detects the input video signal during a period other than the time constant (0.8H in this embodiment) of the second monostable multivibrator 24 in the window control unit 19. This is to supply an auxiliary window pulse to the gate section 32 to prevent the transfer section 44 from malfunctioning due to unnecessary pulses being included in the transfer pulse when the signal is disturbed due to dropout. .

That is, due to the disturbance in the input video signal, the synchronization separation circuit 13 outputs a signal as shown in FIG. 7A.
In addition to including error signals at timings t ₁₃ , t ₁₄ , and t ₁₅ , the timing t ₁₀ immediately after the above timing t ₁₅
If a synchronization separation output signal is output in which _{a synchronization} signal that should exist in ′, t ₁₅ ′, and a gate pulse containing unnecessary pulses at the timing t ₁₀ ′ corresponding to the pedestal portion of the input video signal is output, and the window control unit 19
The first monostable multivibrator 23 of
As shown by the solid line in FIG. 7B, the above t ₁₃ ,
An output signal containing unnecessary pulses at each timing t ₁₄ and t ₁₅ and missing a pulse at timing t ₁₀ immediately after the above timing t ₁₅ is output, and the output signal from the second monostable multivibrator 24 is as shown in FIG. Since the signal becomes as shown in C, the transfer pulse generator 30 as shown in FIG.
At the same time, the output of the decoder 26 in the window control section 19 is
As shown in Figure E, the wind pulse from the window control unit 19 cannot completely guard the period _T30 during which the transfer pulse is disturbed, as shown in Figure 7F. Sometimes I put it away.

Therefore, in the above-mentioned window error detection section 51, the signal input from the second signal input terminal 50 as shown in FIG.
The first D-type flip-flop 52 is triggered by the rising edge of the dropout detection signal as shown in FIG. By clearing the first D-type flip-flop 52 at the falling edge of the output signal from the D-type flip-flop 53 as shown in FIG.
An output signal as shown in FIG. 7I is obtained from the D-type flip-flop 52, and the OR output signal of this output signal and the above-mentioned dropout detection signal is outputted as an auxiliary window pulse via an AND gate 54. It's summery. The above auxiliary wind pulse is shown at J in FIG. Therefore, the transfer command pulse obtained through the gate section 32 whose gate is closed by the auxiliary window pulse from the window error detection output section 51 and the window pulse from the window control section 19 is as follows.
Since the above transfer pulse is guarded during the period _T30 when it is disturbed, the result is as shown in FIG. 7K. If the transfer unit 42 is operated with such a transfer command pulse, the signal level stored in the second storage unit 45 will not be disturbed by the above-mentioned disturbance of the input video signal, so that the signal level will always be correct. The above input video signal can be clamped at the clamp level.

Therefore, in this embodiment, even if the signal level stored in the first storage section 37 via the pedestal gate section 36 fluctuates when the input video signal is disturbed, the above-mentioned input video signal is During the period T ₁₀ during which the signal is disturbed and during the period T ₃₀ during which the wind pulse from the window control section 19 is disturbed, the signal level stored in the first storage section 37 is stored in the second storage section. Since the operation of the transfer unit 42 is controlled so as not to transfer the data to the
A control signal for always setting a correct clamp level is supplied from the control unit 35, which operates according to the signal level stored in the second storage unit 45, to the clamp unit 12, so that the input video signal is set to the correct clamp level. Can be clamped.

In the above embodiment, the pedestal level of the input video signal clamped by the clamp unit 12 1H before is stored in the second storage unit 45 to perform pedestal clamping. The pedestal level stored in the storage unit 45 of
It is not limited to the level 1H before, and may be set arbitrarily. Normally, set it to about 0.5H to 5H. Furthermore, the sync chip level of the input video signal can be stored in the second storage section 45 to perform sync chip clamping.

As is clear from the description of the embodiments described above, according to the present invention, when a disturbance occurs in the input video signal, the clamp operation is performed at the previously stored correct clamp level, so that the signal due to dropout etc. Correct clamping operations can always be performed on input video signals with disturbances.

Therefore, if the present invention is applied to a synchronization separation device, it is possible to always correctly and reliably separate the synchronization signal even when the input video signal is disturbed, and the intended purpose can be fully achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a synchronous separation device using a conventional clamp circuit. Figure 2A
2 to 2F are time charts for explaining normal operation of the above embodiment, and FIGS. 3A to 3F are time charts for explaining malfunction. Figures 2A and 3
Figure A shows the input video signal, Figures 2B and 3B show the signals obtained from the sync separator, Figures 2C and 3C show the signals obtained from the clamp pulse generator, Figure 2D and Figure 3D
2 shows the gate pulse obtained from the gate pulse generator, FIGS. 2E and 3E show the clamp pulse obtained through the gate part, and FIGS. 2F and 3F show the conventional clamp circuit. A clamped input video signal is shown. FIG. 4 is a circuit diagram showing a specific configuration of an embodiment of a synchronous separation device configured by applying a clamp circuit according to the present invention. FIG. 5 is a block diagram showing the basic configuration of the above embodiment. Figure 6 A to 6
FIG. M and FIGS. 7A to 7K are time charts for explaining the operation of the above embodiment. Figure 6A shows the input video signal supplied to the first signal input terminal, Figure 6B and Figure 7A.
6C shows the signal obtained in the synchronous separation section, and FIG. 6C shows the signal obtained in the gate pulse generation section.
Figures D and 7B show the output signals from the first monostable multivibrator of the window control, and Figures 6E and 7C show the Q output signal from the second monostable multivibrator of the window control. 6F and 7E show the decoder output signals from the decoder of the window control section, FIG. 6G shows the signal obtained through the delay circuit of the window control section, and FIG. Figures H and 7F show the wind pulses obtained as the Q output signal from the D-type flip-flop of the window control section, and Figures 6I and 7D show the transfer pulses from the transfer pulse generator. 7G shows the dropout detection signal supplied to the second signal input terminal, FIG. 7H shows the output signal from the second D flip-flop of the wind error detection section, and FIG. 7I shows the dropout detection signal supplied to the second signal input terminal. shows the output signal from the first D-type flip-flop of the detection section,
FIG. 7J shows the auxiliary wind pulse obtained through the AND gate of the wind error detection section, and the sixth
FIG. J and FIG. 7 K show the transfer command signal obtained through the gate section, FIG. 6 K shows the signal level stored in the first storage section, and FIG. 6 L shows the signal level stored in the second storage section. FIG. 6 shows the signal level stored in M.
shows the input video signal clamped by the clamp section. 10... Signal input terminal, 12... Clamp section,
13... Synchronization separation section, 18... Gate pulse generation section, 19... Window control section, 30... Transfer pulse generation section, 32... Gate section, 35... Control section,
36... Pedestal gate section, 37... First storage section, 42... Transfer section, 45... Second storage section.

Claims (1)

[Claims] 1 means for sequentially storing a predetermined signal level of an input video signal as a clamp level; means for clamping the input video signal at the clamp level stored by the means; and means for detecting disturbances in the input video signal. and means for controlling the storage operation of the storage means, and when the input video signal is disturbed, the storage means is prohibited from changing the storage contents and continues to maintain the previously stored clamp level. A clamp circuit characterized in that it is configured to perform a clamp operation by controlling the storage means.