JPS6215149B2 - - Google Patents

Description

[Detailed description of the invention]

This invention comprises at least a display element for displaying AM and PM information, a plurality of segment display elements for displaying hour value information, and two colon display elements for displaying divisions of hour value information, and dynamically displays time information or time information. This invention relates to a timer equipped with a digital display. Conventionally, this type of timepiece with a digital display has a display element for displaying morning and afternoon information, a plurality of segment display elements for displaying hour value information, and a colon display element for displaying the division of hour value information, each of which are separate digits. It is known that the system is controlled as follows. However, an increase in the number of digits for controlling a display device causes a decrease in duty cycle, which causes a problem of a decrease in display brightness of each display element. For this reason, it is conceivable to increase the instantaneous brightness of the display elements to substantially prevent the display brightness of each display element from decreasing, but this causes another problem of shortening the life of the display elements. For this reason, it is desirable to reduce the number of digits controlling the display. However, in the above-mentioned conventional timer, when considering the time display section, if one that displays the time or time down to the hour and minute is used, four segment display elements that are controlled by one digit are required. Adding to this the display elements for morning and afternoon information, which are controlled by one digit each, and the two colon display elements, a total of 6 digits are required, and the timer also requires a display element to display timer information. In the end, the number of digits required to control the display device became more than 6 digits, resulting in a problem that the number of digits increased. The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a timer with a digital display that can reduce the number of digits used to control the display. Embodiments of the present invention will be described below with reference to the drawings. Fig. 1 is a block diagram showing the circuit configuration, in which 1 is a waveform shaping circuit that shapes the commercial AC power waveform input from the input terminal IN into a pulse shape, and 2 is a timer based on the output of the waveform shaping circuit 1. This is a time counter that counts. As shown in FIG. 6, this time counter 2 has a 7-word configuration of 4 bits per word, and the first word bit memories _M11 to _M13 constitute a quintal or hexadecimal counter 2a, and the second word bit memory M ₂₁ to _M24 constitute the decimal counter 2b, and the third word bit memory _M31 to _M34 constitutes 10
A hexadecimal counter 2c is constituted by the fourth word bit memories _M41 to _M43 , and a hexadecimal counter 2d is constituted.
The bit memories _M51 to _M54 of the 6th word constitute a decimal counter 2e, and the bit memory _M61 of the 6th word
~ _M63 constitutes a hexadecimal counter 2f, the 7th word bit memories _M71 to _M74 constitute a hexadecimal counter 2g, and the 6th word bit memory _M64 constitutes the morning and afternoon information setting memory 2h. ing. The signal from the waveform shaping circuit 1 is counted by a quintal or hexadecimal counter 2a in the first word. Note that the counter 2a has a power supply frequency of
At 50Hz it functions as a quinary counter, at 60Hz it functions as a 6-digit counter.
It is designed to function as a forward counter. Therefore, in the time counter 2, the decimal counter 2b in the second word counts 1/10 second, the decimal counter 2c in the third word counts 1 second, and the decimal counter 2c in the third word counts 1 second.
The hexadecimal counter 2d in the 5th word counts 10 seconds, the decimal counter 2e in the 5th word counts 1 minute, the hexadecimal counter 2f in the 6th word counts 10 minutes, and the decimal counter 2f in the 7th word counts 10 minutes. Counter 2g is 1
The time is counted, and the morning and afternoon information setting memory 2h in the sixth word specifies morning and afternoon. 3 is a carry detection circuit that detects when there is a carry from the counter 2e that counts 1 minute in the time counter 2 and the counter 2d that counts 10 seconds; 4, 5, and 6 are two control target circuits; Time information that controls the time switch, on/off control information for the two time switches,
Do you want to repeat the other set time information every day?1
1st, 2nd, and 3rd timer memories for setting each timer information specifying whether to end after only one time, 7 is the time information set in each of the above-mentioned timer memories 4, 5, and 6 and the above-mentioned time This is a comparison circuit that compares the time information counted by the counter 2. Each of the timer memories 4, 5, and 6 has a 4-word configuration of 4 bits per word, as shown in FIG.
The memory section 4a stores 1-minute information in the first word bit memories _M11 to _M14 , the memory section 4b stores 10-minute information in the second word bit memories _M21 to _M23 , and the third word bit memory M A memory section 4c stores time base information in ₃₁ to _M34 , and a memory section 4c stores on/off control information for two time switches in fourth word bit memory _M41 to _M43 .
d. Memory section 4 that stores morning (AM) and afternoon (PM) information in the second word bit memory _M24 .
The bit memory _M44 in the fourth word constitutes a memory section 4f that stores information specifying whether to repeat the time information every day or to finish it only once. For example, addresses 1, 2, and 3 are set in each of the timer memories 4, 5, and 6. A comparison control circuit 8 controls the comparison circuit 7 in response to the carry detection circuit 3 detecting a carry of the time counter 2. That is, when the carry detection signal is input from the carry detection circuit 3, the comparison control circuit 8 first compares the time information set in the first timer memory 4 with the time information of the time counter 2 in the comparison circuit 7. Then, the time information set in the second timer memory 5 and the time information of the time counter 2 are compared, and finally the time information set in the third timer memory 6 and the time information of the time counter 2 are compared. The addresses of each timer memory 4, 5, and 6 are specified so as to compare the numbers. The comparison circuit 7 includes a timer memory 4,
When the time information set in 5 and 6 matches the time information of the time counter 2, the time switch control information set in the corresponding timer memory is supplied to the comparison result judgment circuit 9. The comparison result judgment circuit 9 drives and controls the first time switch control circuit 10 and the second time switch control circuit 11 based on the time switch control information from the comparison circuit 7. Further, the comparison result judgment circuit is configured to drive and control the time switch control circuit with priority given to the OFF information when conflicting time switch control information of ON and OFF is simultaneously input to the same time switch from the comparison circuit 7. ing. In this case, by changing the circuit configuration, it is possible to give priority to the on information, and it is also possible to determine the priority order based on the address number, or it is possible to accept both on and off information. It is also possible to maintain the state. Said first and second
The time switch control circuits 10 and 11 are driven by the comparison result judgment circuit 9 to turn on and off the first and second time switches (not shown), respectively. Reference numeral 12 is an input section, and this input section is used to set the device to time display mode DP and call mode as shown in Fig. 2.
CA, timer setting mode SET, time setting mode
Mode selection switch 12 for setting to CK
a, numeric keys 12b from 0 to 9, morning information setting key (AM) 12c, afternoon information setting key (PM) 12d, first time switch ON setting key (ON ₁ ) 12e, and OFF setting key key (OFF ₁ ) 12f, second time switch ON setting key (ON ₂ ) 12g and setting key (OFF ₂ ) 12h, daily designation key (ED) 12i, setting key (SET) 12j, erase key (C)12
A second display designation key (SEC) 12l is provided. When an input operation is performed using a switch or a key on the input section 12, the input control circuit 13 is activated, and the input control circuit 13 operates to control the address display setting circuit 14, the display mode selection circuit 15, the display setting circuit 16, the timer memory setting circuit 17, and the time counter setting circuit. The input signal is supplied to 18. 19 is a fluorescent display tube, a discharge tube, a light emitting diode,
This display 19 is a dynamic display type digital display made of a liquid crystal or the like, and as shown in FIG.
segment display elements 19c, 19d, 19
It has a 12-hour display configuration consisting of e, 19f and two colon display elements 19g, 19h that indicate the division of hour values. Each segment display element 1
9c, 19d, 19e, 19f are segment elements a, b, c, d, e, f, g as shown in FIG.
It is composed of a 7-segment display element. Further, as shown in FIG. 5, the digital display 19 has a segment display element 19f as a first digit, a segment display element 19e as a second digit, a segment display element 19d as a third digit, and a segment display element 19c as a fourth digit. , AM, and PM display elements 19a, 19b and two colon display elements 19g, 19h as the fifth digit, and each of these digits has a terminal D ₁ , D ₂ , D ₃ , D ₄ , Timing signals are input at a duty cycle of 1/6 from _D5 . In other words _{, the timing signals are D 1 ,} D ₂ , _{D 3 ,}
D ₄ , D ₅ , and D ₄ are input as one cycle, that is, the fourth digit is inputted twice in one cycle. Each of the segment display elements 19c to 19
f connects each segment element a to g to terminals A, B, C,
Commonly connected to D, E, F, and G,
And display element 19a is connected to terminal E, display element 19b is connected to terminal D, display element 19g is connected to terminal F, and display element 19
h are connected to terminal A, respectively. That is, each of the display elements 19a, 19b, 19g, and 19h displays 1 from the six segment elements a to f used to display zero among the segment elements a to g for the segment display elements 19c to 19f. The remaining four segment elements a, b, e, f except for the two segment elements b and c used in
The display element 19a is connected as a segment element e, the display element 19b is connected as a segment element d, the display element 19g is connected as a segment element f, and the display element 19h is connected as a segment element a. Segment drive signals having timer information for each digit are input to each of the terminals A to G in synchronization with the timing signal for each digit. 20 is a display selection circuit provided with a display memory 21 for storing information to be displayed on the display 19, and this display selection circuit 20 has, for example, a time counter on the display 19, a time counter for hours, a minute time counter for seconds, and a sub-second timer. Memory Information Information for displaying five types of information set in the address timer memory and time counter of the timer memory is stored in the display memory 21. As shown in FIG. 8, the display memory 21 has a 6-word configuration of 4 bits per word, and the first word bit memories _M11 to _M14 are memory portions 2 for storing 1-minute information.
1a, 2nd word bit memory _M21 to _M24 = 10
Memory unit 21b for storing hourly unit information, 3rd word bit memory _M31 to _M34 , memory unit 21c for storing 1 hour unit information, 4th word bit memory
Memory section 2 that stores 10 hour information in M ₄₁ to M ₄₄
1d. Further, the memory section 21e stores the morning information in the fifth word bit memory _M51 , and the memory section ₂ stores the afternoon information in the bit memory M52.
1f, bit memory _M53 , colon display element 19g
A memory section 21g that stores information on the bit memory
_M54 constitutes a memory section 21h that stores information on the colon display element 19h. In addition, the sixth word bit memory _M61 is a memory section 21i that stores off information of the second time switch, and a bit memory _M62.
a memory section 21j that stores the on information of the second time switch; a memory section 21k that stores the off information of the first time switch in the bit memory _M63 ;
The bit memory _M64 constitutes a memory section 21l that stores the ON information of the first time switch.
The display memory 21 has the above-mentioned 6-word configuration when storing display information, and the display 19
The structure is adapted to the duty cycle of 6 digits, that is, one cycle is 6 digits. Further, the display memory 21 is used when setting time information in the time counter 2, and when setting time information in the time counter 2 and each of the timer memories 4, 5,
It is also used as a temporary storage device when setting timer information to 6. When the display memory 21 is used as a temporary storage device, it is shortened to a 4-word configuration as shown in FIG.
Correspondence can be established with memory sections 2e, 2f, 2g, and 2h for hour and minute information, morning and afternoon information of time counter 2, and memory sections 4a to 4f of each timer memory 4, 5, and 6. That is, the first word bit memories M ₁₁ to _{M 14} are the memory unit 21a that stores information on the 1 minute range, and the second word bit memories M ₂₁ to
Memory section 21b, 3 for storing 10 minute information in _M23
The memory unit 21c stores time base information in the word bit memories _M31 to _M34 , and the memory unit 21c stores information for controlling the on/off of the first and second time switches in the fourth word bit memories _M41 to _M43 . Part 2
1m, the second word bit memory _M24 stores the morning and afternoon information in the memory section 21n, and the fourth word bit memory _M44 stores information specifying whether to repeat the time information every day or finish it only once. It constitutes a memory section 21p. This display memory 21 stores, for example, 4 words of time value information from the 1st word.
It is designed to be input with a left shift up to the word. 22 is an address selection circuit that determines the address of the timer memory to which timer information is to be set when setting timer information in each timer memory 4, 5, and 6; Determine whether or not timer information is set in memories 4, 5, and 6. If no information is set in the timer memories, specify the timer memory with the lowest address number among them, and all timer memories 4, 5, and 6. When timer information is set in 5 and 6, the contents are notified to the display mode selection circuit 15, display setting circuit 16, and display selection circuit 20. The display setting circuit 16 controls the display selection circuit 20 to receive timer information input from the input section 12. At this time, the display setting circuit 16 uses the morning and afternoon information setting keys 12c and 12d in the input section 12.
Key 1 for setting the first time switch on/off
2e, 12f and the second time switch on/off setting keys 12g, 12h are operated, one side is set to the display memory 21, and when the other is set as negative, reciprocal setting control is performed. I try to do this. For example, when the AM key 12c is operated, "1" is set in the memory section 21e of the display memory 21, and "0" is set in the memory section 21f. Also, when the afternoon key 12d is operated, "1" is stored in the memory section 21f of the display memory 21.
"0" is set in the memory section 21e. This relationship also applies to the on/off keys 12e, 12f, 12g, and 12h of the first and second time switches. Note that when the address selection circuit 22 informs that all addresses contain timer information, the timer information is prohibited from being taken into the display selection circuit 20. When an address is designated by the input section 12, the address display setting circuit 14 notifies the display selection circuit 20 to display the address and the information stored at the address on the display 19. The timer memory setting circuit 17 determines whether the timer information stored in the display memory 21 of the display selection circuit 20 from the input section 12 via the display setting circuit 16 is normal information (the set time is The value must be from 1:00 to 12:59. There must be a morning and afternoon setting. At least one time switch on/off information must be set.) However, when it is determined that the information is normal, the timer information stored in the display memory 21 of the display selection circuit 20 is stored in the timer memory at the address specified by the address selection circuit 22. At this time, the address selection circuit 22 specifies the address of the timer memory in which timer information is to be set, sets the display mode selection circuit 15 to the address display mode, and inputs the address to the display memory 21 of the display selection circuit 20. and controls the digital display 19 to display the specified address. When determining that the information is not normal, the timer memory setting circuit 17 prohibits the timer memory from storing timer information from the display memory 21, and notifies the display mode selection circuit 15 that the information is not normal.
At this time, the display mode selection circuit 15 prohibits switching of the display mode and performs control to maintain the display on the digital display 19 as it is. The determination of normality or abnormality by the timer memory setting circuit 17 is made when timer information is set in the input section 12 and the setting key 12j is operated thereafter. Further, the timer memory setting circuit 17 is configured such that when the call mode CA is set at the input unit 12 and an address is specified using the numeric key 12b, the timer information stored in the timer memory at that address is called and displayed on the display. 19, when the erase key 12k is operated on the input section 12, the timer memory at the designated address is cleared. The time counter setting circuit 18 connects the input section 12 to the display setting circuit 1.
6, the time information stored in the display memory 21 of the display selection circuit 20 is normal information as the time information to be set (the set time is from 1:00 to
Must be the value of 12:59. Must have morning and afternoon settings. ), and when it is determined that the information is normal, the time counter 2 is made to store the time information stored in the display memory 21 of the display selection circuit 20. At this time, counters 2a to 2a that count units lower than the minimum time unit of time information, that is, units of 10 seconds, 1 second, 1/10 second, 1/50 second, or 1/60 second, 2d is reset, and time counting is started anew according to the input frequency from this reset time. At this time, the address selection circuit 22 specifies the clock address, sets the display mode selection circuit 15 to the address display mode, sets the address in the display memory 21 of the display selection circuit 20, and displays the digital display 19.
control so that the specified address is displayed. Further, when it is determined that the information is not normal, the time counter setting circuit 18 sets the time counter 2.
The storage operation of time information from the display memory 21 is prohibited, and the display mode selection circuit 15
inform that the information is not normal. At this time, the display mode selection circuit 15 prohibits switching of the display mode and performs control to maintain the display on the digital display 19 as it is. The judgment of normality or abnormality by the time counter setting circuit 18 is made when the time information is set at the input section 12 and the setting key 12j is then operated. , timer information input from the timer memory selection circuit 17 , time information input from the time counter setting circuit 18 , and address selection information input from the address selection circuit 22 . The display mode to be displayed is determined, and the display mode based on the determination is transmitted to the decoder 23. At this time, especially when the address selection circuit 22 informs that all addresses contain timer information, it instructs the decoder 23 to continue the display mode that notifies this fact. The decoder 23 is a display mode selection circuit 15
The display format of each display element of the display device 19 is determined based on the display mode determination output from the display device 19, and the information in the display memory 21 of the display selection circuit 20 is transferred to the display device based on the determined display format. I am trying to display it at 19. As one display format, the decoder 23 converts the 4-bit signal from the display memory 21 into seven segment drive signals as shown in Table 1, and drives each segment element a to g with the segment drive signals. It takes form. In other words, for "0000" to "1001", 7 each
Segment display elements 19c, 19d, 19e, 1
9f becomes "〓" to "〓", "1100" becomes "〓(C)", "1101" becomes "〓(L)"
So, for "1110" it becomes "〓(U)",
And "1111" is set to be "〓(F)". Note that display of "1010" and "1011" is prohibited. Further, when the display element 19c is driven in the case of "0000", zero display is not performed.

[Table] Another display format for the decoder 23 is to directly drive the four segment elements a, d, e, f with 4-bit signals without decoding the display memory 21, as shown in Table 2. It has a formality. This display format is shown in _FIG .
When energizing each digit with a duty cycle of D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , D ₄ for D ₅ , it is done in the last D ₅ and D ₄ . There is.

[Table] Therefore, for example, if it is now 12:38:58.72 in the afternoon, the counter 2a will count "2" and the counter 2b will count "7" in the time counter 2, as shown in Table 3. , the counter 2c counts "8", the segment 2d counts "5", the counter 2e counts "8", the counter 2f counts "3", and the counter 2g counts "12". ing. In this state, for example, when the mode selection switch 12a is set to the time display mode DP, the display memory 21 receives a bit signal of "8" in the memory section 21a and a bit signal of "3" in the memory section 21b, as shown in Table 4. bit signal,
The memory section 21c receives a bit signal of "2", the memory section 21d receives a bit signal of "1", and the memory section 21
A bit signal of "afternoon" is stored in f. Further, in the memory sections 21g and 21h, a bit signal that intermittently drives the colon display elements 19g and 19h is, for example, "1" for 0 to 4/10 seconds and "0" for 5/10 seconds to 1 second. will be remembered. Then, the display 19 shows D ₁ , D ₂ ,
One cycle consists of six digits D ₃ , D ₄ , D ₅ , and D ₄ , and "8" is initially displayed on the segment display element 19f.
is displayed, and the second segment display element 19e
"3" is displayed on the segment display element 19d, "2" is displayed on the segment display element 19d for the third, "1" is displayed on the segment display element 19c for the fourth, and "1" is displayed on the segment display element 19c for the fifth. ,1
9h is directly driven, and the 6th segment display element 19c is directly driven by a 4-bit signal, but since the bit signal is "0000" at this time, nothing is driven. Therefore, "PM12:38" will be displayed on the display 19 as shown in FIG. Also, in this state, the input section 12
When the seconds display designation key 12l is operated, the display memory 21 receives a bit signal of "2" in the memory section 21a, a bit signal of "7" in the memory section 21b, and a bit signal of "7" in the memory section 21c, as shown in Table 5. is "8"
A bit signal of "5" is stored in the memory section 21d. Further, bit signals are continuously stored in the memory sections 21g and 21h. And on display 19
The six digits of D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , and D ₄ constitute one cycle, and the display element 19f has "2", the display element 19e has "7", the display element 19d has "8", and the display element "5" is displayed on each of the display elements 19c, and the display elements 19g and 19h are directly driven by the 4-bit signal. At this time as well, the segment display element 19c is directly driven by the 4-bit signal in the 6th position, but since the 4-bit signal is "0000", nothing is displayed. Therefore, the display 19 will display "58:72" as shown in FIG. In this way, in the time display mode DP, the time is displayed in hours and minutes, and if the second display designation key 21l is operated in this state, seconds and sub-seconds will be displayed only during that time. Also, for example, turning on each timer memory 4, 5, 6,
The information storage structure of the memory section 4d that stores off information is configured as shown in Table 6, and for example, the first timer memory 4 stores timer information for turning on the first time switch every day at 7:20 a.m. If this is the case, the bit signals in the first timer memory 4 will be as shown in Table 7. In this state, when the mode selection switch 12a is set to call mode CA and the numeric key 12b is operated with "1", address 1 is specified. A bit signal indicating ``1000'' is stored, and the display 19 displays ``1000'' as shown in FIG. When the numeric key 12b is released in this state, the contents of the memory at address 1, that is, the timer information of the first timer memory 4, are stored in the display memory 21 in the form of bit signals shown in Table 9. That is, the memory section 21a receives a "0" bit signal, the memory section 21b receives a "2" bit signal, the memory section 21c receives a "7" bit signal, and so on.
The memory section 21d contains a zero subprocess bit signal, the memory section 21e contains a "morning" bit signal,
The memories 21g and 21h have "colon display element 19".
The bit signals "g, 19h" and the bit signal "first time switch on" are stored in the memory section 21l, respectively. and display 1
9, 6 digits D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , D ₄ are one cycle, and the display element 19f is set to "0", the display element 19e is set to "2", and the display element 19d is set to "7".
are displayed respectively, and segment a of display element 19c, display element 19a, and display elements 19g and 19h are directly driven by the 4-bit signal. Therefore, "AM ^- 7:20" will be displayed on the display 19 as shown in FIG. In this case, " ^- " is set to turn on the first time switch, and ":" is set to display every day.

【table】

【table】

【table】

【table】

【table】

【table】

【table】

[Table] For example, if the second timer memory 5 stores timer information for turning off the second time switch at 9 p.m., the bit signals in the second timer memory 5 will be as shown in Table 10. become. When the numeric key 12b "2" is operated to display the 2nd address as "2000" on the display 19 and the numeric key 12b is released, the memory contents of the 2nd address, that is, the second timer memory 5 are displayed. The timer information is stored in the display memory 21 in the form of bit signals shown in Table 11. That is, the memory section 21a and the memory section 21
The memory section 21c receives a "0" bit signal, the memory section 21c receives a "9" bit signal, the memory section 21d receives a zero suppression bit signal, the memory section 21f receives a "afternoon" bit signal, and the memory section 21i receives a "0" bit signal. Each bit signal of "second time switch off" will be stored. Therefore, the display device 19 has six digits as one cycle.
``0'' is displayed on f, 19e, and ``9'' is displayed on the display element 19d, and the segment e of the display element 19 and the display element 19b are directly driven by the 4-bit signal. Therefore, the display 19 will display "PM=900" as shown in FIG. In this case, "1" is set to indicate that the second time switch is off.

【table】

[Table] In this call mode CA, when the erase key 12k is operated on the input section 12, the timer memory setting circuit 1
7, the timer memory in which the timer information currently being called is stored is cleared. For example, the second timer memory 5, which is currently address 2,
The timer information is called and the digital display 19
If the erase key 12k is operated while the second timer memory 5 is being displayed, the second timer memory 5 will be cleared. Also, for example, when setting timer information in each timer memory 4, 5, 6, the mode selection switch 12
Set a to timer setting mode SET. At this time, if any of the timer memories 4, 5, and 6 has a free space, the address of that timer memory is displayed on the display 19. If two or more timer memories have free space, the one with the smallest address number is displayed. For example, for address 1, "1000", 2
"2000" for street address, "3000" for number 3
The numerical value is displayed on the display 19. Further, when timer information is stored in all of the timer memories 4, 5, and 6, bit signals as shown in Table 12 are stored in the display memory 21. That is, the memory sections 21a and 21b store an "L" bit signal, the memory section 21c stores a "U" bit signal, and the memory section 21d stores an "F" bit signal. As shown in FIG. 15, the characters "FULL" are displayed on the display 19, indicating that none of the timer memories 4, 5, and 6 is empty. Also, this timer setting mode
In SET, the timer information taken into the display memory 21 is cleared by operating the erase key 12k,
The timer information can be reset, but at this time the display on the display 19 changes to the previous address. Note that this clearing operation must be performed before operating the setting key 12j. Further, when setting time information in the time counter 2, the mode selection switch 12a is set to the time setting mode CK. By this setting, bit signals as shown in Table 13 are stored in the display memory 21. In other words, "C" is stored in the memory section 21a.
The memory section 21b stores an "O" bit signal, the memory section 21c stores an "L" bit signal, and the memory section 21d stores a "C" bit signal. However, indicator 1
As shown in FIG. 16, the characters "CLOC" are displayed at 9 to inform that the time is to be set. In this state, if you operate the numeric keys 12b to input time information, the time information will be stored in the memory section 21 of the display memory 21.
a, 21b, 21c, and 21m (FIG. 9) are sequentially taken in by left shift. Note that the "CLOC" display on the display 19 disappears. Then, when the morning or afternoon information setting keys 12c and 12d are operated and the setting key 12j is operated, the time information taken into the display memory 21 is displayed on the counters 2e and 2 of the time counter 2.
f, 2g, and 2h, and at the same time, sub-second counters 2a, 2b, 2c, and 2d are reset. Then, the counter 2a starts counting the AC power frequency. Here, the characters "CLOC" are displayed on the display 19 again, indicating that time setting is possible again. In this time setting mode CK, the display memory 2 can be cleared by operating the erase key 12k.
It becomes possible to reset the time information by clearing the time information imported into 1, but at this time as well, the display 19 will display the characters "CLOC". Note that this clearing operation must be performed before operating the setting key 12j.

【table】

[Table] In this configuration, digital display 1
9 is a display element 19a for displaying morning and afternoon information;
19b and two colon display elements 19g, 19
Since the clocks are driven using the same digit, the time display section of the digital display 19 is set to 5.
It can be driven with a small number of digits. Therefore, even if the number of digits of the display device for displaying timer information is increased by one, only six digits in total are required and it is possible to prevent the display brightness of each display element from decreasing. Moreover, display elements 19a, 19b and 2 displaying morning and afternoon information.
Since the two colon display elements 19g and 19h are used directly without decoding the 4-bit signal unlike the 7-segment display element, the control circuit including the decoder 23 can be simplified in configuration. In the above embodiment, the digital display is used to display time information, but the present invention is not limited to this. For example, the time information can be set such as how many hours a time switch is to be turned on from a certain time. In some cases, time information can also be displayed. Incidentally, in the above embodiment, the control of two time switches has been described, but it is needless to say that the invention is not limited to this. Further, in addition to the time switch, a buzzer circuit may be provided and the buzzer circuit may be energized by the timer output, and by doing so, an alarm operation or wake-up operation can be performed. Further, in the above embodiment, a time counter that counts time based on the commercial power frequency is described, but the invention is not limited to this. It may also be something that counts the time. Further, in the embodiment described above, the time information for operating the timer is set up to the minute range, but the invention is not necessarily limited to this, and for example, time information up to the second range can be set. In this case, the comparison circuit may be configured to compare the time information of the time counter and the time information of the timer memory by detecting a carry from the sub-second range to the second range. Of course, a digital display that can display hours, minutes, and seconds will be used.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention; FIG. 1 is a block diagram showing the circuit configuration, FIG. 2 is a diagram showing the input section, FIG. 3 is a diagram showing the digital display, and FIG.
The figure shows the segment configuration of a 7-segment display element, FIG. 5 shows the specific configuration of a digital display, and FIG. 6 shows the configuration of a time counter.
Figure 7 is a diagram showing the configuration of the timer memory, Figure 8 is a diagram showing the configuration of the display memory, Figure 9 is a memory configuration diagram when the display memory is used as a temporary storage, and Figure 10 is a diagram showing the configuration of the display memory. Information display diagram, Figure 11 is a display diagram of sub-second information, Figures 12 and 13 are timer information display diagrams, Figure 14 is an address display diagram, and Figure 15 is when there is no space in the timer memory. FIG. 16 is a character display diagram at the time of starting time setting. 19...Digital display, 19a...Display element that displays AM, 19b...Display element that displays PM, 19c, 19d, 19e, 19f...Segment display element, 19g, 19h...Colon display element, 23 ……decoder.

Claims (1)

[Scope of Claims] 1. A digital display device comprising at least a display element that displays AM and PM information, a plurality of segment display elements that display hour value information, and two colon display elements that display a division of hour value information; The segment display element of this digital display dynamically displays time information or time information by a segment drive signal and timing signal obtained by decoding a 4-bit signal, and displays AM and PM information. 1. A timer with a digital display comprising display control means for dynamically controlling the display of two colon display elements using an undecoded 4-bit signal and a timing signal. 2. A timer with a digital display according to claim 1, wherein the digital display displays a display element for displaying morning and afternoon information and two colon display elements as the same digit. 3. The display control means performs display control using 4-bit signals when displaying 1 from 6 input lines used when displaying zero among the input lines of the segment drive signal in the 7-segment display element. The remaining 4 lines excluding the 2 input lines
2. A timer with a digital display according to claim 1, wherein the timer is operated using a book input line.