JPS6215895B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to an information processing system in which a central processing unit and a channel processing unit share intermediate buffer storage, and particularly relates to an information processing system in which a central processing unit and a channel processing unit share intermediate buffer storage. The present invention relates to an intermediate buffer storage control method for improving the efficiency of access to intermediate buffer storage by a channel processing device by using different control methods in accessing buffer storage.

(b) Prior art and problems An intermediate buffer storage is provided between a central processing unit, a channel processing unit, and a main storage device, and the central processing unit and the channel processing unit share the intermediate buffer storage, In an information processing system that uses a swap method between the main storage device and intermediate buffer storage, the central processing unit and the channel processing unit access the intermediate buffer storage.

If there is no data in the intermediate buffer storage, that is, if it is not hit, a move out/move in between the main memory and the intermediate buffer storage is performed while writing is being performed to a block in the newly allocated intermediate buffer storage. Then access it. If writing has not been performed, only a move-in is performed from the main memory to the intermediate buffer storage, and then access is made.

If there is data in the intermediate buffer storage, that is, if there is a hit, the intermediate buffer storage is directly accessed without being moved into the intermediate buffer storage from the main memory.

The intermediate buffer storage access control method described above is common to both the central processing unit and the channel processing unit. Further, control is performed between the intermediate buffer storage and the main memory so that the data is always the same except for the part where the store is executed for the intermediate buffer storage.

When a channel processing device makes an access, most of the time it handles 8-byte continuous data, which has the drawback that the hit rate of the intermediate buffer storage is low and the access efficiency of the channel processing device is poor.

(c) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks by adding a byte mark in the case of an n-byte full store and omitting the write move-in operation when the channel processing device stores. An object of the present invention is to provide an intermediate buffer storage control method that improves access efficiency.

(d) Configuration of the Invention The configuration of the present invention has an intermediate buffer storage between the central processing unit, the channel processing unit, and the main storage, and the central processing unit and the channel processing unit have the intermediate buffer storage. In an information processing system that shares a central processing unit and a channel processing unit, when the central processing unit and the channel processing unit access the intermediate buffer storage, mutually different control methods are used, and the channel processing unit performs a full store of n bytes. At the time of writing, a byte mark is attached to the intermediate buffer storage and written to prevent a move-in operation from being performed.

(e) Embodiments of the Invention FIG. 1 shows an example of the configuration of an information processing system to which the present invention is applied. Main storage device 1 and central processing unit 5
There is a memory control device 2 having a built-in intermediate buffer storage 8 between it and the channel processing device 4 .

A move-in is performed between the intermediate buffer storage 3 and the main storage device 1 in units of, for example, 64 bytes via the bus 6, and move-out is performed in units of 64 bytes via the bus 7. Access between the central processing unit 5 and the intermediate buffer storage is performed in units of 8 bytes via the bus 10, and access between the channel processing unit 4 and the intermediate buffer storage 3 is performed in units of 8 bytes via the bus 9. It can be done. 8 from channel processor 4 by bus 8.
A byte full store is detected, in which case move-in is inhibited and a byte mark is forcibly added. For example, an 8-byte full store in the channel processing device 4 writes to the intermediate buffer storage 3 without executing move-in regardless of the presence or absence of data in the intermediate buffer storage 3, and at this time, 1 bit is prepared for 1 byte. Turn on the bite mark.

When access from the central processing unit 5 or the channel processing unit 4 refers to the intermediate buffer storage 3 and allocates a new block to the intermediate buffer storage 3, only data with byte marks is sent to the main memory 1. and move out.

FIG. 2 is a block diagram of a circuit showing one embodiment of the present invention. An address from the central processing unit 5 is input from the terminal A and stored in the address port 11. The address from the channel processing device 4 is input from the terminal B and stored in the address port 12. A signal for adding a byte mark is also stored in the address port 12 at the same time.

The addresses taken out in priority order by the priority selection circuit 13 enter registers 14, 15, 16, and 17, and the addresses entered in registers 15 and 16 select tag sections 20 and 21 of the intermediate buffer storage, and are sent to register 17. The entered address selects the data sections 22 and 23 of the intermediate buffer storage.
The address entered into the register 14 enters the selection circuit 32 via the register 24. The output selected by the address in the intermediate buffer storage tag units 20 and 21 enters the matching circuit 30 or 31 via the register 25 or 26, matches the output of the register 24, and the matching address is sent from the selection circuit 32. The address is sent from terminal E via register 33 as the address of main memory device 1.

The address and byte mark signal from the channel processing device 4 enters the intermediate buffer storage tag unit 20 or 21 via the register 14, and the intermediate buffer storage tag unit 20 selected by the address
Or, the byte mark signal sent from 21 enters register 27 and is sent from terminal F to the move-in/move-out control circuit.

The move-in/move-out control circuit moves out, for example, an 8-byte full word from the intermediate buffer storage to the main memory when a block in the intermediate buffer storage is allocated and the block has a byte mark. After that, the data at the address requested for access is controlled to be moved in from the main memory, and in the case of store access, the store operation is started after the move-in.

However, if the priority selection circuit 13 detects an 8-byte full store from the channel processing device 4, the move-in/move-out control circuit is notified, the move-in is inhibited, and the store operation is immediately started. .

Data is input from the central processing unit 5 or the channel processing unit 4 from the terminal C, passes through the register 18 or 19, and is transferred to the data section 22 or 23 of the intermediate buffer storage at the address specified by the register 17.
is stored in Further, data is input from the main storage device 1 through the terminal D and is stored in the data section 22 or 23 of the intermediate buffer storage in the same manner as described above. The data is read out by the address from the register 17, passed through the register 28 or 29, selected by the selection circuit 34, passed through the register 35, and sent from the terminal G to the central processing unit 5 or the channel processing unit 4. It is also sent to the main memory device 1 from the terminal H via the register 36. In the case of move-in, data is input from terminal D, and in the case of move-out, data is sent out from terminal H.

The above explanation was based on the case where the channel processing device executes an 8-byte full store. However, there are two methods to control access other than an 8-byte full store to an address with a byte mark, but either of these methods can be used. It is possible.

When accessing a part of a block where the byte mark is on, the intermediate buffer storage is directly accessed. Portions whose byte marks are off are accessed after the move-out/move-in is executed.

Access to a block with a byte mark is performed after moving out and then moving in.

(f) Effects of the Invention As explained above, the present invention changes the control method of access to the intermediate buffer storage between the central processing unit and the channel processing unit, which was conventionally the same, to a mutually different method. The access control method of the channel processing unit with a low hit rate is distinguished by adding a byte mark when n bytes are full stored, and the method of moving in and later storing when there is no hit from the main memory is eliminated, and the method of moving in regardless of the hit rate is changed. The time required for move-in can be reduced by storing the data in intermediate buffer storage without having to do so, which has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of an information processing system.
FIG. 2 is a block diagram of a circuit showing one embodiment of the present invention. 1 is a main storage device, 2 is a memory control device, 3 is an intermediate buffer storage, 4 is a channel processing device,
5 is a central processing unit, 11 and 12 are address ports, 13 is a priority selection circuit, 14, 15, 16,
17, 18, 19, 24, 25, 26, 27, 2
8, 29, 33, 35, 36 are registers, 20,
21 is an intermediate buffer storage tag section, 22, 2
3 is the intermediate buffer storage data section, 30,3
1 is a matching circuit, and 32 and 34 are selection circuits.

Claims (1)

[Scope of Claims] 1 Information that has an intermediate buffer storage between a central processing unit, a channel processing unit, and a main memory, and that the central processing unit and the channel processing unit share the intermediate buffer storage. The processing system is configured to detect that the channel processing unit performs an n-byte full store and to inhibit a move-in operation from the main storage to the intermediate buffer storage. intermediate buffer storage control method.