JPS6215902B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access control method, and particularly to a memory access control method in a data processing device.

As shown in Fig. 1, in the conventional memory access control method, if there is only one memory access request from multiple request sources 1-1, 1-2, . If there are memory access requests, the priority order determining circuit 2 determines the acceptance order, and the memory access request information is stacked in the memory access request stack 3 (the case where the number of stacks is 4 is shown here).
Thereafter, memory access processing was performed in the order of reception using a first-in, first-out method. 10-1,1 in the figure
0-2, .
10-2, -, 10-n, 12 is memory access request information ST1, in the memory access request stack 3 that accesses the memory device 4.
〜, one of ST4.

Here, since the memory access time is generally longer than the logic circuit operating time, the memory access request stack 3 may become clogged, and the memory access request information ST1 stored therein may become clogged.
~ Even if there is a memory access request with a higher request priority than ST4, the memory access will not be performed unless all of the previously packed memory access requests are sequentially processed. As a result, high-priority memory access requests are forced to wait longer than the allowable limit, leading to data loss and overruns, especially for memory access requests from high-speed input/output devices as the request source. There were flaws.

Measures such as retrying using firmware or software have been taken as a remedy for this problem, but in some cases, the troublesomeness of retrying and the resulting harm or performance degradation cannot be ignored. The results were obvious.

Furthermore, in recent years, the speed of arithmetic processing units and input/output devices that serve as request sources has increased rapidly, and the above-mentioned trends are expected to become even stronger, so it is expected that a situation will become impossible to avoid using retry methods. .

In other words, as the speed of the arithmetic processing device increases, the frequency of memory access requests from the arithmetic processing device increases proportionally, and the memory access request stack 3 tends to be always occupied by the arithmetic processing device. As devices become faster, the allowable turnaround time required for memory access requests from input/output devices becomes stricter in proportion.

In addition, as another remedy, the memory device 4 is divided into several banks so that each bank can be accessed independently, in order to alleviate such drawbacks, but this requires considerable effort. This involves an increase in the amount of hardware, and at the same time, there is basically no solution to the problem.

In order to keep up with the increasing speed of arithmetic processing units and input/output devices that are request sources, efforts are being made to speed up the memory access control unit and the memory device 4 itself, but in reality, the speed of the memory device 4 itself is increased. It is relatively rare for memory access requests to overlap under adverse conditions, and there is usually still plenty of time on average. In any case, conventional memory access control methods have the disadvantage that data loss and overruns are likely to occur as the speed of the requester for memory access requests increases.

An object of the present invention is to prevent data loss in the input/output device system by making it possible to allocate the next memory cycle depending on the strength of the request source even after the request is stored in the memory access request stack. An object of the present invention is to provide a memory access control method with extremely few overrun failures.

Another object of the present invention is to provide a memory access control system that can prevent data loss and overrun with as little hardware as possible.

In other words, as mentioned above, memory access requests that can be made to wait are made to wait as long as necessary, and requests that cannot be made to wait can be processed first. There is no longer a need to invest in excessive amounts of materials or provide excessive performance.

The memory access control method of the present invention includes: a time clock unit that outputs a time; an addition circuit that adds time information from a request source to the time to generate time information; The memory access request information is combined with the time information.
a memory access request stack that stores a plurality of sets as a set; a comparison circuit that mutually compares a plurality of the stored time information and outputs a comparison result signal that indicates the minimum time information; and a comparison circuit that outputs a comparison result signal that indicates the minimum time information; and a selector that outputs memory access request information to the memory device.

That is, in the memory access control method of the present invention, memory access requests issued from a plurality of request sources are temporarily stored in a memory access request stack according to the order of reception, and the memory device is controlled by the output of the memory access request stack. A memory access control method for accessing a memory is configured by the following means (1) to (6).

(1) Means provided for each request source to send time information, which is wait permissible time interval information determined according to the characteristics of the request source, at the same time as memory access request information.

(2) A time measurement means that measures time at a common system time interval and outputs the time.

(3) The time information described in the preceding paragraph sent from the request source,
Means for adding the time from the time clock section in the previous section.

(4) Stack means capable of storing time information as a result of addition by the addition means and the memory access request information in combination.

(5) Compare the contents of all the time information stored in the time storage section of the stack means and determine that the memory access request with the highest strength (for example, the minimum or maximum value) is stored. A comparison means that outputs the stack number.

(6) Stack selection means for allocating the next memory cycle based on the output of the comparison means.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, in which a plurality of memory access request sources 60-1, 60-2, .
1, 62-2, . . . , wait permissible time interval information generating units 61-1, 61-2, . . . are provided.

The above requester 60-1, 60-2, ~, 60-
Memory access request information 110-1 from n,
110-2, ~, 110-n are access control units 5
The memory access requests are sent to the priority order determination circuit 52 in 0, and priority order control is performed when memory access requests arrive at the same time.

Memory access request information to which access rights have been granted is divided into memory request information 111 and time information 113. Memory request information 111 is stored in the request storage section of the memory request stack 53, and time information 1
13(ti) is added to the time 114(Ti) from the time clock section 55 that constantly measures the time in the adder circuit 56, resulting in time information 115(Ti+ti), which is combined with the memory request information 111 and issued as a memory access request. It is stored in the time storage section of the stack 53.
Of course, if there is no free space in the memory access request stack 53, the above operation is controlled to wait. When storing the time information 115 in the time storage section, the valid bit of the time storage section is set, and is reset later when the memory access request is processed.
The initial values of the above valid bits are all in the reset state.

Next, a description will be given of how one of the plurality of pieces of memory access request information stored in the memory access request stack 53 is selected with the highest degree of urgency, which is the greatest feature of the present invention. Before that, the meaning of each of the time and time-related information that has been released so far will be described below.

Time information ti: Maximum time interval allowed to wait after issuing a memory access request until memory access is granted. Appropriate values are determined depending on the characteristics of the requesting device.

Time Ti: Time at which a memory access request is allowed to be stored in the memory request stack 53.

Time information Ti+ti: Time at which it is permissible to wait the maximum time for allowing memory access in response to a memory access request.

In addition, time information is provided to make the following explanation easier to understand.
The unit of ti and time Ti is the system clock t.

Now, since the plurality of time information Ti+ti stored in the time storage section of the memory access request stack 53 each has the above meaning, the memory access request having the smallest value among them is the most It needs to be processed first. In other words, it is easy to understand that this is the most urgent memory access request.

Therefore, the time information 301, 30 output from the time storage section of the memory access request stack 53
2, 303, and 304 (as shown in FIG. 2, the case where the number of stacks is 4 is described. The same applies hereinafter) are compared in the comparator circuit 57, and the stack number in which the time information having the minimum value is stored is indicated. If the selector 58 is selected using the comparison result signal 116, the memory access request information 112 which is the output of the selector is divided into four pieces of memory access request information 201, 202,
This is memory access request information based on the memory access request with the highest degree of urgency around that time among 203 and 204.

In addition, in the above comparison, the time information 301, 3
The comparison circuit 57 is configured so that if any of 02, 303, and 304 has its valid bit reset, it is excluded from comparison. Further, the valid bit in the time storage unit of the stack number containing the memory access request for which memory access was permitted as described above is reset at the output 117 of the register 59.

Such operations are repeated thereafter, but in short, if the memory device 4 is accessed based on the memory access request information 112, the memory access request with the highest degree of urgency is always met in any memory cycle. Thus, the object of the present invention is achieved.

Note that the bit widths of the time clock section 55, the time storage section of the memory access request stack 53, the addition circuit 56, the comparison circuit 57, and the related signal lines cannot be made very large from an economic standpoint; There is no need to make it too large from the point of view. For this reason, it is necessary to take appropriate measures against overflows in the time clock unit 55 and the adder circuit 56, but this part is omitted in the above-described embodiment.

As can be understood from the above explanation, it is possible to configure an optimal system by appropriately determining each time information ti depending on the characteristics of the request source.

Furthermore, instead of setting the time information ti fixedly using hardware, it can also be made variable so that it can be arbitrarily set using firmware or software, but all of these are included in the present invention. .

FIG. 3 shows an example of how reception of a memory access request and allocation of memory cycle time are performed in accordance with the memory access request of the request source.

Requests 1, 2, 6, indicating the order of request reception in the diagram.
Reference numerals 8, 9, and 11 indicate requests from devices such as arithmetic processing units that, in principle, can make memory accesses wait for a long time. Therefore, the value of time information ti is set large. Further, requests 4, 5, and 10 indicate memory access requests from data channel devices to which high-speed input/output devices are connected, and the value of time information ti is set small. Further, requests 3 and 7 represent requests from data channel devices to which medium-speed input/output devices are connected.

As can be seen from the figure, as long as memory access requests continue, the four memory access request stacks are always in the FULL state and four requests are kept waiting, so the time information Ti + ti is compared four by four, and the minimum Memory cycle time from top to bottom
The situation in which C ₁ , C ₂ , ... are allocated is shown. The numbers are shown inside the circle, and the memory cycle time is allocated to the corresponding memory access requests in the order of the numbers. 〇 indicates that the memory access request has been registered in the corresponding memory access request stack but has not yet been processed, / indicates that the memory access request has already been processed and has been deleted from the stack, and - indicates that the memory access request has not yet arrived. Each represents a memory access request that is not available.

Here, the unit of time is the system clock interval t, and the memory cycle time is 20t.

The concern here is that even if you can wait, you won't have to wait forever, but in reality, every time a memory cycle passes, the cycle time (20t in this case) has elapsed. The priority order of memory access requests that have been kept waiting will gradually become higher. Therefore, at worst, ti/memory cycle time is 400 in the example shown.
t/20t = At or before the 20th time, the memory access request has the highest priority and is always processed. However, in reality, memory access requests with small values of time information ti do not occur consecutively or frequently, and are accepted far before the value of the above equation.

At the right end of FIG. 3, the times at which the requests were actually received and processed are shown, but both indicate that they were processed well before the time information Ti+ti.

It goes without saying that the comparison circuit 57 is configured so that when the time information Ti+ti and the value of the other time information Tj+tj are completely equal, only one of them is selected.

The memory access control method of the present invention adds a time clock section, an addition circuit, and a comparison circuit, and receives time information in addition to memory access request information when a memory access request is made from a request source. By mutually comparing multiple pieces of time information obtained as a result of adding the time information and the time information, and sending memory access request information corresponding to the minimum time information to the memory device, the subsequent memory access requests with high request priority can be processed. Since memory can be accessed first,
A small increase in the amount of hardware has the effect of minimizing failures due to data loss and overrun.

That is, in the memory access control method of the present invention, when a memory access request is stored in a memory access request stack, time information that combines the strength of the request and the reception time is simultaneously stored as a set, and when the next memory cycle is allocated. By configuring the memory device to be accessed by selecting the memory access request that corresponds to the time information with the smallest content in the stack, problems such as data loss and overruns that occur in the input/output device system can be minimized. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram for explaining the operation of the embodiment shown in FIG. 1-1, 1-2, ~, 1-n...Memory access request source, 2...Priority order determining circuit, 3...Memory request stack, 4...Memory device, 10-1, ~10-
n, 11, 12...Memory request information, 60-1, 6
0-2, ~, 60-n...Memory access request source,
61-1, ... Allowable waiting time interval information generation unit, 62
-1,...Memory access request generation unit, 110-
1,110-2, to, 110-n...Memory access request information, 50...Access control unit, 52...Priority order determining circuit, 53...Memory access request stack, 55...Time clock unit, 56...Addition circuit, 57...
Comparison circuit, 58...Selector, 59...Register, 1
11, 201, 202, 203, 204 and 11
2...Memory access request information, 113...Time information, 114...Time, 115, 301, 302, 3
03 and 304...Time information, 116...Comparison result signal, 117...Reset signal.

Claims (1)

[Claims] 1. A time clock unit that outputs a time; an addition circuit that adds time information from a request source to the time to generate time information; and an add circuit that adds time information from a request source to the time to generate time information; a memory access request stack that stores a plurality of sets of time information; a comparison circuit that mutually compares the plurality of stored time information and outputs a comparison result signal instructing the minimum time information; 1. A memory access control method, comprising: a selector that outputs instructed memory access request information to a memory device.