JPS6216009B2 - - Google Patents
Info
- Publication number
- JPS6216009B2 JPS6216009B2 JP55152594A JP15259480A JPS6216009B2 JP S6216009 B2 JPS6216009 B2 JP S6216009B2 JP 55152594 A JP55152594 A JP 55152594A JP 15259480 A JP15259480 A JP 15259480A JP S6216009 B2 JPS6216009 B2 JP S6216009B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- integrated circuit
- wafer
- pad
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
- H10W46/603—Formed on wafers or substrates before dicing and remaining on chips after dicing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に係り、特に集積回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and particularly to integrated circuits.
現在の集積回路は、短期間で、かつ、多品種の
生産を要求されている。その目的で、同一ウエー
ハ上に多数の回路単位を形成することが行なわれ
る。製作されたウエーハは、その後、自動測定機
によつて、電気的にテストされる。その場合、従
来構造のままの多数の回路単位を有したウエーハ
ではそれらを視覚的にしか区別できないために、
自動測定機で、識別することが極めて難しいとい
う欠点があつた。 Current integrated circuits are required to be produced in a wide variety of products in a short period of time. For that purpose, a large number of circuit units are formed on the same wafer. The fabricated wafers are then electrically tested using an automatic measuring machine. In this case, since the wafer has a large number of circuit units with the conventional structure and can only be visually distinguished,
The drawback was that it was extremely difficult to identify using an automatic measuring device.
本発明の目的は、その種の欠点を除去する事で
ある。すなわち、同一ウエーハ上に形成された複
数の回路単位を電気的に容易に識別可能とするこ
とを目的とする。 The aim of the invention is to eliminate such drawbacks. That is, the object is to make it possible to electrically easily identify a plurality of circuit units formed on the same wafer.
本発明によれば、数種の異なる回路単位を有す
る半導体ウエーハに於いて、各回路単位を回路の
種類別に有意づける適切な素子が接続され、かつ
それぞれ異なる回路単位に共通する特定位置に置
かれたパツドを備えることによつて電気的に容易
に区別可能とする。 According to the present invention, in a semiconductor wafer having several types of different circuit units, appropriate elements that give significance to each circuit unit according to the type of circuit are connected and placed at specific positions common to each different circuit unit. This makes it easy to distinguish electrically.
しかして、本発明によれば、数種の回路単位を
有するウエーハを自動測定機によつて、それぞれ
を電気的に容易に識別できることで、それぞれの
回路単位に応じてテストできる様になり、短期間
に、多品種の生産が可能になる。 According to the present invention, a wafer having several types of circuit units can be electrically identified easily using an automatic measuring machine, making it possible to test each circuit unit in a short period of time. In the meantime, it becomes possible to produce a wide variety of products.
次に本発明の好ましい、実施例１、２を図面に
基づいて説明する。 Next, preferred embodiments 1 and 2 of the present invention will be described based on the drawings.
第１例として、２種類の集積回路Ｘ，Ｙを同一
ウエーハに製作する場合について説明する。 As a first example, a case will be described in which two types of integrated circuits X and Y are manufactured on the same wafer.
集積回路Ｘ，Ｙを交互で、かつ、マトリツクス
状に配置したウエーハ１を製作する（第１図
ａ）。それには、本発明によるところの適切な素
子として、集積回路Ｘにはダイオード４、集積回
路Ｙには、ダイオード７を設けてある。更に、両
者は、同一のパツド配置を有し、共通した特定の
位置にパツド３，３′，５，５′を設けてあり、集
積回路Ｘに於いて、パツド３にダイオード４のカ
ソード極、パツド５にアノード極を接続し（第１
図ｂ）、集積回路Ｙに於いて、パツド３′にダイオ
ード７のアノード極、パツド５′にカソード極を
接続（第１図ｃ）しておく。 A wafer 1 in which integrated circuits X and Y are arranged alternately in a matrix is manufactured (FIG. 1a). For this purpose, integrated circuit X is provided with a diode 4 and integrated circuit Y with a diode 7 as suitable elements according to the invention. Furthermore, both have the same pad arrangement, with pads 3, 3', 5, and 5' provided at common specific positions, and in the integrated circuit Connect the anode pole to pad 5 (first
In the integrated circuit Y, the anode electrode of the diode 7 is connected to the pad 3', and the cathode electrode is connected to the pad 5' (FIG. 1c).
そうして、製作されたウエーハを自動測定機に
てテストする。その際、パツド３と５の間又は
３′と５′の間に適当な電圧をかけて調べれば、順
方向特性を示す場合は集積回路Ｘ、逆方向特性を
示す場合は、集積回路Ｙと判定できる。そして、
それぞれの回路機能に応じたテストができる。 The manufactured wafer is then tested using an automatic measuring machine. At that time, if an appropriate voltage is applied between pads 3 and 5 or between pads 3' and 5', it is found that if it exhibits forward characteristics, it is an integrated circuit X, and if it exhibits reverse characteristics, it is an integrated circuit Y. Can be judged. and,
Tests can be performed according to each circuit function.
第２の実施例として、４品種の集積回路Ａ，
Ｂ，Ｃ，Ｄを同一ウエーハ上に製作する場合につ
いて述べる。これも、第１の実施例と同様に、集
積回路Ａ，Ｂ，Ｃ，Ｄを適当に配置したウエーハ
８を製作する（第２図ａ）。それには、本発明に
よる適切な素子として、抵抗１０（抵抗値γ
〔Ω〕）を２個設けてある。 As a second embodiment, four types of integrated circuits A,
The case where B, C, and D are manufactured on the same wafer will be described. Similarly to the first embodiment, a wafer 8 on which integrated circuits A, B, C, and D are appropriately arranged is manufactured (FIG. 2a). For this purpose, a resistor 10 (resistance value γ
[Ω]) are provided.
そして、前例と同様に、特定のパツド１１，１
１′，１１″，１１，１３，１３′，１３″，１３
が設けてあり、集積回Ａに於いて、両者を配線
で短絡し、集積回路Ｂに於いて、抵抗１０を１個
接続し、集積回路Ｃに於いて、抵抗１０を２個直
列接続し、集積回路Ｄに於いては、両者を開放状
態にしておく。 Then, as in the previous example, a specific pad 11,1
1', 11'', 11, 13, 13', 13'', 13
are provided, in integrated circuit A, they are short-circuited with wiring, in integrated circuit B, one resistor 10 is connected, and in integrated circuit C, two resistors 10 are connected in series, In integrated circuit D, both are left open.
そうして、自動測定機で、パツド１１と１３、
１１′と１１″と１３″、１１と１３の抵抗値
を調べれば集積回路Ａの場合はＯ〔Ω〕、集積回
路Ｂの場合はγ〔Ω〕、集積回路Ｃの場合２γ
〔Ω〕、集積回路Ｄの場合は∞〔Ω〕となり、各回
路を識別できる。従つて、各回路機能に応じたテ
ストが可能となる。 Then, with an automatic measuring machine, pads 11 and 13,
If you look at the resistance values of 11', 11'' and 13'', and 11 and 13, you will find that for integrated circuit A it is O [Ω], for integrated circuit B it is γ [Ω], and for integrated circuit C it is 2γ.
[Ω], and ∞[Ω] in the case of integrated circuit D, allowing each circuit to be identified. Therefore, it is possible to perform tests according to each circuit function.
以上の実施例について説明したが、本発明の主
要部分は、数種の異なる回路単位を有する半導体
ウエーハに於いて、
(1)各回路単位を回路の種類別に有意づける適切
な素子を備え、かつ、(2)その素子を接続した、
各々、異なる回路単位に共通する特定の位置に置
かれたパツド
を備えていることにある。 Although the above embodiments have been described, the main part of the present invention is that in a semiconductor wafer having several types of different circuit units, (1) each circuit unit is provided with an appropriate element that makes it significant for each type of circuit, and , (2) the element is connected,
Each has a pad located at a specific location common to different circuit units.
本発明の効果は、各回路単位の識別が、電気的
に容易に行なえるという点にある。 An advantage of the present invention is that each circuit unit can be easily identified electrically.
第１図ａ乃至第１図ｃは、本発明の第１の実施
例を示す平面図、第２図ａ乃至第２図ｅは、本発
明の第２の実施例を示す平面図である。
尚図において、１……実積回路Ｘ，Ｙを配置し
たウエーハ、２……集積回路Ｘ，３，５，３′，
５′……パツド、４，７……ダイオード、１６…
…集積回路Ｙ、１８……集積回路Ａ，Ｂ，Ｃ，Ｄ
を配置したウエーハ、９……集積回路Ａ、１０…
…抵抗Ｒ、１１，１１′，１１″，１１……パツ
ド、１２……配線、１３，１３′，１３″，１３
……パツド、１４……集積回路Ｂ、１５……集積
回路Ｃ、１６……集積回路Ｄ。
1A to 1C are plan views showing a first embodiment of the present invention, and FIGS. 2A to 2E are plan views showing a second embodiment of the present invention. In the figure, 1...a wafer on which actual circuits X and Y are arranged, 2... integrated circuits X, 3, 5, 3',
5'... Pad, 4, 7... Diode, 16...
...Integrated circuit Y, 18...Integrated circuit A, B, C, D
Wafer 9... integrated circuit A, 10...
...Resistance R, 11, 11', 11", 11... Pad, 12... Wiring, 13, 13', 13", 13
...Pad, 14...Integrated circuit B, 15...Integrated circuit C, 16...Integrated circuit D.
Claims (1)
エーハに於いて、前記各回路単位に共通する所定
の位置に２つの測定パツドと各回路単位における
素子とは電気的に分離した小なくとも２つの抵抗
性素子とを設け、前記抵抗性素子は各回路単位の
種類毎に任意の組み合せで前記測定パツドに接続
されていることを特徴とする半導体装置。1. In a semiconductor wafer having a large number of different types of circuit units, there are two measurement pads at predetermined positions common to each of the circuit units, and at least two resistors electrically separated from the elements in each circuit unit. 1. A semiconductor device, wherein the resistive elements are connected to the measurement pads in arbitrary combinations for each type of circuit unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55152594A JPS5776854A (en) | 1980-10-30 | 1980-10-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55152594A JPS5776854A (en) | 1980-10-30 | 1980-10-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5776854A JPS5776854A (en) | 1982-05-14 |
| JPS6216009B2 true JPS6216009B2 (en) | 1987-04-10 |
Family
ID=15543842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55152594A Granted JPS5776854A (en) | 1980-10-30 | 1980-10-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5776854A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5996833U (en) * | 1982-12-20 | 1984-06-30 | クラリオン株式会社 | semiconductor equipment |
| JPS59115642U (en) * | 1983-01-26 | 1984-08-04 | 日本電気アイシ−マイコンシステム株式会社 | semiconductor wafer |
| JPS59159948U (en) * | 1983-04-12 | 1984-10-26 | 日本電気株式会社 | integrated circuit device |
| JPS59215717A (en) * | 1983-05-24 | 1984-12-05 | Nec Corp | Manufacture of semiconductor integrated circuit device |
| JPH07120696B2 (en) * | 1986-02-26 | 1995-12-20 | 富士通株式会社 | Method for manufacturing semiconductor device |
| JPH03273502A (en) * | 1990-03-23 | 1991-12-04 | Matsushita Electric Ind Co Ltd | rotating head device |
-
1980
- 1980-10-30 JP JP55152594A patent/JPS5776854A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5776854A (en) | 1982-05-14 |
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