JPS6216432B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character generator for character display devices such as CRT display devices and dot printers.

In general, this type of character display device selects a corresponding character pattern from a character generator that stores multiple types of character patterns by supplying a character signal, and synchronizes it with the scanning of a printing device or CRT display device. The dot information forming the character pattern is derived and the character is displayed.

With these display devices, the number of characters that can be displayed in one line is limited by the size of the CRT screen and the line length of the printing device, but the number of characters in one line can be increased by reducing the width of each character. be able to.

In order to increase or decrease the number of characters in one line in this way, conventional methods include multiple character generators that store character information with different character widths in each column, and by selecting this character generator, it is possible to create the desired character width. It was designed to generate character information. Therefore, it was necessary to provide many character generators, which was uneconomical.

Further, the display device may include a CRT display device and a printing device. In this case, if one character generator is used for the same purpose, the number of characters for one line of the CRT display device and the number of characters for one line of the printing device will be different, so the display positions of the characters will not match between the two, making it difficult for the operator. The problem arises that it is difficult to see. As a countermeasure to this problem, it has conventionally been necessary to provide character generators with different character widths for the CRT display device and the printing device, respectively.

This invention was made to solve the above problem, and by connecting a character width conversion circuit to a character generator, it is possible to obtain multiple types of character information with different character widths from a common character generator. The object is to provide a character generator.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a character signal generation circuit;
For example, upon receiving an input signal from a character key, a character code signal consisting of multiple bits corresponding to that character is generated.

2 memorizes multiple character patterns
It is a character generator equipped with a ROM2', etc., and has a plurality of storage areas with unique addresses corresponding to the characters to be handled, and the storage area for one character is a 24 x 24 dot matrix in this embodiment. It is composed of corresponding memory bits, and dot information "1" is stored in the memory bit corresponding to a character pattern expressed by a dot matrix. The address of the storage area of the character is specified in this character generator 2 by the character code signal applied from the character signal generator 1, and thereafter by the synchronization signal applied from the synchronization circuit 7 via the OR gate 3. , dot information for one row (horizontal direction) of the dot matrix is sequentially outputted to output terminals O1 to O24 (FIG. 2), and then dot information for the next one column is read out.

The read dot information is applied to a printing device 4, such as an inkjet printer.

In this embodiment, the printing device 4 has one column (vertical direction) 1
This printer has a recording position of 24 dots in a line, and it takes in only one dot in the corresponding column of the 24-bit dot information output to the output terminals O1 to O24 of the character generator 2, so that the dot information "1" is If so, record it in that position, then record it in the second position.
Line, 3rd line...The information output as 24th line is sequentially captured and recorded in the corresponding columns, and by repeating this, one character is created by the point recorded at a predetermined position in the 24 x 24 dot matrix. is beginning to form.

5 is a bit conversion circuit connected to the output side of the character generator 2, which reduces the character width by reducing the 24-bit output of the character generator 2 to, for example, 16 bits, and converts this reduced character information into CRT display device 6
to be applied.

The CRT display device 6 converts the 16-bit parallel output signal of the bit conversion circuit 5 into a serial signal, and sequentially displays a 16×24 dot matrix in synchronization with a raster signal whose screen is scanned by a synchronization signal applied from a synchronization signal 8. Display format characters.

The bit conversion circuit 5 includes, for example, OR gates 51 to 58 as shown in FIG.
It is connected to the O2 and O3 output terminals of the ROM2', and outputs the OR output of the outputs of the output terminals O2 and O3 to the output terminal P2. Note that the output terminal O1 is directly connected to P1.

The other two input terminals of the OR gates 52, 53, 54 are the output terminals O5, O6, O7, O of the ROM2'.
8, O11, and O12, and the output terminals of each OR gate 52, 53, and 54 are connected to terminal P.
4, P6, and P8. Output terminal O
4, O7, and O10 are connected to terminals P3, P5, and P7.

On the other hand, the input terminals of the OR gates 55, 56, 57, 58 are the output terminals O13, O14, ;O of the ROM2'.
16, O17; O19, O20; O22, O23
and the output terminals are terminals P9, P11,
Connected to P13 and P15. Output terminals O15, O18, O21, O24 of ROM2' are directly connected to terminals P10, P12, P14, P16.

As described above, the bit conversion circuit 5 outputs the lower digits of each 3-bit output up to the output terminal O12 of the ROM 2' directly, and the upper 2 digits output the logical sum of the two bits. O13 to O
24 is designed such that the upper digit of each 3-bit output is directly output, and the lower 2 digits are output as the logical sum thereof.

With the above configuration, a character having a width of 24 columns of the dot matrix generated from the ROM 2', that is, the character generator 2, is converted into a character having a width of 16 columns and reduced symmetrically with respect to the center of the dot matrix. be done.

In the circuit shown in FIG. 2, 10 is an address circuit which has terminals A1 to A11 and whose output changes sequentially in response to a synchronizing signal t.
Addresses of ROM2' are specified sequentially.

Further, 11 and 12 are buffers, respectively. Buffer 11 stores the 16-bit output of bit conversion circuit 5 and supplies a character signal to the CRT display device, and buffer 12 stores the output of ROM 2' and supplies it to the printing device. A character signal is supplied to 4.

In the character generator configured as above,
For example, when a character A is input, a character code signal corresponding to A is applied from the character signal generation circuit 1 to the address circuit 10 of the character generator 2, and the ROM
A predetermined address of 2' is specified. and ROM
It is assumed that the dot information is sequentially read out from the first row L1 in FIG. 4 to the output terminals O1 to O24 of 2'. In FIG. 4, the Γ mark represents "0" and the 〓 mark represents "1".

For example, when the second row L2 is read, the ROM
The output terminals O12 and O13 of 2' become "1".

In this way, signals from the respective output terminals O1 to O24 of the ROM 2' are applied to the buffer 12, and the printing device 4 prints a character whose width corresponds to 24 columns of the dot matrix.

On the other hand, the output of ROM2' is OR gate 51 or 5.
8 to output terminals O2, O3; O5, O6;...
A logical sum is calculated for each set of . Therefore, the CRT display device 6 displays characters each having a width of 16 columns.

If we look at this operation regarding the third row L3 in Figure 4,
The outputs of the output terminals O12, O13, and O14 of the ROM 2' are "1", and the printing device 4 prints three dots at the position corresponding to the third line.

On the other hand, the two outputs of the output terminals O13 and O14 of the ROM 2' are logically summed by the OR gate 55 and become one output, and as a result, two dots are displayed on the CRT display device 6 as shown at L3 in FIG. be done.

Thereafter, in the same manner, the character A, which is narrower than the character generated from the character generator 2, is displayed on the CRT display device 6 as shown in FIG.

7 and 8 show examples in which the letter W is displayed on the printing device 4 and the CRT display device 6, respectively.

According to the bit conversion circuit 5 shown in FIG. 2, for example, there is a blank space of three dots between the left dot and the right dot in the eighth line L8 of the character A in FIG. Since the output of the OR gate 55 is "1", the outputs of the terminals P7, P8, and P9 are "1", "0", and "1", which is to the left of the 8th line of the character A displayed on the CRT display device 6. The blank space between the dot and the dot on the right side is one dot, and the resolution is reduced.

The bit conversion circuit shown in FIG. 3 eliminates the above-mentioned problem, and 501 to 508 are inverters, 511 to 518 are AND gates, and 52
1 to 528 are OR gates.

Since each circuit has a similar configuration, one circuit will be explained. The input terminal of inverter 501 is connected to output terminal O1, the output terminal of inverter 501 is connected to one input terminal of AND gate 511, and the input terminal of inverter 501 is connected to one input terminal of AND gate 511. Another input terminal of the gate is connected to the output terminal O2. Further, the output terminal of the AND gate 511 is connected to one input terminal of the OR gate 521, and the other input terminal of the OR gate is connected to the output terminal O3. Also, the output terminal of the OR gate 521 is the terminal P2
It is connected to the.

With this configuration, as in L8 of FIG.
When the output terminals O10 to O14 of ROM2' become "10001", the terminal P7 becomes 1, the terminal P8 becomes "0" because the output of the AND gate 514 is "0", and the output of the inverter 505 becomes "0". Therefore, the output of terminal P9 becomes "0", and as a result, the output of terminals P7 to P10 becomes "1001", and as shown in FIG. 6, two blank spaces are obtained between the left and right dots of the eighth row L8, Resolution is improved.

FIG. 9 shows a case where the letter W is displayed using the bit conversion circuit of FIG.

As mentioned above, the bit conversion circuit 5 is inserted into the CRT display device 6 side so that the character width displayed on the CRT display device is narrower than the character width displayed on the printing device. For CRT
Even if the number of characters that can be displayed on each line of the display device is smaller than the number of characters that can be displayed on one line of the printing device, the same character can now be displayed in the same position on the same line on both devices. , it becomes easier for the operator to read.

Note that the present invention is not limited to the above-described embodiment; for example, by selectively applying the output of a character generator and the output of a bit conversion circuit to a CRT display device (or printing device) via a switching means, It is possible to change the number of characters in one line by changing the character width on the same display device. Such selection is possible, for example, by switching the control signals of the buffers 11 and 12.

As described in detail above, according to the present invention, character information with different widths can be obtained from one character generator, so there is no need to provide multiple character generators as in the past, which is economical and takes up less space. This method is also advantageous in terms of saving the number of dots, and since the number of dots is compressed by a logic compression method using an AND gate, an OR gate, and an inverter, it has the advantage that the configuration is simple and compression distortion is small.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a bit conversion circuit used in the embodiment of FIG. 1, and FIG. 3 is another example of the bit conversion circuit. FIGS. 4 to 9 are circuit diagrams showing various aspects of displayed characters. 1...Character signal generation circuit, 2...Character generator,
4...Printing device, 5...Bit conversion circuit, 6...
CRT display device, 501 to 508... Inverter, 511 to 518... AND gate, 5
21 to 528...or gate.

Claims (1)

[Claims] 1 A character generator that generates pattern information constituting one line of a matrix character pattern using signals on three or more multi-dot signal lines, and an inverter for the first signal of the signals on two adjacent signal lines. and a second signal is directly inputted to an AND gate having two input terminals, and an output signal of the AND gate and a signal of one signal line adjacent to one of the two signal lines. A character generating device comprising an OR gate as an input, and obtaining dot information compressed by the first signal and the signal of the OR gate.