JPS6216434B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern reduction method for various patterns used in display devices and printing devices. Generally, these patterns are stored in a memory called a character generator, and a predetermined pattern is read out using a code and printed or displayed. As is generally known, this character generator requires an enormous storage capacity. In addition, it is necessary to prepare several types of printers of a desired size based on the size of characters to be printed.

Conventionally, the following method has been adopted in this character generator to reduce the storage capacity. In other words, with this method, only standard-sized patterns are stored in the character generator, and if a larger pattern than the standard size is required, the pattern can be enlarged and displayed or printed by leaving a predetermined interval between the patterns. In addition, when a smaller pattern than the standard pattern is required, the pattern is thinned out and used.

However, in such a method, it is better to enlarge the pattern, but when reducing the pattern, it is simply thinned out, so a clear pattern cannot be obtained.

Therefore, it is an object of the present invention to provide a pattern reduction method that eliminates such drawbacks.The purpose of this invention is to provide a pattern reduction method that reduces a pattern composed of 4N+1 columns to 2N+1 columns. a first detecting means for detecting, in each digit, that patterns are mutually present in the same digits of even-numbered columns; The first step of adding a pattern to the same digit as the
The pattern adding means determines, for each digit, in which range of the 2 to 4N/2 columns or the 4N/2+2 to 4N columns the remaining even number column patterns not detected by the first pattern detection means exist. A second detection means detects, and as a result of detection by the second detection means, when a pattern is detected in columns 2 to 4N/2, it is the same as the detected digit in the -1st column from the detected column. Add a pattern to the digits,
When a pattern is detected in columns 4N/2 to 4N, the pattern is added to the same digit as the detected digit in the +1st column from the detected column. This can be achieved by reducing the pattern by adding a predetermined pattern to the odd columns and constructing the desired pattern with the patterns of these odd columns.

The present invention will be explained below with reference to the drawings. FIG. 1 shows an embodiment of the pattern reduction method of the present invention. In the figure, 1 is a character generator, 2
a to 2i are register groups, 3 to 7 are OR gate groups, 8 to 11 are exclusive OR gate groups, 1
2 to 14 represent andgade groups, respectively. 1
is a character generator, and a desired pattern is read out by specifying a predetermined address. These read patterns are stored in registers 2a to 2i for each column. Each gate group 3~
14 each have a number of gates corresponding to the number of digits of the pattern.

Note that FIG. 2 1 shows the pattern before reduction, and FIG. 2 2 shows the pattern after reduction.

First, the principle of the pattern reduction method of the present invention will be explained using FIG. In this example, a pattern of 9 columns x 13 digits is reduced to 5 columns x 13 digits. In order to perform this reduction, in the present invention, the odd numbered columns are used as they are, and the data of the even numbered columns are reduced to the odd numbered columns. In the present invention, this reduction is performed according to the following two regulations.

If pattern data exists in columns adjacent to each other in the same digit in even-numbered columns, pattern data is added to the same digit in the odd-numbered columns between them.
In FIG. 2, digits a and e correspond in the second and fourth columns, and digits i and M correspond in the sixth and eighth columns.

For pattern data in even columns that did not apply above, for data in even columns from the second column to the center column with the center column as the border, a pattern is applied to the same digit in the -1st column for each digit. Data is added, and for data in even-numbered columns from the center column to n columns, pattern data is added to the same digit in the +1st column for each digit. In Figure 2 1, the J digit in the second column, the H digit in the fourth column, the f digit in the sixth column, and the d digit in the eighth column.
The digits correspond. If only the odd numbered columns added in this way are taken out, it will be configured as shown in Fig. 2,
The pattern data indicated by ● is newly added, and the data shown in FIG. 2 is the reduced pattern data.

Next, returning to FIG. 1, a description will be given of an embodiment in which pattern reduction is achieved by achieving the requirements of and described in FIG. 2. First, the AND gate groups 12, 13, and 14 and the OR gate groups 4, 5, and 6 add patterns to odd-numbered digits by determining the above-mentioned regulations.

That is, an and gate group 12 is used to determine whether or not pattern data is stored in each digit in registers 2b and 2d in which adjacent even-numbered data are stored; It is determined whether the above-mentioned regulations are satisfied by the AND gate group 13 that determines storage, and the AND gate group 14 that similarly determines whether pattern data is stored in the registers 2f and 2h, and if it is satisfied, the AND gate group 12, 13, and 14 generate outputs only for the digits that satisfy each digit, and output data from OR gate groups 4, 5, and 6, respectively, so that each output adds a pattern to the same digit as the middle odd number digit. do. This adds the specified pattern described above.

On the other hand, regarding the above-mentioned regulation, the outputs of the AND gate groups 12, 13, 14 used for the determination for adding the prescribed pattern are used, and the outputs of the exclusive OR gate groups 8, 9, 10,
11, and OR gate groups 3, 4, 6, and 7 are used to add patterns. That is, in exclusive-OR gate groups 8, 9, 10, and 11, even-numbered column data (registers 2b, 2d, 2f, 2h
AND gate group 1 is used to extract only pattern data for which no output of AND gate groups 12, 13, and 14 occurs.
2, 13, and 14 are input, and only the digits with the above-mentioned non-standard pattern data are output for each even number column, and the exclusive OR gate groups 8 and 9 each output a pattern in the -1st odd column. Data is input to OR gate groups 3 and 4, respectively, to be added.

On the other hand, exclusive or gate groups 10 and 11
The pattern data detected and output by is input to OR gate groups 6 and 7, respectively, in order to add pattern data to the +1st even column.

In this way, the pattern data added to the odd columns so as to satisfy the above-mentioned regulations is the data that was originally in the odd columns (registers 2a, 2
c, 2e, 2g, 2i) from the OR gate groups 3, 4, 5, 6, and 7. Therefore, the reduced pattern shown in FIG. 2 can be obtained.

As described above, according to the present invention, 4N+1 rows of patterns stored in a character generator, etc.
When reducing the pattern to 2N+1 columns, a pattern more similar to the standard pattern can be created with a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the pattern reduction method of the present invention, FIG. 2 1 shows a pattern before reduction, and FIG. 2 2 shows a pattern after reduction. 3 to 7 are OR gate groups, 8 to 11 are exclusive OR gate groups, and 12 to 14 are AND gate groups, respectively.

Claims (1)

[Claims] 1 A pattern composed of 4N+1 columns is 2N+1
In a pattern reduction method that reduces patterns into columns, a first detection means detects in each digit that patterns exist in the same digits of adjacent even number columns; a first pattern adding means for adding a pattern to the same digit as the detected pattern in an odd numbered column between columns, and a pattern in the remaining even numbered columns not detected by the first pattern detection means is 2 to 4N; /2 column and 4N/2+2 to 4N columns, a second detection means detects for each digit in which range it exists; as a result of the detection by the second detection means, a pattern is detected in columns 2 to 4N/2; is detected, the pattern is added to the same digit as the detected digit in the -1 column from the detected column, and when a pattern is detected in the 4N/2 to 4N columns, the pattern is added from the detected column. A second pattern adding means adds a pattern to the same digit as the detected digit in the +1st column, and each of these means adds a predetermined pattern to the odd numbered columns, and the patterns in the odd numbered columns form a desired pattern. A pattern reduction method characterized by reducing a pattern by configuring it.