JPS6216548B2 - - Google Patents
Info
- Publication number
- JPS6216548B2 JPS6216548B2 JP54040132A JP4013279A JPS6216548B2 JP S6216548 B2 JPS6216548 B2 JP S6216548B2 JP 54040132 A JP54040132 A JP 54040132A JP 4013279 A JP4013279 A JP 4013279A JP S6216548 B2 JPS6216548 B2 JP S6216548B2
- Authority
- JP
- Japan
- Prior art keywords
- phs
- conductive film
- manufacturing
- present
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P54/00—Cutting or separating of wafers, substrates or parts of devices
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体素子の放熱構造の製法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a heat dissipation structure for a semiconductor device.
ガンダイオード、インパツトダイオード等、そ
の取り扱う電力密度の大きな半導体素子にあつて
は、動作部で発生する熱をすみやかに素子外へ放
出して、素子を熱的破壊から守らなければならな
い。動作部で発生する熱を素子外へ能率よく伝達
するための放熱構造の一つとしてプレエーテツ
ド・ヒートシンク(Plated Heat Sink、以下
PHSと記す)と呼ばれるものが実用されている。 When dealing with semiconductor devices such as Gunn diodes and impact diodes, which have a high power density, the heat generated in the operating parts must be promptly released to the outside of the device to protect the device from thermal destruction. Plated heat sink (hereinafter referred to as Plated Heat Sink) is one of the heat dissipation structures to efficiently transfer the heat generated in the operating part to the outside of the element.
PHS (written as PHS) is in practical use.
PHSが実用されている例としてガンダイオード
を取り上げ、その製法および構造を第1図a〜e
に示す。低比抵抗のn形砒化ガリウム(以下
GaAsと記す)の基板1に動作層となる高比抵抗
のn形GaAs2およびオーミツク電極を形成する
ための低比抵抗のn型GaAs3を、エピタキシヤ
ル成長させたウエハーをまず準備する(第1図
a)。低比抵抗であるGaAs基板1およびGaAs層
3の表面に金・ゲルマニウム等の金属を付着、合
金化処理を行なつてオーミツク性のよい電極4お
よび5を形成する(第1図b)。電極5の上に、
金を電解めつきで厚く成長させPHS6とする(第
1図c)。半導体結晶部1,2,3を所定の領域
だけ残して、化学エツチング等で除去し(第1図
d)、最後にPHS部6を切断して個々の素子を完
成する(第1図e)。 Taking the Gunn diode as an example of a practical PHS, its manufacturing method and structure are shown in Figures 1a-e.
Shown below. Low resistivity n-type gallium arsenide (hereinafter
First, a wafer is prepared on which n-type GaAs 2 with a high resistivity to serve as an active layer and n-type GaAs 3 with a low resistivity to form an ohmic electrode are epitaxially grown on a substrate 1 of GaAs (denoted as GaAs) (see Fig. 1). a). Metals such as gold and germanium are deposited on the surfaces of the GaAs substrate 1 and the GaAs layer 3, which have low resistivity, and are alloyed to form electrodes 4 and 5 with good ohmic properties (FIG. 1b). On top of the electrode 5,
Gold is grown thickly by electrolytic plating to form PHS6 (Figure 1c). Semiconductor crystal parts 1, 2, and 3 are removed by chemical etching or the like, leaving only predetermined areas (Fig. 1 d), and finally, the PHS part 6 is cut to complete individual devices (Fig. 1 e). .
以上に述べた従来のPHSの製法には二つの大き
な欠点がある。一つはPHS形成によつて発生する
応力が、第1図cのようにウエハー全面に一続き
にPHS形成される際には非常に大きなものとな
り、そのために半導体結晶に欠陥を生じさせた
り、微小の欠陥を増大させていることが予想され
る。さらに、もう一つの欠点は第1図dで明らか
なように、従来のPHSの製法によればエツチング
により素子分離を行つているので、本来素子にな
り得る半導体結晶の非常に大きな部分を排除せざ
るを得ず、素子の収量が必然的に悪くなるという
ことである。 The conventional PHS manufacturing method described above has two major drawbacks. One is that the stress generated by PHS formation becomes extremely large when PHS is formed continuously over the entire wafer as shown in Figure 1c, which may cause defects in the semiconductor crystal. It is expected that the number of minute defects is increasing. Furthermore, as shown in Figure 1(d), another drawback is that in the conventional PHS manufacturing method, elements are separated by etching, so a very large portion of the semiconductor crystal that could originally become an element must be removed. Unavoidably, the yield of the device inevitably deteriorates.
本発明は、以上に述べた従来のPHSの製法が持
つている欠点を解消しようとするものである。 The present invention aims to eliminate the drawbacks of the conventional PHS manufacturing method described above.
すなわち、本発明によれば素子分離後PHSを電
解メツキで取り付ける製法を得る。 That is, according to the present invention, a manufacturing method is obtained in which the PHS is attached by electrolytic plating after element separation.
以下、第1図にならいガンダイオードの場合を
例に取つて、本発明の一実施例について第2図に
より説明する。本発明の一実施例による製法にお
いても第1図a〜bの過程は従来と同様である。
第1図bまで作られたウエハーを所定の大きさに
ダイヤモンドスクライバーによるスクライビング
等により切断し、切断片11を適当な間隔をもつ
て導電性の膜12の上に並べる(第2図a)。切
断片11の配列のより簡便な方法として、伸展性
のよい導電性の膜の上にウエハーを密着させて切
断し、その後導電性の膜を適宜伸展させることも
可能である。いずれの場合もPHSを形成する面と
は反対の面(電極4の面)を導電性の膜12に密
着させる。導電性の膜12をめつきのための一方
の電極として、切断片11にPHS13を電解めつ
き法にて形成することによつて、導電性の膜12
の上に所定のガンダイオードの素子が並ぶことに
なり(第2図b)、使用に際してはそれらの素子
を導電性の膜12から剥せばよい。 Hereinafter, one embodiment of the present invention will be described with reference to FIG. 2, taking the case of a Gunn diode as an example, based on FIG. 1. In the manufacturing method according to an embodiment of the present invention, the steps shown in FIGS. 1a to 1b are the same as those in the conventional method.
The wafer fabricated up to FIG. 1b is cut into a predetermined size by scribing with a diamond scriber, etc., and the cut pieces 11 are arranged on the conductive film 12 at appropriate intervals (FIG. 2a). As a simpler method for arranging the cut pieces 11, it is also possible to cut the wafer by placing it in close contact with a conductive film with good stretchability, and then stretch the conductive film appropriately. In either case, the surface opposite to the surface on which the PHS is formed (the surface of the electrode 4) is brought into close contact with the conductive film 12. The conductive film 12 is formed by forming the PHS 13 on the cut piece 11 by electrolytic plating, using the conductive film 12 as one electrode for plating.
Predetermined Gunn diode elements are arranged on top (FIG. 2b), and when used, these elements can be peeled off from the conductive film 12.
以上に述べた所で明らかなように、本発明によ
ればPHSに伴なう半導体結晶に対する応力は各素
子単位の大きさで考えればよく、実用上無視し得
る。また、素子収量も飛躍的に増大する。 As is clear from the above description, according to the present invention, the stress on the semiconductor crystal caused by PHS can be considered in terms of the size of each element and can be ignored in practical terms. Moreover, the device yield also increases dramatically.
以上、本発明の実施例としてガンダイオードを
取り上げて説明したが、本発明は他の半導体素子
にも容易に適用できることは明白であろう。 Although the Gunn diode has been described above as an example of the present invention, it is obvious that the present invention can be easily applied to other semiconductor devices.
第1図a〜eは従来のPHSの製法によるガンダ
イオードの製作工程および構造を示す断面図であ
り、第2図a〜bは本発明の一実施例によるPHS
を持つたガンダイオードの製作工程および構造を
示す断面図である。
1,2,3……n形GaAs結晶、4,5……電
極、6,13……PHS、12……導電性の膜。
1A to 1E are cross-sectional views showing the manufacturing process and structure of a Gunn diode according to a conventional PHS manufacturing method, and FIGS. 2A to 2B are cross-sectional views showing a PHS according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the manufacturing process and structure of a Gunn diode having a structure. 1, 2, 3... n-type GaAs crystal, 4, 5... electrode, 6, 13... PHS, 12... conductive film.
Claims (1)
これらの間隔が互いに広げられた状態で導電性膜
で支持し、しかる後、前記導電性膜を通電パスと
して各半導体素子上に放熱体となる金属をめつき
形成することを特徴とする半導体素子の製法。1. A plurality of semiconductor elements cut and separated into individual pieces are supported by a conductive film in a state where the intervals between them are widened, and then the conductive film is used as a current conduction path to serve as a heat sink on each semiconductor element. A method for manufacturing a semiconductor device characterized by forming metal by plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4013279A JPS55133560A (en) | 1979-04-03 | 1979-04-03 | Method of fabricating semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4013279A JPS55133560A (en) | 1979-04-03 | 1979-04-03 | Method of fabricating semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55133560A JPS55133560A (en) | 1980-10-17 |
| JPS6216548B2 true JPS6216548B2 (en) | 1987-04-13 |
Family
ID=12572272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4013279A Granted JPS55133560A (en) | 1979-04-03 | 1979-04-03 | Method of fabricating semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55133560A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2330942B (en) * | 1997-11-04 | 1999-09-15 | Samsung Electronics Co Ltd | Magnetron |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5226869B2 (en) * | 1972-09-09 | 1977-07-16 |
-
1979
- 1979-04-03 JP JP4013279A patent/JPS55133560A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55133560A (en) | 1980-10-17 |
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