JPS6216576B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving device, and in particular to an oscillator (hereinafter referred to as VCO) that changes the oscillation frequency according to a change in voltage.
This invention relates to a heterodyne receiver (hereinafter referred to as a synthesizer tuner) having a local oscillator (hereinafter referred to as a synthesizer/tuner).

A PLL synthesizer tuner oscillates at a certain frequency by detecting the frequency difference or phase difference between the divided oscillation frequency of the VCO and a predetermined reference frequency, and feeding the difference back to the VCO. In this case, the oscillation frequency is determined by the division ratio of the frequency divider that divides the oscillation frequency of the VCO. To obtain the desired VCO oscillation frequency using the PLL method, a variable frequency divider with a variable division ratio is generally used as a frequency divider, the frequency division ratio corresponding to the desired oscillation frequency is memorized, and the memorized frequency division This is done by inputting ratio data to the variable frequency divider.

The frequency change interval in this PLL system must be the greatest common divisor of the inter-office frequencies of the plurality of stations to be received. For this reason, even if the number of broadcast stations to be received is small, if the greatest common divisor of the inter-station frequencies of those stations is an extremely small value, the memory required to store one station is The number of bits increases, which has the disadvantage of increasing the cost of memory. for example
10KHz frequency band from 100KHz to 250KHz
The number of memory bits required to receive 15 broadcast stations distributed at intervals is 4 bits, assuming that the lowest oscillation frequency of the VCO is 100 KHz and the weight of the frequency corresponding to the lowest bit of the memory is 10 KHz. It is sufficient, but the inter-station frequency is 10KHz,
If there are two types of 9KHz, the weight of the lowest bit of the memory must be set to 1KHz, so
To receive all stations distributed from 100KHz to 150KHz, 8 bits of memory is required.

The present invention saves the number of memory bits for storing codes corresponding to oscillation frequencies in a PLL type synthesizer, and provides a relatively inexpensive and practically sufficient synthesizer/tuner.

The present invention will be described in detail below with reference to the drawings.

The figure is a block diagram of an embodiment in which the present invention is applied to a radio receiver using a PLL type synthesizer tuner. In the figure, 7
is a VCO whose oscillation frequency is determined by the error output 59 from the charge pump 6, and this oscillation output 60 is input to the mixer 20 of the radio receiver and the variable frequency divider 3 of the PLL section. 3 is determined by inputting the block frequency division ratio (higher bits of the actual frequency division ratio) 56, which is the data read from block memory 1, and the count data output 57 from counter 2 as the lower bits of the frequency division ratio. with the dividing ratio
The output 60 of the VCO 7 is frequency-divided to obtain a frequency-divided output 58. A phase comparator 5 detects the phase difference between the output 61 from the reference frequency generator 4 and the output 58 from the variable frequency divider 3 and transmits it to the charge pump 6. The charge pump 6 generates a voltage corresponding to the phase difference transmitted from the phase comparator 5, and outputs an error signal 59.
get. 21 is an intermediate frequency filter of the receiver, 22 is an intermediate frequency amplifier, 23 is a detector, 24 is a low frequency amplifier, and 25 is a speaker. Therefore, the broadcast waves input from the antenna 26 are 20, 21, 2
2, 23, and 24, and is output as audio from the speaker 25. Detector 23 outputs broadcast detection signal 55 to logic circuit 30 when broadcasting is being performed at the tuned frequency. The logic circuit 30 transmits the electrical pulses sent from the pulse generator 31 to the counter 2 until the broadcast detection signal 55 is input, but when the broadcast detection signal 55 is input, the logic circuit 30 stops the transmission. The contents of the counter 2 are changed by pulses from the logic circuit 30, and the contents of the counter 2 are reset when the memory read request signal 52 is input. The memory read request signal 52 is also input to the block memory 1, and the memory read signal 52 is input when reading out the data (block frequency division ratio) specified by the address input signal 51 from the data stored in the block memory 1. input. Note that the weight of the bits of the frequency division ratio of the variable frequency divider output 58 is determined by the weight of the least significant bit, that is, the least significant bit of the portion corresponding to the output 57 of the counter 2. The frequency shall be set to be the greatest common divisor of the inter-station frequencies of broadcasting stations.

Next, the specific operation of the embodiment shown in the figure will be explained. The block memory No. 1 stores the encoded upper bits of the frequency division ratio for the variable frequency divider 3 corresponding to the desired frequency in the reception band. In other words, only the upper bits of the frequency division ratio to be input to the variable frequency divider 3 are stored in the block memory 1, and this is called a block frequency division ratio. The address where the desired block frequency division ratio is stored is designated from the address input line 51 to the block memory 1, and
When a read request is made via the read request signal line 52, the specified block frequency division ratio is input to the variable frequency divider 3 via the block data line 56.
At the same time, counter 2 is reset and the contents of counter 2 are input to variable frequency divider 3 via counter output line 57 as the lower bits of the division ratio to variable frequency divider 3. As a result, the VCO oscillates at a frequency based on the division ratio determined by the data on the block data line 56 and the counter output line 57, and the oscillation output 6
0 is input to the mixer 20, and the receiver outputs the oscillation output 6.
Tune to the frequency determined by 0. When broadcasting is not being carried out at the tuned frequency, the electrical pulse from the pulse generator 31 is transmitted to the counter 2 via the logic circuit 30, and the counter 2 updates its contents, and the contents are transferred to the variable frequency divider. 3, the frequency division ratio to the variable frequency divider 3 is also updated, and the receiver updates the tuning frequency. If broadcasting is being performed on a tuned frequency, the detector 23
A broadcast detection signal is input to the logic circuit 30 via the broadcast detection signal line 55, and the logic circuit 30 stops transmitting the pulse from the pulse generator 31 to the counter 2. In this embodiment, even if a large number of bits are required to express the frequency division ratio to the variable frequency divider 3, the contents of the lower bits of the frequency division ratio are determined by the contents of the counter 2. does not need to remember all bits of the divider ratio,
Memory is saved. Moreover, the weight of the lowest bit of the variable frequency divider 3 is set to the greatest common divisor of the inter-office frequencies of the broadcast stations to be received, so all the broadcast stations to be received within the reception band can be received.
Only the memory capacity can be reduced without degrading any of the receiver's original functions, resulting in significant cost reductions.

Although the above description has been made with reference to the embodiment, each part of this embodiment does not need to use any of the circuits described therein, and may be replaced with other circuits or devices that perform similar operations. for example,
It goes without saying that even if the microcomputer and the like are replaced with some of the parts shown in the above embodiments, a device that operates in the same way can be realized.

As described above, the present invention has the great advantage of being able to realize a cheaper receiver with a PLL synthesizer tuner without degrading the functionality of the conventional receiver.

[Brief explanation of the drawing]

The figure is a block diagram of an embodiment in which the present invention is applied to a PLL type synthesizer tuner. Here 1...block memory, 2...counter, 3
...Variable frequency divider, 4...Reference frequency generator, 5...
...Phase comparator, 6...Charge pump, 7...
Voltage controlled oscillator (VCO), 23...reception detector,
30...Logic circuit, 31...Scanning pulse generator.

Claims (1)

[Claims] 1 In a heterodyne receiver that uses a voltage controlled oscillator (VCO) as a receiving local oscillator,
A PLL configured by a variable frequency divider that divides the output frequency of the VCO, and a phase comparator that compares the phase of the output of this frequency divider and a reference oscillator output and feeds back the comparison output to the VCO. Then, the reception frequency band of the receiver is divided into a plurality of blocks, a block frequency division ratio corresponding to one or all of the blocks is stored, and the read data is applied to the variable frequency divider. A block memory that is set to the upper bits, a pulse generator that generates pulses for frequency division ratio scanning, a counter that counts the output of this pulse generator, and an output of this counter that is set to the lower bits of the variable frequency divider. and a received signal detection circuit for producing a control output for causing the counter to stop counting pulses from the pulse generator.