JPS6217239B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a frequency control device for an electronic musical instrument. [Background of the Invention] Conventionally, in order to reduce the capacity of a memory that stores frequency information, such as a ROM, information on a specific octave is stored in the memory, and information on other octaves is stored in this memory. frequency information is generated by shifting it according to the octave.
(See Publication No. 49419). However, performing such shift processing requires a shift circuit for shifting multi-bit data, which has the disadvantage of increasing the burden on hardware. [Object of the Invention] The present invention has been made in view of the above circumstances, and provides a frequency control device for an electronic musical instrument that uses a simple circuit configuration to generate a scale clock corresponding to the scale frequency of a musical tone. The purpose is to [Summary of the Invention] In order to achieve the above object, the present invention reads out frequency information that determines the time length of each block of the output waveform from the frequency information memory according to the scale code of the output musical tone, and performs addition/subtraction on the frequency information that determines the time length of each block of the output waveform. The adding/subtracting means calculates a control value multiplied by 2 ⁿ (n is an integer determined by the octave code) according to the octave code of the musical tone to be generated, for the preset frequency information. , is repeatedly added and subtracted at each reference timing, and when the result satisfies a predetermined condition, a scale clock is generated to increment the block of the output waveform, and the frequency information is selectively read out from the frequency information memory again. The main point is that the frequency information to be used is preset. [Embodiments of the Invention] Hereinafter, embodiments of a frequency control device for an electronic musical instrument according to the present invention will be described in detail with reference to the drawings. <Basic Concept> First, the basic concept of the electronic musical instrument of this system will be explained with reference to the principle block diagram shown in FIG. In Fig. 1, 1 indicates a different pitch input code corresponding to each key operation of a performance key group (for example, 48 pitch keys that enable a basic range of 4 octaves and 12 notes). This pitch input code is supplied to the scale period setting circuit 2 which controls the scale clock frequency. Therefore, a different scale clock frequency signal is generated according to each pitch input code from the scale cycle setting circuit 2, and is sent as a counting step signal to the cycle counting circuit 3, which counts one cycle of the musical sound waveform in multiple steps. supply The period counting circuit 3 is preferably composed of a counter that performs binary counting operation, and in this example, the period counting circuit 3 is configured with a counter that performs a binary counting operation, and in this example, the period counting circuit 3 is configured with a counter that performs a binary counting operation.
This circuit consists of 8 bits weighted with ``16'', ``32'', ``64'', and ``128'', and obtains the counting state of ``256'' from decimal number ``0'' to ``255''. Therefore, one cycle of the musical sound waveform is represented by ``256'' counting steps corresponding to each count value in ``256'' decimal. The ``256'' counting steps are divided into blocks with one or more specific steps as one unit, and one cycle is divided into m blocks. That is, in this example, it is divided into ``16'' blocks with m = 16, and one block consists of ``16'' counting steps (decimal numbers ``0'' to ``15'').
Therefore, the state of the 4-bit count value representing the wait stages "16", "32", "64", and "128" of the period counting circuit 3 can be expressed as a time transition. It can be associated as the address of the accompanying block "16", which is shown in Table 1.

【table】

[Table] The output of each 8-bit stage of the period counting circuit 3 is supplied to the scale period setting circuit 2, which controls the output frequency of the scale clock frequency signal corresponding to the pitch input code, as will be described in detail later. I will be forced to do it. Furthermore, the output of the upper 4 bits (weights ``16'', ``32'', ``64'', ``128'') of the period counting circuit 3 is sent to the waveform program specifying section for each block as a 16-bit block address signal via the decoder 4. 5. This waveform program designation section 5 is designated by one period of musical sound waveforms "0" to "15". The rise of the waveform at each block address,
The amount of change in the falling amplitude (in this example, "0", "1",
The absolute values of "2" and "4") are indicated with + (up) and - (down), and the amount of change in amplitude (that is, the differential value) is called the differential coefficient value. The differential coefficient value and "+" and "-" instruction signals specified for each block address by the waveform program specifying section 5 are sequentially output in synchronization with the block address signal from the decoder 4 and supplied to the multiplier circuit 6. . The multiplier circuit 6 also controls a volume curve creation counter (hereinafter referred to as an envelope counter) 7 that digitally controls volume control to increase or decrease the performance volume as time passes from the time the performance key is operated. A value (counter count value) is supplied, and eventually this control value and the waveform program specifying section 5
The differential coefficient value and the positive and negative values determined according to the "+" and "-" instructions are multiplied in synchronization with the block address. The envelope counter 7 controls a designated clock (referred to as an envelope clock) according to one of the various volume curve (referred to as an envelope hereinafter) modes to be described later, and controls the attack, decay, and release clocks to be described later. It performs up or down counting control according to each volume control state. In other words, the count value of envelope counter 7 is "0"
It is an integer value of ˜31, and will be referred to as an envelope coefficient value (represented by E). One example of envelope mode is shown in FIG. Therefore, the differential coefficient value specified in advance for each block address by the waveform program specifying unit 5 is specified as an integral multiple of the envelope coefficient value E shown in FIG. 2 with "+" or "-". The multiplication circuit 6 calculates ±(differential coefficient value x envelope coefficient value E).
is carried out. That is, FIG. 3 illustrates an example of this, and shows the relationship between the envelope coefficient value E and the differential coefficient value of each block of block addresses "0" to "15" in one period of the musical waveform. Therefore, in the case of Fig. 2, the volume control values at the time when the envelope coefficient value E is "5", "10", "20", and "30" (indicated by an x mark in Fig. 2) are The amount of change in the relative magnitude of the included tone waveforms is as shown in FIGS. 4A, B, and C. Of course, the relative change in the tone waveform changes sequentially depending on the envelope coefficient value E as time passes. In this example, only the block address ``0'' is the differential coefficient value, and ``+'' and ``-'' are not specified, and the amount of change is always zero. The output of the multiplication circuit 6 is supplied to one input side of the adder 8, and the output of the adder 8 is fed back to the other input side of the adder 8 via the accumulator 9. Therefore, the multiplication output of the previous block is The amount of change, which is the multiplication output value of the current block, is accumulated with respect to the value.
The tone waveform diagram of C is taken out as the output of this accumulator 9. The output of the accumulator 9 is converted into a D/A converter (digital-to-analog converter) 10.
The musical tones corresponding to the performance keys operated by the speaker 11 are produced via the speaker 11. <Base structure> Next, the present invention will be explained in detail using a specific example of the structure.
B, C, D, and E, which include logical formulas, truth tables, and general logical symbols corresponding to each logical symbol, as well as examples of combinational circuits. What must be particularly noted here is that the inverter symbol attached to the input line of an OR gate and an AND gate is valid only for that gate.For details, please refer to the combinational circuit examples in each figure. FIG. 6 shows a combined state of FIGS. 7A, B, C, and D. In FIG. 7A, 20 has 4-bit (1, 2, 4, 8 weight) input/output ends, and 8 wires that shift in 4-bit parallel in the direction of the arrow. The scale code register 21 is composed of line memories, and 21 is an octave composed of eight line memories that have input and output terminals of 2 bits (“1” and “2” weights) and shift 2 bits in parallel in the direction of the arrow. This is a code register that stores the scale code and octave code corresponding to each operated performance key. That is, in synchronization with the generation of an input instruction signal related to the operation of a performance key, which will be described later, the corresponding scale code and octave code are AND gates 22 to 27 and OR gate 28-1.
28-4 and are input to the scale code register 20 and octave code register 21 via OR gates 29 and 30, respectively. Then, the input scale code and octave code (hereinafter referred to as pitch code) are sequentially shifted in parallel in the direction of the arrow by a shift pulse φ ₀ (the basic clock of this system), and after a shift time of 8φ ₀ , each Inhibit gates 31-1 to 31 from the output terminal, respectively.
-4 and inhibit gates 32 and 33 to perform a so-called dynamic shift operation. Then, the inhibit gates 31-1 to 31- are activated in synchronization with the new input instruction signal.
4 and inhibit gates 32-33, the pitch codes in each register 20, 21 are controlled to be erased. In addition, since the scale code register 20 and octave code register 21 have eight line memories, for example, even if a maximum of eight performance keys are operated simultaneously, the corresponding scale input code will be input in synchronization with the input instruction signal. Octave input codes can be sequentially input in accordance with the timing order, each dynamically shifted, and cyclically held. In other words, eight sounds are controlled in a time-division manner. The scale chords and octave chords in this system are listed in Tables 2 and 3.

【table】

[Table] Reference numeral 34 denotes a cycle counting register for counting one period (cycle) of a musical sound waveform according to the pitch code stored in circulation in the scale code register 20 and the octave code register 21, and is similar to the above-mentioned scale code register. 20. Like the octave code register 21, it is comprised of eight line memories that are sequentially and dynamically shifted in the direction of the arrow by a shift pulse _φ0 . This cycle count register 34 is basically a 4-bit hexadecimal register (see Table 1) that stores the count value corresponding to the address of each block in order to divide one cycle of the musical waveform into 16 blocks according to the time transition. "0" to "15" shown in
A block counting register 34-1 consists of a block count register 34-1 (corresponding to the block addresses of 16 blocks), and a 4-bit register 34-1 that controls the number of steps for each block, which will be described in detail later, to take out the addition timing signal that commands the increment of the block count. The hexadecimal period count register (TC register) 34-2 and the block count register 34-1 are incremented by 3 counts every cycle.
It consists of a bit octal cycle number register 34-3. The count contents of each line memory generated from the respective outputs of the block count register 34-1 and the cycle number register 34-3 are directly passed through the deformation program designation section 35 for each block, which will be described later, and are further processed by the adder 36 in FIG. 7B. are dynamically cyclically held through the input gates 37-1 to 37-7, which are cyclic gates, and the adder 36, which performs a binary counting step in this cyclic cycle, receives ``+1'' when the above-mentioned addition timing signal is generated. ” He is making progress. In addition, the 4 bits (“1”, “2”,
"4", "8" weight) output (see Figure 8a) is
It is supplied to the block state detection circuit 38 for detecting a specific block address among the 16 block addresses, and from its output, the "0" shown in FIG. 8b is output.
The output signals shown in FIG. 8c are taken out from the block address signals, . . . , respectively. Outputs .about. are supplied to a scale step matrix circuit 39 which determines the number of step corrections for each scale, which will be described in detail later. That is, the output of the block state detection circuit 38 is transmitted to the inverted AND gate 38-1 and the inhibit gates 38-2 and 38-3.
By connecting 8-3 in series, under the condition of [1, 2, 4, 8] where weights "1", "2", "4", and "8" are all "0", "0" block address signal, and the output is the output of weight "1" as is, and the odd block address signal is output as follows.
The outputs are "2", "6",
``10'' and ``14'' block address signals are output when weight ``4'' is ``1'' and weight ``2'' is output.
In order to satisfy the condition [4, 2, 1] that both "1" and "0" are present, inhibit gates 38-5, 38-
6 are connected in series to output "4" and "12" block address signals, and the output is "1" for weight "8" and "0" for weights "4", "2", and "1" [8 .4.2.1], the inhibit gates 38-7 to 83-9 are connected in series and each outputs an "8" block address signal. On the other hand, the period counting register (TC register) 34
The output of each 4-bit stage of -2 is connected to the input of an adder 40, the output of each 5-bit stage of this adder 40 is connected to a subtractor (subtractor) 41, and the 4-bit output of the subtractor 41 is connected to a circulation control gate. The signals are fed back to the input side of the corresponding bit stage via inhibit gates 42-1 to 42-4. Also, the period count register 34-
Each stage output of "2" is an addition timing generation circuit 43 which outputs an addition timing signal supplied to the adder 36 described above according to each octave, and "1".
The 3-bit output of weights "2" and "4" is supplied to a weight shift circuit 44, which will be described later. Furthermore,
The addition timing generation circuit 43 and the weight shift circuit 44 receive the output of an octave code decoder 45 that generates first to fourth octave signals 0 ₁ to _{0 4} according to the 2-bit output state output from the octave code register 21. The signals are combined. That is, the inverted AND gate 45-1 of the octave code decoder 45 inputs the first octave signal ₀₁ to the inhibit gate 45-2.
detects the code states shown in Table 3 above, in which the inhibit gate 45-3 detects the second octave signal _0-2 , the inhibit gate 45-3 detects the third octave signal _0-3 , and the AND gate 45-4 detects the fourth octave signal _0-4 . This is what outputs by doing this. Octave signals 0 ₁ to 0 ₃ are supplied to AND gates 43 - 1 , 43 - 2 and 43 - 3 of the addition timing generation circuit 43, respectively, and octave signals 0 _{to 2} are supplied to AND gates 44 - 1 of the weight shift circuit 44. Signal 0 ₃ is sent to AND gates 44-2 and 44-3, and octave signal 0 ₄ is sent to AND gates 44-4 and 44.
-5 and 44-6. The output signals of "1", "2", and "4" weights of the period counting register 34-2 are coupled to the AND gate 43-1 of the addition timing generation circuit 43 via OR gates 43-4 and 43-5. The "2" and "4" weight output signals output from the OR gate 43-4 are coupled to the AND gate 43-2, and the "8" weight output signal is coupled to the AND gate 43-3. The outputs of these AND gates are coupled to inhibit gates 43-6, 43-7 and an inverted AND gate 43-8, respectively, and an output signal of weight "8" is connected to the inverted AND gate 43-8. are combined. The output of these inverted AND gates 43-8 is sent to the inhibit gate 43-7, and the output of the inhibit gate 43-7 is sent to the inhibit gate 43-6.
is connected in series to the inhibit gate 43-
The above-mentioned addition timing signal is obtained from the output of 6. That is, in one line memory shown in FIG. 9, as can be understood from the counting state of the period counting register 34-2 (FIG. 9a), the output lines of the addition timing generation circuit 43, .
The output signals shown in FIG. 9b are output from the inhibit gate 43-6 in synchronization with the respective generated outputs of octave signals ₀₁ to ₀₄ from the octave code decoder 45. It is taken out as an output signal. That is, for the first octave signal 0 _{to 1} , the period count register 34
-2nd octave signal 0 only when counting “0”
₂ only when counting "0" and "1", 3rd octave signal 0 ₃ only when counting "0" to "3", 4th octave signal 0 ₄ only when counting "0" to "7" The addition timing generation circuit 43 outputs it as an addition timing signal. Then, the addition timing signal obtained in this way is added to the adder 4.
0 as a "+8" addition command signal, and the AND gates 46-1 to 46-4 as a gate opening signal, and the adder 36 in FIG. 7B as a "+8" addition command signal.
1" is also applied as an addition command signal. On the other hand, the octave signals 0 ₁ , 0 ₂ , 0 ₃ , 0 ₄ outputted from the octave code decoder 45 pass through the addition timing generation circuit 43 and pass through the seventh
Each of the subtractors 41 in FIG.
It is supplied as command signals of ``1'', ``-2'', ``-4'', and ``-8''. Therefore, the period count register 34-2
In the circular loop of → adder 40 → subtractor 41 → period counting register 34-2, the adder 40 basically synchronizes with the addition timing signal with respect to the count storage value output from the period counting register 34-2. Then, "+8" is added, and the addition result is a numerical value corresponding to octave signals 0 ₁ to _{0 4} ("-1" for octave signals 0 ₁ , "-2" for octave signals 0 ₂ , and "-2" for octave signals 0 ₃ ). The subtraction operation is performed by "-4", and "-8" for octave signal ₀₄ ). The adder 40 includes AND gates 46-1 to 46-4 that are opened in synchronization with the generation of the addition timing signal.
A step correction number corresponding to the scale is supplied from the scale step matrix circuit 39 in accordance with the block count state of the block count register 34-1. That is, one cycle of the musical waveform consists of 16 block addresses as time progresses, and each block address corresponds to ₈ blocks of the basic clock φ0.
It consists of more than double the number of clocks (8 times the period of the basic clock period). One shot of this basic clock _φ0 corresponds to one step of the musical waveform,
In the end, each block address has more than 8 steps. The highest note in this system is when each of the "16" block addresses in one cycle of the musical waveform has 8 steps, making a total of 128 steps (in fact, as you will see later, in this system,
The highest note is C# ₇ ) with 130 steps). Therefore, by increasing the number of steps between each scale within one octave from the step number of the highest note so that the relationship is a geometric series of ¹² √2 times, the period becomes longer depending on the scale. You will get a lower sound. The number of step corrections for period setting according to this scale is incorporated into a scale step matrix circuit 39, which will be explained next. The scale step matrix circuit 39 in FIG. 7B basically divides the cycle setting value based on the progress (+) of the count in the cycle count register 34 into a coarse number and a fraction, and performs cycle control according to the scale. It memorizes the control values to be set. Therefore, the block state detection circuit 38 described above
The output signals of , , , and the 4-bit output of the scale code register 20 are input.
This scale step matrix circuit 39
is provided with an AND function matrix circuit 39-1 that detects the chord status of each of the 12 scales shown in Table 2, and has 12 output lines corresponding to the scales (C scale shown in the figure). Detection line~
C# scale detection line) is taken out, passes through a first OR function matrix circuit 39-2, a second OR function matrix circuit 39-3, and is coupled to AND gates 39-4 to 39-14. 1st
The OR function matrix circuit 39-2 inputs "0, 0, 1, 1, 2, 2,
3, 4, 5, 5, 6, 7'' is output as a code consisting of three output lines X ₁ , X ₂ , and X ₃ , and the step addend is Each scale is added to each of the 16 blocks. That is, as shown in Table 4.

[Table] The second OR function matrix circuit 39-3 is a circuit for providing a step correction addend corresponding to a coarse number for each scale of one cycle of a musical sound waveform.
In that case, in order to average and add the step correction addend value at the timing of a plurality of block addresses, the output of ~ output from the block state detection circuit 38 is selected according to each scale. As shown in FIG. 8d, the block addresses marked with "O" are selected according to the musical scale. In other words, a plurality of selected block addresses constitute a rough number of control timings. The selection signal is then supplied to the AND gates 39-4 to 39-14 according to the musical scale. Further, the outputs of the AND gates 39-4 to 39-14 are connected to a series circuit of OR gates 39-15 to 39-25, and the output line _X4 of the final OR gate 39-25 outputs "1" to "15" for each scale. A "+1" correction signal is output to the selected block address. That is, the step correction number output from the scale step matrix circuit 39 becomes a periodic control value [step addend for controlling the fractional number+step correction addend according to the coarse number]. Then,
Output line of scale step matrix circuit 39
The output signals from X ₁ , X ₂ , X ₃ , and X ₄ are connected to inhibit gates 47-1 to 47- whose gates are opened except when the "0" block address signal output from the block state detection circuit 38 is generated. 4. Inhibit gates 47-1 to 47-3 are supplied to AND gates 46-2 to 46-4 via corresponding OR gates 48-1 to 48-3, respectively, and the output of inhibit gate 47-4 is supplied to AND gates 46-2 to 46-4, respectively. The signal is supplied to the gate 46-1. Therefore, for other than the "0" block address signal, "+8" and "+1" are added to the step addend for each block address and the selected block address in synchronization with the generation of the addition timing signal.
The step correction addend obtained is supplied to the adder 40 as an addition signal. Furthermore, when a "0" block address signal is generated from the block state detection circuit 38, a "+2" correction value is applied via the OR gate 48-4 and the AND gate 46-2, and in synchronization with the generation of the addition timing signal. This will be added together with the addition of "+8". As a result, the added value for each block address according to the scale supplied to the adder 40 is the highest octave (fourth octave signal O ₄ ) as shown in FIG. The number of steps in one cycle of the tone waveform of each scale is also shown in the right column of FIG. In other words, the number of steps between each scale is ¹² √2 times. Of course, the above-mentioned addition timing signal supplied to the adder 40 is the octave signal O ₁ ~
O ₄ and the value subtracted by the subtractor 41 also differs depending on the octave signals O ₁ to O ₄ , and the octave becomes lower (octave signal
₁ direction), the period of one cycle of the musical sound waveform becomes longer. Thus, the period count register 34, the scale code register 20, and the octave code register 2
1 has 8 line memories, and one cycle of each register in the direction of the arrow is a shift pulse of 8φ ₀ .
Since the musical tone waveform is cycled, control of the tone waveform is performed based on the one cycle, and furthermore, according to this system, by using a shift memory described below, it is possible to control the register at any position within one cycle. That is, in this system, eight line memories are installed in the direction of the arrow on the output sound generation section side (immediately before the D/A conversion circuit) in FIG. 7C, and the basic clock φ ₀
A shift memory 49 that performs a shift operation is provided. This shift memory 49 stores the 3 output from the weight shift circuit 44 described above in FIG.
One of the eight line memories is addressed by a code represented by a bit (1, 2, 4 weights), and the addresses are sequentially addressed starting from the line memory closest to the output side. “0”~
It has become "7". That is, this address designation allows a maximum delay of _8φ0 shift time. Further, the address of this shift memory 49 is specified only when the addition timing signal output from the addition timing generation circuit 43 of FIG. 7A is supplied via the AND gates 50 and 51 of FIG. 7C. , the output signal of the AND gate 51 applied to the shift memory 49 is called an enable signal. In FIG. 7A, the output of the weight "1" of the period counting register 34-2 is applied to the AND gates 44-1, 44-3, and 44-6 of the weight shift circuit 44, and 5 is applied with the output of weight "2", and AND gate 44-4 is applied with the output of weight "4", and AND gate 44-6 is applied to output line _Y1 , and AND gates 44-3 and 44- 5 is or gate 44-7
to output line Y ₂ through AND gate 44-
4 and 44-5 are OR gates 44 to which the outputs of OR gate 44-8 and AND gate 44-1 are supplied.
-9 to output line _Y4 . That is, the 3 lines represented by these output lines Y ₁ , Y ₂ , Y ₄
The bit output is now supplied to the shift memory 49 as an addressing code, and the output of the period counting register 34-2 is the octave signal O ₁ -
According to _O4 , the address specification shown in Table 5 is obtained.

[Table] As will be described in detail later, the output value from the adder 52 is sequentially shifted up by the φ ₀ pulse from the line memory at this designated address and taken out from the output of the shift memory 49. In this way, one cycle of the musical sound waveform for each scale is divided into steps using the reference clock φ ₀ as a unit, and each scale has a different number of steps. Figure 11A
The operation will be explained using . The operation shown in FIG. 11A is for the case where the highest octave is _O4 shown in FIG. 10 and the scale name is "C". Since the addition timing signal is output from the addition timing generation circuit 43 when the period counting register 34 is in the initial state of "0", the OR gate 48- is output in synchronization with the "0" block address signal from the block state detection circuit 38. 4. “+” via AND gate 46-3
The "2" correction value is given together with the "+8" addition command, so the adder 40 adds (0+10). This additional value "10" is converted to "-" by the fourth octave signal _O4 in the subtractor 41.
8'' is subtracted, and the subtracted output value ``2'' is fed back to the period counting register 34-2. Further, the addition timing signal is supplied to the adder 36 as a "+1" addition command, and is also supplied as an enable signal to the shift memory 49 in FIG. 7C. At this time, the address of the shift memory 49 is "0", and the output timing state is such that the output value of the adder 52, which will be described later, can be immediately output from the line memory "0" of the shift memory 49. Next, after <sub>8φ0</sub> shift time, "2" is output from the period count register 34-2, and "1" is output from the block count register 34-1 (see b and e in FIG. 11A, respectively). At this point, the output of the block count register 34-1 is "1", so the scale step matrix circuit 3
9, the output of the block state detection circuit 38 is applied to the matrix circuit 39.
No output signal is generated from , and therefore no step correction number is given to the adder 40, and only the "+8" command is supplied in synchronization with the addition timing signal, and in the end, the addition of (2+8) is It will be done. Furthermore, "-8" is subtracted by the subtractor 41, and the subtracted output value "2" is eventually fed back to the period count register 34-2. Further, a "+1" signal is supplied to the adder 36 in synchronization with the addition timing signal, and the added value "2" is fed back to the block count register 34-1. Furthermore, this addition timing signal is applied to the shift memory 49 as an enable signal, and the output value of the period counting register (TC) 34-2 is "2".
is supplied to the weight shift circuit 44, the "1" signal is taken out from its output <sub>Y2</sub> , and as seen from Table 5, the address "2" of the shift memory 49 is
It is necessary to specify the As a result, the output timing of block address "1" is changed to i in FIG. 11A.
As can be seen from the above, the output from the shift memory 49 is delayed by <sub>2φ0</sub> shift time. That is, there are 10 steps between block addresses "0" and "1". Thereafter, the same operation is repeated, and in the scale "C", the intervals between the following block addresses are 8 steps, and one cycle of the musical sound waveform has 130 steps as shown in FIG.
Further, in FIGS. 11B and 11C, an explanation of the operation for the scales "B" and "C#" in the fourth octave signal <sub>O4</sub> is shown in the same manner as the state diagram in FIG. 11A. FIG. 12 shows details of the shift memory 49 and adder 52 in FIG. 7C.
9-8 is eight line memories each consisting of 10 bits (49-4 to 49-7 are omitted in the drawing).
Shift with base clock <sub>φ0</sub> . An input control circuit 4 is provided on the input side of each line memory 49-1 to 49-8.
9-9 to 49-16 are provided, and although the gate circuit for only one bit is shown in the drawing for simplification, all the bits are made up of similar gate circuits. Also, this shift memory 4
The 3-bit addressing signal <sub>Y1</sub> , <sub>Y2</sub> , <sub>Y4</sub> of the weight shift circuit 44 of FIG. 7A is applied to the decoder 49-17 of No.
Addressing is performed. That is, the line memories 49-1 to 49-1 are stored in the order of addresses "0" to "7".
49-8 is associated with it. Thus, the designation signals of addresses "0" to "7" are supplied to the AND gates 49-18 to 49-18 to which the enable signal is supplied.
49-25, and its output is supplied to input control circuits 49-9 to 49-16. The input control circuits 49-9 to 49-16 input the output of the adder 52 from the line memory at a designated address and sequentially shift it to the output side. Then, from the output of the line memory 49-1, the output adder 4
9-26, D/A via latch circuit 49-27
It is supplied to the conversion circuit (see Figure 1).
Also, the output of the latch circuit 49-27 is output to the output adder 4.
It is accumulated by circulating from 9 to 26. Further, the output of the immediately preceding line memory corresponding to the designated address of line memories 49-1 to 49-8 is applied to the corresponding wait stage of adder 52 via OR gate 49-28 (only 1 bit is shown). . Next, the envelope relationship will be explained. Reference numeral 53 in FIG. 7A is a synchronous set register consisting of eight 1-bit line memories connected in series.
54 in Figure D is an envelope register with 7 bits ('1', '2', '3', '4', '8', '16',
"32",
Eight line memories of ``64'' weight) are connected in parallel in the direction of the arrow, and all of them are sequentially shifted in the direction of the arrow in synchronization with the shift pulse _φ0 . In short, the scale code register 20, octave code register 21, period count register 34, synchronization set register 53, and envelope register 54 are associated with their respective line memories. That is, scale code register 2
0, the control output corresponding to the pitch code output from the octave code register 21 is generated from the period count register 34, the synchronization set register 53, and the envelope register 54. 5 of the weights “1”, “2”, “4”, “8”, and “16” of the envelope register 54
32 of “0” to “31” represented by bit output
The envelope coefficient value is indicated by the count value, and the two bits of weight "32" and "64" indicate the four envelope states of attack, decay, release, and clear of the envelope. Thus, the 7-bit output from each stage of the envelope register 54 is applied to the corresponding weight input terminal of the adder 55 in FIG. 7C. Adder 5 that counts the envelope control value in this adder 55
Each bit output of 5-1 is controlled by an inhibit gate 56-1 which inhibits output when the carry output signal is present.
.about.56-5 to the corresponding input sides of the weights "1", "2", "4", "8", and "16" of the envelope register. Also, adder 55-
The carry output signal generated from 1 is an inhibit gate whose gate is prohibited by the output of the inverted AND gate 57 which detects the clear state of "00" at the state detection weights "32" and "64" of the envelope register 54. 55-2 to the carry input terminal of adder 55-3 for state counting. That is, the adder 55-3 accepts the carry output signal except in the envelope clear state. The output of the adder 55-3 is then held in circulation at the weight input terminals "32" and "64" of the envelope register 54 via inhibit gates 58-1 and 58-2. In addition, the input instruction signal of the performance key in FIG. The envelope is therefore immediately placed in the attack state. Here, the relationship between the envelope state and the 2-bit code state with weights “32” and “64” is expressed as
It is shown in the table.

〔Effect of the invention〕

As described in detail above, the present invention enables the frequency information memory storing the frequency information that determines the time length between each block of the output waveform to correspond to the 12-tone scale of a specific octave, to The corresponding frequency information is read out and preset in the adding/subtracting means, and the adding/subtracting means converts the preset frequency information into a value of 2 ⁿ (n is an integer and corresponds to the octave code) according to the octave code of the musical tone to be generated. The multiplied control value (determined by the code) is repeatedly added and subtracted at each reference timing, and when the result satisfies a predetermined condition, a scale clock is generated and the block of the output waveform is incremented. , the frequency information selectively read out from the frequency information memory is preset and the same operation is performed again.
It has a simple circuit configuration and has the advantage of being able to generate clocks of any octave and any scale without the need for a shift circuit, making it ideal for LSI implementation.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle configuration based on the basic concept of this system, Figure 2 is a diagram of the envelope mode used in Figure 1, Figure 3 is a basic explanatory diagram of the tone waveform setting method in Figure 1, 4A, B, and C are diagrams showing relative changes in musical sound waveforms according to envelope coefficient values; FIGS. 5A, B, C, D, E, and F are diagrams explaining logical symbols used in this embodiment; Figure 6 is the 7th
Diagram showing the connection state of diagrams A, B, C, and D, No. 7
Figures A, B, C, and D are specific circuit configuration diagrams of the heart of this system, and Figure 8 is a time diagram showing selected output states according to scales related to the block address states in Figures 7 A and B. Chart, Figure 9 is Figure 7A
Figure 10 is a diagram explaining the number of scale steps in Figures 7A and B, and Figure 11 A, B, and C are time charts showing the addition timing output for each octave related to the synchronization register of this system. FIG. 12 is a detailed diagram of the shift memory in FIG. 7C, FIG. 13 is a diagram showing the types of volume curve formats used in this system, Fig. 14 is a diagram explaining the combination of volume curve formats for α and β in this system, Fig. 15 is an explanatory diagram based on block address specification for α and β of musical sound waveforms in this system, and Fig. 16 is a detailed diagram of the waveform program designation section in Figure 7A, Figure 17 is a diagram explaining the output addition value in Figure 7C, and Figure 18 is a diagram of the cycle number counter in Figure 7A. Time chart, 1st
FIG. 9 is an explanatory diagram explaining the basic relationship between the number of cycles and duty used to explain FIG. Figures 22 and 23
The figure is a waveform diagram explaining tremolo control used in this system, and FIGS. 24A and 24B are waveform diagrams explaining plucked string sound tremolo control used in this system.
Figure 25 is a diagram explaining the connection state of Figures 26A and B, Figures 26A and B are Figures 7A, B, C, and D.
Specific circuit diagram of the control unit that controls the 2nd
Figures 7A and B are time charts related to the ensemble in Figure 26A, Figures 28A and B are time charts related to key input timing and synchronization signals in Figure 26B, and Figure 29 is a time chart related to various FIG. 30 is a diagram explaining the time clock selection state based on the clock time generation circuit, FIG. 30 is a time chart of vibrato control in this system, and FIG. 31 is a diagram explaining the rise state of various volume levels as the attack changes over time. , FIG. 32 is a diagram illustrating various changes in volume due to changes over time at the decay time, and FIG. 33 is a diagram illustrating changes in volume due to changes over time at the time of release. 1... Pitch input code register, 2... Cycle setting circuit, 3... Waveform cycle counting circuit, 5... Waveform program specification section for each block, 6... Multiplication circuit,
7... Volume curve creation counter, 8... Adder, 9
... Accumulator, 11 ... Speaker, 20 ... Scale code register, 21 ... Octave code register, 34 ... Period count register, 36 ... Adder, 39 ... Scale step matrix circuit, 4
0...Adder, 41...Subtractor, 74...
...Periodic control circuit.

Claims (1)

[Claims] 1. A frequency information memory that stores frequency information that corresponds to a 12-tone scale of a specific octave and determines the time length between each block of the output waveform, and a frequency information memory that stores frequency information that determines the time length between each block of the output waveform; an addition/subtraction means in which the frequency information corresponding to the time length is selectively read out and preset each time; control means for repeatedly adding and subtracting the control value multiplied by 2 ⁿ (n is an integer determined by the octave code) at each reference timing; means for outputting a scale clock to increment the block of the output waveform when the frequency is reached, and again presetting the frequency information selectively read out from the frequency information memory for the addition/subtraction means; A frequency control device for an electronic musical instrument equipped with.