JPS6217251B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an asynchronous processing device for outputting data from a plurality of stations to a digital signal processing device.

Conventionally, there are the following methods for outputting data from n stations as a digital signal.

In FIG. 1, 10 is a digital signal generation source (hereinafter abbreviated as DSG) which outputs data to a digital signal processing device (hereinafter abbreviated as DSR) 2. In FIG. Similarly for each DSG11~1n
Output data to DSR2. In such a device, each of the DSGs 10 to 1n has a different operating speed (BPS), and when outputting data to the DSR 2, the DSG with a faster operating speed is in a waiting state, wasting time. This is a so-called synchronous processing method. This synchronous processing method naturally slows down the processing speed, and
Each DSG 10 to 1n must have a function of transmitting data after inputting the select signal from the DSR 2. Therefore, the method shown in Figure 2 was devised.

In FIG. 2, 31 to 3n are latch circuits that latch and store data at the timing from each DSG 10 to 1n. The DSR 2 selects each of the latch circuits 31 to 3n as necessary, and inputs data from the selected latch circuit. However, this method also requires n independent memories, and since each DSG10 to 1n and DSR2 operate asynchronously, there are drawbacks such as data loss when data writing and reading overlap. It was hot.

The present invention has been made in view of the above circumstances, and its purpose is to prevent data from being missed when outputting data from multiple DSGs to a DSR, and to quickly transfer data desired by the DSR. The aim is to provide processing equipment.

Hereinafter, the present invention will be explained in detail based on FIGS. 3 to 5.

In Figure 3, the same symbols as in Figure 1 are
Indicates the same code or corresponding part.

In the figure, 4 is an asynchronous processing device including a data selector 41, a memory circuit 42, a latch circuit 43,
It consists of an address gate 44, a control circuit 45, and a clock counter 46. Data selector 41
inputs data from each DSG 10 to 1n in a time-division manner based on the scanner address signal from the clock counter 46, and outputs the data to the storage circuit 42. The storage circuit 42 stores data from each of the DSGs 10 to 1n, and each of these data is latched in a latch circuit 43 based on an address signal inputted from an address gate 44, and the data is output to the DSR2. address gate 44
inputs the scanner address from the clock counter 46 and the frame address signal from the DSR 2, and outputs one of the two address signals to the storage circuit 42 in response to a control signal from the control circuit 45. The control circuit 45 receives a scanner counter signal (hereinafter referred to as
(abbreviated as SSC) is input, and when the frame address signal from the DSR 2 is updated, a control signal is output to the address gate 44 so that the address gate 44 selects the frame address signal, and at this time, While outputting the read signal R to the memory circuit 42, the latch circuit 43
The TMLATCH signal is output to cause the latch circuit 43 to latch the data. When the frame address is not updated, the control signal is not output, the address gate 44 outputs the scanner address signal to the storage circuit 42, and the control circuit 45
A write signal W is output to the memory circuit 42. The clock counter 46 divides the frequency of the reference clock.
It outputs SC0 to the control circuit 45, and also outputs a scanner address signal to the data selector 41 and address gate 44. This scanner address signal is updated every TM1 as shown in FIG. do.

When the DSR 2 requires data from each DSG 10 to 1n, it outputs a frame address signal of the required data to the address gate 44 and the control circuit 45, and inputs the data from the latch circuit 43.

FIG. 4 is a graph diagram showing the timing of this processing device. In the figure, A is a signal output from the clock counter 46 to the control circuit 45 at SC0. B and C are control circuits 45 at SC1 and SC2, respectively.
Created based on SC0. D is the frame address signal. Ho is the scanner address signal. F is an address signal output from the address gate 44. G, C,
RI and NU are TM1, TM2, TM3, and TM4, respectively, and four states are created by the control circuit 45 from SC1 and SC2. Signals for these four states are generated at the timing of SC0, and these are TM1 and TM1, respectively.
They become TM2, TM3, and TM4. A control signal is output from the control circuit 45 to the address gate 44. 0 is a TMLATCH signal which is output from the control circuit 45 to the latch circuit 43.

The operation of the device configured as described above will be explained next.

Now, the data selector 41 is the Kurotsuke counter 4.
Based on the scanner address signal inputted from DSG 6 through bus 105, data is inputted from each DSG 10 to 1n in a time-division manner and outputted to storage circuit 42 through bus 100. At this time, the control circuit 4
5 outputs the write signal W to the memory circuit 42 through the signal line 201 at the timing of TM4 as shown in FIG.
Output to. Then, the storage circuit 42 stores the data at the address pointed to by the scanner address signal. Then, as shown in FIG. 4E, the scanner address signal is updated at the timing of TM1 shown in FIG.
~1n data are stored.

At this time, the DSR 2 outputs a frame address signal of the required data to the address gate and control circuit 45 through the bus 104. Control circuit 4
5 detects a change in the frame address signal as shown in FIG. This control signal continues to be output until the rising edge signal of SC2 is output. Address gate 44 outputs a frame address signal to storage circuit 42 since the control signal is output thereto. Then, the control circuit 45 controls the signal line 20 at the timing of TM1.
1 to output the read signal R to the storage circuit 42, and output the latch signal R as shown in FIG.
TMLATCH is output to the latch circuit 43 through the signal line 202. Then, the data stored in the memory circuit 42 is latched and transmitted through the bus 102.
Output to DSR2. When the control signal is turned off, the address gate 44 outputs a scanner address signal to the memory circuit 42 through the bus 103, and writes data from each DSG 10 to 1n into the memory circuit 42. By doing this, n
Station data is transferred to DSR2. That is,
Of the four states for one scanner address signal, the first two states are opened for reading when updating a frame address, and are used for writing in other cases.

Next, FIG. 5 shows another embodiment.

In this embodiment, a plurality of data from one station is transferred to n stations, and although it is not necessary for parallel-parallel asynchronous processing, there is a parallel-to-serial converter (hereinafter abbreviated as P/S) in the data distributor. ) is required.

In Fig. 5, the same symbols as in Fig. 3 are:
Indicates the same name or equivalent part. In the figure, 1 is a DSG, which is a data output source for n stations. 47
is a second memory circuit which inputs data from the first latch circuit 43 and outputs it to the second latch circuit 48. The role of this memory circuit 47 is to perform high-speed time sharing processing, so scanning cannot be stopped until the P/S for one station is completed. That is, since scanning is faster than the P/S bit count, the parallel data for one station must be held until the P/S finishes sending out the parallel data. Therefore, the memory circuit 47 is in charge of this role. 49 is a data distributor which inputs data from the latch circuit 48, converts it into a serial signal, and transmits the data to each latch circuit 50 to
5n to each DSR 60 to 6n. Clock counter 46 outputs a scanner address signal to address gate 44, memory circuit 47, and data reviewer 49.

The operation of the device configured as described above will be explained next.

Now, from DSG1 to bus 1 to address gate 44
A frame address signal is input from the clock counter 46 through the bus 114, and a scanner address signal is input from the clock counter 46 through the bus 114. At this time, the control signal from the control circuit 45 is transmitted to the signal line 21.
5 to the address gate 44, the address gate 44 outputs the frame signal to the first storage circuit 42 through the bus 113. At the same time, the write signal W is sent from the control circuit 45 to the signal line 2.
11 to the storage circuit 42. Then
Data from DSG1 is stored in storage circuit 42 based on the frame address signal. When the control circuit 45 turns off the control signal, it outputs the scanner address signal from the address gate 44 to the storage circuit 42 through the bus 113. At this time, the control circuit 45 outputs the read signal R to the memory circuit 42 through the signal line 211, outputs the write signal W to the memory circuit 47 through the signal line 213, and outputs the latch signal LTM1 to the latch circuit through the signal line 212. 43. Then, data is latched from the memory circuit 42 to the latch circuit 43 based on the scanner address signal,
Data is stored in storage circuit 47 through bus 112. Then, the read signal R from the control circuit 45 is outputted to the storage circuit 47 and the data distributor 49 through the signal line 213, and the latch signal
LTM2 is passed through the signal line 214 to the latch circuit 48.
When output to the scanner address signal, the data stored in the memory circuit 47 is transferred to the latch circuit 48.
is latched and input to the data distributor 49. P/S is then performed by the data distributor 49 and output to each DSR 60-6n via each latch circuit 50-51.

As described above, the present invention creates four states using the scanner counter from the clock counter 46, and processes asynchronous data based on these states, which eliminates the waiting time for signal exchange and improves processing speed. It also prevents data from being lost due to overlapping read/write timing, and can be applied to high-speed time sharing systems. Since this device alone can perform asynchronous processing, functions are simplified, such as eliminating the need for scanning-related synchronization circuits on the data generation and reception sides. Further, it has excellent advantages such as the ability to assemble a system without changing the functions of the conventional signal generation side and reception side.

[Brief explanation of the drawing]

Figure 1 shows the conventional synchronous data processing method.
Figure 2 shows the conventional asynchronous data processing method.
Fig. 3 is a configuration diagram showing one embodiment of the present invention;
The figure is a timing chart for explaining the present invention, and FIG. 5 is a configuration diagram showing another embodiment of the present invention. 1,10~1n is DSG, 2,60~6n is
DDSR, 4 is an asynchronous processing device, 41 is a data selector, 42, 47 are storage circuits, 43, 48, 50
~5n is a latch circuit, 44 is an address gate, 4
45 is a control circuit, and 46 is a clock counter.

Claims (1)

[Claims] 1. In a device that asynchronously outputs data from a plurality of digital signal generation sources to a digital signal processing device, a scanner address signal is output to a data selector and an address gate, and a scanner counter signal is sent to a control circuit. A clock counter that outputs a clock counter, a storage circuit that stores data from the digital signal generation source via a data selector, and a control signal that is output to the address gate by dividing the scanner counter signal into two states: write and read. At the same time, a control circuit that outputs a latch signal to the latch circuit, a scanner address signal, and a frame address signal from the digital signal processing device are input, and one of the address signals of the two signals is input to the storage circuit according to the control signal. 1. An asynchronous processing device comprising: an address gate that outputs; and a latch circuit that latches data from a storage circuit in response to a latch signal and outputs the data to the digital signal processing device. 2 Output a plurality of data In a device that asynchronously outputs data from a digital signal generation source to a plurality of digital signal processing devices, a scanner address signal is output to an address gate, a second storage circuit, and a data distributor. In addition, a clock counter outputs the scanner counter signal to the control circuit, a control signal is output to the address gate by dividing the scanner counter signal into two states, write and read, and a latch signal is output to the first latch. a control circuit that outputs a scanner address signal and a frame address signal from the digital signal generation source to a second latch circuit;
a first memory circuit that stores data from the digital signal generation source based on the frame address signal; and a second memory circuit that stores data latched from the first circuit. and a data distributor that inputs the latched data from the second storage circuit, performs parallel-to-serial conversion, and outputs the converted data to the digital signal processing device via the latching circuit. Device.