JPS6217264B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a processor control method.

In particular, a processor control method for an information processing device that includes a plurality of processors, each of which has the function of detecting its own abnormality and can operate in parallel, and a processor common control section that performs common control for all of the plurality of processors. Regarding.

Furthermore, a processor, a processor common control section,
A processor control method for an information processing device in which data is exchanged between so-called central processing unit devices such as an input/output control device and a memory unit via a data bus that connects the central processing unit devices. Regarding.

In such information processing devices, the central processing unit units are integrated via a data bus, so if the system, especially the processor, becomes abnormal, abnormal data will mix with normal data. It is often extremely difficult to investigate the cause of the abnormality.

In order to avoid such damage, conventional processor control systems of this type directly connect a data bus that connects central processing unit devices to each processor and between each processor and a processor common control section. It is equipped with an abnormality report line and an abnormal state data bus that connects each of the processors and between each processor and the processor common control section, and further includes a bus connection between the processors or between each processor and the processor common control section for each processor. a normal transmitting/receiving means for sending and receiving normal data between the processors; and a normal transmitting/receiving means for transmitting and receiving normal data between the processors; and abnormality transmission means for transmitting abnormal state data to the processor common control unit.

In such a conventional configuration, normal data and abnormal state data are transmitted via separate buses, so the two do not mix, but the interface line on the processor common control unit side and the interface circuit attached to it This has the drawback of increasing the amount of hardware required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a processor control method that facilitates investigation of the cause of an abnormality by increasing the amount of hardware to a minimum.

The method of the present invention is an information processing apparatus that includes a plurality of processors, each of which has a function of detecting its own abnormal state and can operate in parallel, and a processor common control section that performs common control for all of the plurality of processors. A data bus that connects the central processing unit of the information processing device including the processor and the processor common control unit, and a data bus that directly connects each of the processors and between each of the processors and the processor common control unit. Further, for each of the processors, the processor that has detected an abnormality transmits the abnormality to all other processors and the processor common control section via the abnormality report line. abnormality transmission means for transmitting its own abnormal state data to the processor common control section via the data bus; and a processor common control section between the processors or between the processors and the processor common control section when all the processors do not detect the abnormality. and a normal time transmitting/receiving means for sending and receiving normal data between the processor itself and the normal time transmitting/receiving means of its own processor when it does not detect the abnormality but the abnormality sending means of another processor is transmitting the abnormality. and suppressing means for suppressing transmission of the normal data.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment includes two processors 1 and 2, two bus transmission/reception circuits 3 and 4, a processor common control section 5, a data bus 10, an abnormality report line 20,
A set of transmission data lines 11 and 21, two sets of reception data lines 12 and 22, and two sets of abnormal state data lines 1.
3 and 23, two abnormality detection lines 14 and 24, and two data transmission instruction lines 15 and 25.

An input/output control device and a memory unit (both not shown) are connected to the data bus 10, and the processor common control unit 5 is connected to a host processor (not shown) via a data line 50, and also receives error data. It is connected to an external display device, a magnetic disk device (none of which are shown), etc. via a line 60.

FIG. 2 is a circuit diagram showing details of the data transmitting and receiving circuit 3 of the embodiment shown in FIG. 1, and includes two receivers 3A, 3D and two drivers 3B, 3C.
, three gates 3E, 3F, 3G and selection circuit 3
It is composed of H. The data transmitting/receiving circuit 4 is also not shown because it has a similar configuration, but the receivers 3A, 3D, drivers 3B, 3C, gates 3E,
3F3G and selection circuit 3H, receivers 4A, 4D, drivers 4B, 4C, gate 4
It has E, 4F, 4G and a selection circuit 4H. Drivers 3B and 3C connect the outputs of gate 3F and selection circuit 3H to abnormality report line 20 and data bus 1, respectively, only when the output of gate 3G is a logic signal "1".
Output to 0. FIG. 3 is a circuit diagram showing details of a part of the processor common control unit 5 in the embodiment shown in FIG.
AND circuits 5C, 5D, 5E and gate 5F
, an error status register 5G, and a clock generation circuit 5H.

Now, when the two processors 1 and 2 do not detect any abnormality, the signals on the abnormality detection lines 14 and 24 are logic "0", and the signal on the abnormality report line 20 is logic "0". There is. When processor 1 or 2 wants to send data,
A logic signal "1" is output to the data transmission instruction line 15 or 25, respectively.

In response, the selection circuit 3H outputs the data on the transmission data line 11 or 21 onto the data bus 10 via the driver 3C. data bus 1
The data output on the processor 0 is sent to the host via the receiver 4D or receiver 3D, the reception data line 22 or 12, and the other processor 2 or 1, or the processor common control unit 5 and the data line 50. and a processor (not shown).

A control signal (not shown) is input to the receiver 3D or 4D, and in response to this control signal, it can receive data from another processor or a host processor. Further, data transmission from the processors 1 and 2 and the host processor is controlled so as not to be performed at the same time.

When an arbitrary processor, for example processor 1, detects an abnormality in processor 1, abnormality detection line 1
A logic signal "1" is output to the terminal 4. In response, the driver 3B sends a logic signal "1" to the abnormality report line 20.
Output to. This logic signal is input to the selection circuit 3H via the receiver 3A and the gate 3E, and the abnormal state data on the abnormal state data line 13 is sent to the error status register 5G of the processor common control section 5 via the data bus 10. supply to.

When the gate 5F detects that the error status register 5G is all "0", that is, the previous abnormal state data has been cleared, the above-mentioned abnormal state on the data bus 10 is detected by the clock from the clock generation circuit 5H. Data is set in error status register 5G.
The set abnormal state data is the error data line 6.
0 to an external display device or magnetic disk device, and then the error status register 5G is reset.

The negative signal of the logic signal "1" on the abnormality report line 20 obtained from the negative terminal of the receiver 5A is input to the AND circuits 5C and 5D, and the clock generated by the clock generating circuit 5H is output to the processors 1 and 2. Try not to let it happen.

On the other hand, abnormal state data on the data bus 10 is controlled so as not to be accepted by the receiver 4D.

Further, the logic signal "1" on the abnormality report line 20, which indicates abnormality detection, passes through the receiver 4A of the data transmitting/receiving circuit 4 and the gate 4E and becomes one input of the gate 4G. At this time, if the processor 2 is in a normal state, a logic signal "0" appears on the abnormality detection line 24, so that the outputs of the drivers 4B and 4C are blocked. When the data bus 2 is in an abnormal state, the outputs of the drivers 4B and 4C are not blocked, and the selection circuit 4H also selects the abnormal state data on the abnormal state data line 23. Therefore, the abnormal state data of the processor 2 is also transferred to the data bus 10. is output to. Although the abnormal state data of the processors 1 and 2 coexist on the data bus 10, the processor common control section 5 separates the data.

The effect of this embodiment is that when the processor 1 or 2 detects an abnormality in its own processor, the processor common control section 5 stops supplying clocks to the processors 1 and 2. This makes it easier to investigate the cause of detected abnormalities.

According to the present invention, instead of separately providing a data bus for sending and receiving normal data and an abnormal state data bus for transmitting abnormal state data,
By adopting the above configuration, the data bus can be used both for sending and receiving normal data and for sending abnormal state data, so the abnormal state data bus and its associated interface circuit can be removed, and the hardware can be minimized. The cause of the abnormality can be easily investigated simply by increasing the amount of clothing.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the invention, and FIGS. 2 and 3 each show partial details of the embodiment. In the figure, 1, 2...processor, 3, 4...
...data transmitting and receiving circuit, 5...processor common control unit, 10...data bus, 20...abnormality report line,
30, 40... Clock supply line, 50... Data line, 60... Error data line, 11, 21... Transmission data line, 12, 22... Reception data line, 1
3, 23... Abnormal state data line, 14, 24...
Abnormality detection line, 15, 25...data transmission instruction line,
3A, 3D, 5A, 5B...Receiver, 3B, 3
C... Driver, 3E, 3F, 3G, 5F... Gate, 5C, 5D, 5E... AND circuit, 3H...
...Selection circuit, 5G...Error status register, 5H...Clock generation circuit.

Claims (1)

[Claims] 1. Information including a plurality of processors, each of which has a function of detecting its own abnormal state and can operate in parallel, and a processor common control section that performs common control to all of the plurality of processors. In the processing device, a data bus connects the central processing unit system of the information processing device including the processor and the processor common control unit; and a data bus connecting the processors and between the processors and the processor common control unit. Further, for each of the processors, the processor that has detected an abnormality transmits the abnormality to all other processors and the processor common control section via the abnormality report line. an abnormality transmission means for transmitting its own abnormal state data to the processor common control unit via the data bus; Normal time transmission/reception means for transmitting and receiving normal data to and from the control section; and when the abnormality sending means of another processor is not detecting the abnormality but the abnormality sending means of the other processor is transmitting the abnormality, the normal time transmission/reception means of the own processor; 1. A processor control method, further comprising a suppressing means for suppressing transmission of the normal data from the processor.