JPS6217329B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a constant inspection device for a breaker trip circuit.

As shown in Fig. 1, the conventional trip circuit of a circuit breaker using an electromagnetic relay consists of a normally closed contact Sy of a check relay Y, which is activated by the closing of a check start command contact Sx, and two contacts. It consists of normally open relay contacts S ₁ and S ₂ , trip coil TC, and palette switch PS connected in series. The AND condition for the main relay contact S ₁ and the sub relay contact S ₂ is included here to prevent the circuit breaker from malfunctioning during equipment inspection. To inspect the operation of the relay and trip circuit in this configuration, first operate the inspection start command contact Sx, open the short circuit with the inspection relay contact Sy, and then inspect the relay contacts S ₁ and S ₂ . It is customary.

Regarding the inspection method of the trip circuit using the contact sequence of such an electromagnetic relay, there is a drawback that a constant inspection method is difficult due to the life of the contacts, and the time required for inspection is long.

The present invention eliminates the above drawbacks, and by employing a semiconductor switch, constant inspection is possible, and when the semiconductor switch fails, the inspection signal is locked and a failure alarm is issued. The purpose of the present invention is to provide a device for constantly checking a device trip circuit.

The basic operating principle of the present invention is that a GTO thyristor, for example, is used as a semiconductor switch, and the voltage change between the anode and cathode of the GTO thyristor is applied when positive and negative pulses are applied to the gate to turn on and off the GTO thyristor. This voltage must be converted to TTL level and processed, positive,
Negative gate pulses and input signals from other GTO thyristors must never overlap, the input pulse for inspection must be a narrow pulse on the μsec order, and when multiple GTO thyristors are conducting at the same time, the protective relay must operate. For non-trip signals, the GTO thyristor must be cut off before the trip coil operates, and when a trip signal is input due to the operation of a protective relay during inspection, a wide pulse on the order of milliseconds is applied to prevent overlapping of pulses. generation and ensure that multiple GTO thyristors are conductive at the same time.
The on-current of the thyristor is set with a circuit constant such that the trip coil does not operate, and can be reduced to zero by a negative gate pulse.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a logic sequence diagram of the method of the present invention. Trip circuit 1 includes two gate turn-off thyristor elements GTO ₁ in a series circuit of a trip coil TC and a normally closed palette switch PS.
GTO ₂ are connected in series, and voltage dividing resistors R ₁ and R ₂ are connected in parallel to elements GTO ₁ and GTO ₂ , respectively.
The circuit constant of the trip circuit 1 is, for example, the electric wire P-
The voltage between N is DC100V, and the voltage dividing resistors _R1 and _R2 are each 20V.
Ω, and the trip coil TC is assumed to operate at 5 A (internal resistance 20 Ω), then elements GTO ₁ and GTO ₂ are rated to match that. When two elements GTO ₁ and GTO ₂ are both disconnected,
A shared voltage of about 30V is applied to the resistors R ₁ and R ₂ and the trip coil TC, respectively, and the current is about 1.7A and P →
The flow follows the route R ₁ → R ₂ → TC → PS → N. When only element GTO ₁ is conducting, 50V is applied to element GTO ₂ ,
50V is distributed to trip coil TC, current is 2.5A
It flows on the route P → GTO ₁ → R ₂ → TC → PS → N. When only element GTO ₂ is conducting, it is connected to element GTO ₁ .
50V is applied to the trip coil TC, and a current of 2.5A flows through the route P → R ₁ → GTO ₂ → TC → PS → N. Also, when the two elements GTO ₁ and GTO ₂ conduct at the same time, 100V DC is applied directly to the trip coil TC, and a current of 5A flows from P→GTO ₁ →GTO ₂ →TC→
It flows on the route of PS→N. At this time, the element GTO ₁ ,
If the gate signal of GTO ₂ is a trip signal from a protection relay, the trip coil TC will be excited in several tens of milliseconds and the palette switch PS will be tripped and opened, but if it is other than that, the trip coil TC will be activated before the trip coil TC starts up. Elements GTO ₁ , GTO ₂
This is something that can lead to breakage or breakage.

The elements GTO ₁ of such a trip circuit 1,
A logic sequence is configured to control GTO ₂ . 2 is a clock generator that generates clock pulses as shown in FIG. 3; 3 is a signal generator that generates four temporally different inspection pulses Q ₁ , ₁ , Q ₂ , ₂ based on the clock pulses; 4 ~7 is an AND circuit from which four inspection pulses are derived as one input, and 8 and 9 are trip signals generated by protection relay operation as one input of each.
An OR circuit 10 and 11 is a GTO drive circuit, to which Ry1 and Ry2 are guided and check pulses from AND circuits 4 and 6 are introduced as the other input. At the gate of element GTO ₁ of trip circuit 1,
The output of the OR circuit 8 is guided through the positive pulse gate circuit 12 of the GTO drive circuit 10, and the output of the AND circuit 5 is guided through the negative pulse gate circuit ₁₃ .
The output of the OR circuit 9 is led through the positive pulse gate circuit 14 of the GTO drive circuit 11, and the output of the AND circuit 7 is led through the negative pulse gate circuit 15, respectively.

16 and 17 are GTO failure determination circuits. G.T.O.
The failure determination circuit 16 is a voltage dividing resistor of the trip circuit 1.
The partial pressure V ₁ taken out from R ₁ is set to “1” or “0”.
TTL circuit 18 converting to TTL level voltage V ₁
and the positive pulse gate circuit 1 of the GTO drive circuit 10
TTL circuit 20 which is guided by inputting the output Q′ ₁ of 2
and the negative pulse gate circuit 1 of the GTO drive circuit 10
3's output ' ₁ is input to the sign inverting circuit 22, and the output of the sign inverting circuit 22 is guided.
A TTL circuit 24, an AND circuit 26 from which the outputs of the TTL circuits 18 and 20 are guided, and one input
It consists of an AND circuit 28 to which the output of the TTL circuit 18 is guided through a NOT circuit 30 and the output of the TTL circuit 24 as the other input, and an OR circuit 32 to which the outputs of the AND circuits 26 and 28 are guided. The GTO failure determination circuit 17 has the same configuration as above, including TTL circuits 19 and 21, a sign inversion circuit 23,
It consists of a TTL circuit 25, AND circuits 27 and 29, a NOT circuit 31, and an OR circuit 32. The divided voltage V ₂ of the voltage dividing resistor R ₂ of the trip circuit 1 is the TTL circuit 19.
The output _Q'2 of the positive pulse gate circuit 14 of the GTO drive circuit 11 is guided to the TTL circuit 21, and the output ' ₂ of the negative pulse gate circuit 15 is guided to the sign inversion circuit 23. .

The outputs of the OR circuits 32 and 33 of the GTO failure determination circuits 16 and 17 are led to an OR circuit 34. The output of the OR circuit 34 is passed through the NOT circuit 35.
It is led as one input to the AND circuit 36 and also to the GTO abnormality alarm device. 37 is a relay operation determination circuit, which includes an AND circuit 38 to which trip signals Ry1 and Ry2 due to protection relay operation are guided, a NOT circuit 39 on its output side,
NOT circuits 40 and 41 to which the output voltages V ₁ and V ₂ of the TTL circuits 18 and 19 are respectively guided, an AND circuit 42 on the output side thereof, a NOT circuit 43, and an AND circuit 44 to which the outputs of the NOT circuits 39 and 43 are guided. It is composed of The output of the AND circuit 44 is
It is led to the AND circuit 36 as the other input.
The output of the AND circuit 36 is led to the AND circuits 4 to 7 as the other inputs, respectively.

Here, the regular inspection operation of the trip circuit 1 begins with inspection of the element GTO ₁ . When the signal Q ₁ =1 is generated from the signal generator 3, the positive pulse gate of the GTO drive circuit 10 From circuit 12, shown in FIG.
A positive pulse of Q' ₁ = 1 (takes a certain value I _M )
Given to the gate of GTO ₁ . If element GTO ₁ is normal, it is conductive and the voltage between the anode and cathode starts from 30V.
Changes to 0V. That is, at this time, the partial pressure V ₁ is
The voltage V ₁ converted to the TTL level changes from V ₁ =1 to V ₁ =0 as shown in FIG. Even if the positive pulse Q' ₁ entering the gate of element GTO ₁ becomes 0 due to the second clock pulse, element GTO ₁ continues to maintain the same state once it has become conductive, and even if Q' ₁ = 0, At this time, V ₁ =0.

If V ₁ = 1 at this time, even though a positive pulse is applied to the gate, the element GTO ₁
Since there was no conduction, the GTO failure determination circuit 16 operates and determines that the element GTO ₁ has an open failure. Alternatively, if element GTO ₁ is turned off even though it has been ignited once, but before the next check signal (negative gate pulse) is applied, the voltage V ₁ will be reduced as shown in Figure 4C. 1 → 0 → 1 (continued from now on)
Therefore, it is determined that an open failure has occurred. In such a case, the AND circuit 26 of the GTO failure determination circuit 16
Since the output of the OR circuit 32 becomes 1, the output of the OR circuit 34 becomes 1, which sends a signal to the GTO abnormality alarm device, and also sends a signal to the NOT circuit 3.
5, one input of the AND circuit 36 is set to 0, and the other inputs of the AND circuits 4 to 7 are set to 0. As a result, a lock signal is sent to the gate circuits 12 to 15 of the GTO drive circuits 10 and 11, blocking the output of all inspection pulses and stopping the inspection.

When the element GTO ₁ is given a positive gate pulse and becomes normally conductive, the output of the GTO failure determination circuit 16 is 0, and both inputs of the AND circuit 36 are 1, and the inspection is continued. Next, the signal from signal generator 3
₁ =+1, the negative pulse gate circuit 13 of the GTO drive circuit 10 generates a negative gate pulse' ₁ =-
1 (=−Im value) is given. element
If GTO ₁ is normal, the output V ₁ of the TTL circuit 18 is V ₁
= changes from 0 to 1 and transitions from conduction to disconnection.

If V ₁ = 0 at this time, the element GTO ₁ continues to be conductive even though the negative gate pulse ' ₁ = -1 is applied, so the GTO failure determination circuit 16, it is determined that there is a short circuit failure. Furthermore, if element GTO ₁ becomes conductive again even though it was temporarily disconnected, the voltage V ₁ changes from 0 to 1 to 0 (continuing thereafter) as shown in Figure 5C, and it is similarly determined that it is a short circuit failure. be done. In such a case, the output of the AND circuit 28 of the GTO failure determination circuit 16 becomes 1, and the output of the OR circuit 32 becomes 1.
Therefore, as in the case of an open failure, a signal is sent to the GTO abnormality alarm device, and NOT circuit 3 is
5, one input of the AND circuit 36 is set to 0, and a lock signal is sent to the gate circuits 12-15.

The above is based on the assumption that element GTO ₂ is normal, but if element GTO ₁ is conductive due to inspection and element GTO ₂ is also conductive,
This is the trip signal Ry due to protection relay operation.
1. Under conditions other than _Ry2 , the 6th
As shown in Figures E, F, and G, the healthy element GTO ₁ is immediately cut off by the gate pulse.

If there is no abnormality in element GTO ₁ in the inspection up to this point, then inspect element GTO ₂ . In other words, Q ₂ and ' ₂ are sequentially generated from the signal generator 3, and the elements
Pulses of Q' ₂ =1 and ' ₂ =-1 are sequentially applied to the gate of GTO ₂ , and inspection is performed in exactly the same manner as described above.

In this way, element GTO ₁ is inspected by applying a positive gate pulse → without both gate pulses (inspect for open failure using these two methods) → applying negative gate pulse → without both gate pulses (inspecting for short circuit failure using the latter two methods) )
If there is no abnormality, then the element is
The inspection of GTO ₂ was carried out in a similar sequence, →
By repeating →→→..., the inspection is automatically continued at all times by making sure that there are no simultaneous inspection inputs. When the inspection is being performed normally, the output of the OR circuit 34 is always 0.

If trip signals Ry1 and Ry2 due to protection relay operation are received during regular inspection, these trip signals Ry1 and Ry2 have a narrow width of μsec order for inspection, as shown in Figure 7 H and I. Since it is not a pulse but a wide positive pulse on the order of milliseconds, there is sufficient overlap between the pulses. Two elements are activated by trip signals Ry1 and Ry2.
Ensures that GTO ₁ and GTO ₂ conduct at the same time. element
When GTO ₁ and GTO ₂ become conductive at the rising edge of the μsec order, the trip coil TC starts energizing, and several
Palette switch PS is tripped after 10msec.
At this time, the check signal is unnecessary, and the relay operation determination circuit 37 is immediately activated on the condition that the elements GTO ₁ and GTO ₂ are made conductive by the trip signals Ry1 and Ry2.
The output from the AND circuit 44 becomes 0, and a check lock is performed.

FIG. 8 shows a simplified configuration diagram of the above embodiment system. A positive pulse input signal from the signal input/output circuit 51 to the trip circuit 1 is sent via the signal cable 52 to one element of the plurality of trip circuits 1 provided in series through the gate circuit 54 of the GTO drive circuit 53.
Send to GTO gate. When this element GTO is in a disconnected state, a voltage is present across the voltage dividing resistor R, and the element
The element GTO is activated by inputting a positive pulse to the gate of GTO.
When conductive, the voltage across the voltage dividing resistor R becomes zero. This voltage is led to the GTO failure determination circuit 55, where it is determined whether there is a failure or not, and then returned to the signal input/output circuit 51 via the signal cable 52. By sequentially monitoring the input and output signals of a plurality of GTO thyristors, it is constantly checked whether each element of the trip circuit 1 is normal.

Figure 9 shows how the method of the present invention can be applied in place of the electromagnetic relay contact in the trip circuit shown in Figure 1.
An electrical circuit diagram of a trip circuit constructed using GTO thyristors is shown. 3 elements GTO _Y ,
GTO ₁ and GTO ₂ are the relay contacts S _Y shown in Figure 1,
Instead of S ₁ and S ₂ , it is connected in series to the trip coil TC and palette switch PS circuit. Further, voltage dividing resistors R _Y , R ₁ , and R ₂ are connected in parallel to each of the elements GTO _Y , GTO ₁ , and GTO ₂ . element
Trip signals RyY, _Ry1 , and Ry2 are guided to the gates of GTO _Y , GTO 1, and GTO ₂ , respectively, by protection relay operations. In this case, a logic sequence circuit is configured to gate control the three elements GTOy, GTO ₁ , and GTO ₂ using trip signals and check signals.

The method of the present invention enables comprehensive constant inspection of the GTO thyristor in the trip circuit 1, including short-circuit failures and open failures, as well as trip circuit disconnections, GTO drive circuit abnormalities, and signal cable disconnections.

As mentioned above, according to the constant inspection method of the disconnector trip circuit according to the present invention, a plurality of semiconductor switches are inserted in series in the trip circuit, and each semiconductor switch is inputted sequentially without being simultaneously input. Since the check signal is repeatedly given, the operation of the trip circuit can be constantly checked, and in the event of a failure, the check signal is locked and the alarm device can immediately issue a failure warning.

[Brief explanation of the drawing]

Fig. 1 is an electric circuit diagram of an example of a conventional trip circuit using electromagnetic relay contacts, Fig. 2 is a logic sequence diagram of an embodiment of the method of the present invention, and Fig. 3 is an electrical circuit diagram of an example of a conventional trip circuit using electromagnetic relay contacts. Time chart during GTO normal inspection operation, Figure 4 is time chart when open failure of element GTO ₁ , Figure 5 is time chart when short circuit failure of element GTO ₁ , Figure 6 is simultaneous conduction of two GTO thyristors. Fig. 7 is a time chart when the protection relay operates and a trip signal is applied during regular inspection, Fig. 8 is a simplified configuration diagram of the embodiment shown in Fig. 2, Fig. 9 is the first
Instead of the electromagnetic relay contacts in the trip circuit shown in the figure.
FIG. 2 is an electrical circuit diagram of a trip circuit configured using a GTO thyristor. 1...Trip circuit, 2...Clock generator,
3... Signal generator, 10, 11... GTO drive circuit, 12, 14... Positive pulse gate circuit, 13,
15... Negative pulse gate circuit, 16, 17...
GTO failure determination circuit, 37... Relay operation judgment circuit, 51... Signal input/output circuit, 52... Signal cable, 53... GTO drive circuit, 54... Gate circuit, TC... Trip coil, PS... Palette switch, GTO, GTO ₁ , GTO ₂ , GTOy... Gate turn-off thyristor, R, R ₁ , R ₂ , Ry...
...Divider resistance, Ry1, Ry2...Trip signal due to protection relay operation, Q,,Q','...Inspection signal.

Claims (1)

[Claims] 1 Connect multiple semiconductor switches in full series to the trip coil of the breaker trip circuit, connect a voltage dividing resistor in parallel to each semiconductor switch, and when there is no trip signal, the trip coil is activated from the check signal generator. A drive circuit is provided for supplying a check signal that does not lead to operation to the semiconductor switch, and a check signal output circuit is provided between the drive circuit and the check signal generator to prevent the check signal from being input to a plurality of semiconductor switches at the same time. The divided voltage value of the voltage dividing resistor and the output signal of the drive circuit are input, and when the conditions of both inputs are satisfied, the semiconductor switch determines that there is a failure and sends out a failure alarm output, and also outputs a failure alarm from the inspection signal output circuit. 1. A constant inspection device for a breaker trip circuit, characterized by being provided with a failure determination circuit that sends out a signal such that no inspection signal is output.