JPS6217376B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a testing method, and particularly to a method for simultaneously testing a plurality of semiconductor integrated circuits in parallel, which requires a long testing time.

In recent years, as a means of measuring semiconductor integrated circuits (hereinafter referred to as ICs), which require particularly long test times, multiple wafer probers or automatic handling equipment are connected to inspection equipment (hereinafter referred to as testers) to test multiple ICs. Parallel testing methods are used to run tests in parallel and improve the throughput, but the effect is
Since it is greatly affected by the inspection yield, it does not necessarily mean that it is constantly increasing. However, in recent years, while the degree of integration of ICs has improved year by year, test times have become longer in proportion to or at an even greater rate.
The ratio of testing costs to the total cost of ICs continues to increase, and there is a strong desire to improve the throughput of testing systems, including testers. As a means of achieving this, it is not necessary to test multiple ICs in parallel at the same time.

The parallel test method is most effective when multiple ICs under test (hereinafter referred to as DUTs) measured at the same time are of good quality.
The greater the number of combinations of non-defective products and defective products that become defective in a short test time, the less effective the test will be. However, in the conventional parallel testing method, multiple DUTs are randomly combined, so it is unclear whether good DUTs will be combined or not, and the effectiveness is not always maximized. Ta.

The present invention aims to provide an efficient parallel testing method that solves the above-mentioned problems.

According to the test method of the present invention, a plurality of ICs under test
a first test means for performing a preliminary test in parallel; and a first test means for conducting a preliminary test in parallel;
For ICs, continuing tests will be temporarily suspended,
At this point, the test is completed only for the IC under test that has been judged as "fail", and the measurement section continues to perform the same preliminary test as above until the IC under test is tentatively judged as "good". a second test means for testing the ICs under test while changing them sequentially; and a second test means for testing the ICs under test while sequentially changing them, and testing the plurality of ICs that have been provisionally determined to be "good" obtained from the first and second test means again in parallel after the preliminary test. This test method is characterized by comprising a third test means for executing the test and obtaining a final pass/fail judgment.

Hereinafter, the parallel testing method according to the present invention will be explained in detail with reference to the drawings. FIG. 1 is a wafer map showing the good and bad chips of two semiconductor wafers, with ○ marks indicating good chips and x marks indicating defective chips. For convenience of explanation, it is assumed that the defective chips marked with an "X" are found by the first test means (preliminary test) of the parallel test method according to the present invention. Furthermore, FIG. 2 is a timing chart of the test order seen from time detection when two wafers as shown in FIG. 1 are tested using the conventional parallel testing method, and FIG. This is a timing chart when the wafer shown in the figure is tested using the parallel testing method according to the present invention.

When chips 2a and 2b on two wafers 1a and 1b are simultaneously tested in parallel as shown in FIG. The chips that form a pair between the wafer 1a and the wafer 1b are the chip and the second chip of the wafer 1b, the third chip of the wafer 1a and the third chip of the wafer 1b, the 16th chip of the wafer 1a and the 16th chip of the wafer 1b. It was constant, and it depended on chance whether good chips would work together or not.

Therefore, when wafers having good and bad chips as shown in FIG. 1 are tested in parallel using the conventional method, when testing the sixth chip of each wafer as shown in FIG. , since it is a good chip, the effect of parallel measurement appears, but
For example, in the second, seventh, and eighth chips of each wafer, good chips and defective chips are combined, and the measurement time required for the defective chips is included in the measurement time for the good chips. This will reduce the time required for the exam, but
In particular, defects in wafer testing are discovered through tests that take a relatively short time compared to the total test time, such as short failure tests, DC parametric tests, and basic function tests. Since the ratio is high, as mentioned above, the effect of parallel testing on combinations of good chips and defective chips can hardly be expected.

Therefore, the present invention pays special attention to the above-described problems and intentionally combines chips that are considered to be of good quality.

In the parallel test method of the present invention, the test content of the IC under test is divided into two parts, such as a preliminary test and a main test. It consists of basic test items such as , and other test items that have a relatively high failure detection rate to account for failures in AC tests and margin margin tests, and these test items are short compared to the total test time. The test will be short. The test execution procedure is to first perform the preliminary test on the first chip of wafer 1a and the first chip of wafer 1b in parallel, and if both chips are judged to be "good" as a result, then continue the main test in parallel. However, when the preliminary test results are divided into "pass" and "fail", the test is temporarily interrupted for the chips on the "pass" side, and the test ends at this point only for the chips that are "fail". Then move the target chip to the next one and run the preliminary test again. In the case of wafers as shown in FIG. 1, the first chips of wafers 1a and 1b are pretested in parallel, but since both chips are "defective", the next second chip is pretested in parallel. Here, wafer 1a is "defective" and wafer 1
Since chip b is "good", the test for the second chip of wafer 1b is temporarily interrupted, and the test for the second chip of wafer 1b is
Transfer the test chip a to the third chip, perform a preliminary test on this chip alone, and since that chip is also "defective", perform a preliminary test on the fourth chip, and then sequentially use wafer 1a to perform a preliminary test. Execute until. If the 6th chip passes the preliminary test, the 2nd chip of wafer 1b, which was previously suspended,
The main test is performed on the chip and the sixth chip of the wafer 1a in parallel, and the result of the main test becomes the final judgment result for both chips. Thereafter, the chips of both wafers are transferred to the next one and tests are carried out in the manner described above from the preliminary test.

The above execution order is shown in a timing chart in FIG. 3. As can be seen by comparing the timing chart of the conventional parallel test method shown in FIG. 2 with the timing chart of FIG. The effect of parallel testing is clearly improved compared to the conventional method because the test is performed in combination with good chips from the other wafer, and the shorter the preliminary test time, the greater the effect.

[Brief explanation of the drawing]

Fig. 1 is a wafer map, Fig. 2 is a timing chart of the chip execution order seen from time detection using the conventional parallel testing method, and Fig. 3 is a timing chart similar to Fig. 2 of the parallel testing method according to the present invention. be. In the figure, 1a, 1b...wafer,
2a, 2b... chips to be measured.

Claims (1)

[Claims] 1. In a method for testing multiple semiconductor wafers in parallel, each having multiple chips,
A plurality of semiconductor wafers are tested in parallel in the test, and the subsequent second test is temporarily interrupted for chips that are determined to be "good" in the first test,
The first test was continued only for the semiconductor wafers that were determined to be "fail" until chips that were determined to be "good" were obtained, and all semiconductor wafers had chips that were determined to be "good". At the same time, a second test is performed on those devices under test, and the first test is a test that has a relatively high defect detection rate and results can be obtained in a short time. A test method characterized by conducting another main test as a test for.