JPS6217408B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention uses a random access memory to store received signals while updating them sequentially, and is configured to be able to sequentially and repeatedly reproduce the stored signals when necessary. The present invention relates to a radio receiver and aims to provide a simple configuration that allows the start and end of a reproduced signal to be clearly identified.

Generally, when a radio receiver is used to receive a broadcast program such as a quiz, it may be of no use if a part of it is missed. For example, in broadcast programs such as quizzes, etc., the address of the destination is usually broadcast repeatedly several times, but if the tone is too fast, it is impossible to write down the information, and there is a problem that the user cannot answer the quiz etc.

Therefore, the present inventor first used a random access memory to store the received signals while updating them sequentially, and constructed the system so that the stored signals can be sequentially and repeatedly reproduced when necessary. Invented the radio receiver. however,
In this type of radio receiver, which was previously invented by the present inventor, the signals stored in the random access memory are sequentially and repeatedly reproduced, so there is no interval between the end and the beginning of the reproduced signal. The problem was that it felt extremely unnatural at the moment.

The present invention eliminates the above-mentioned conventional drawbacks, and when a signal stored in a random access memory is read and reproduced, there is no need for blank spaces or delimiters such as warning sounds between the end and start of the signal. The structure is such that sections are provided so that the above-mentioned unnaturalness is not felt.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The radio receiver of the present invention will be described below with reference to the drawings of one embodiment. In the figure, 1 is a radio receiving circuit, 2 is an amplifier circuit, 3 is an analog-to-digital conversion circuit, 4 is a digital-to-analog conversion circuit, 5 is a random access memory, and 6 is an address signal for the random access memory 5. 7 is a clock pulse generation circuit, 8 is a microcomputer, 9 is an analog switch circuit, and 10 is a warning signal generation circuit.

Note that SW ₁ , SW ₂ , and SW ₃ are switches for switching between storage and readout that are linked to each other, and the microcomputer 8 operates according to the state of the address signal from the switch SW ₃ and the counter 6 as shown in FIG. It is programmed to perform actions according to a chart. That is, in FIG. 2, flow 11
Then, the input Sin from the switch SW ₃ is detected, and it is determined whether the switch SW ₃ is connected to the memory side terminal n or the read side terminal r. If switch SW ₃ is connected to memory side terminal n, output that holds analog switch circuit 9 at a side terminal
Sout is output, and if it is input to the read-side terminal r, the process moves to flow 12, at which point the address signal Ain from the counter 6 is input, this is stored as Ao, and the process moves to flow 13. And flow 13
At , an output Sout for switching the analog switch circuit 9 from the a-side terminal to the b-side terminal is output, and the process moves to flow 14. In flow 14, a timer starts counting in order to detect the passage of a certain period of time.
Then, in flow 15, check the position of switch SW ₃ , and if it is connected to memory side terminal n, flow 21
Then, the analog switch circuit 9 is turned on to the a side terminal and acts to return to the original flow 11, and if it is turned on to the read side terminal r, flow 1 is applied.
6, it is determined whether a certain period of time has elapsed after the timer started counting. If the predetermined time has not elapsed, the process returns to flow 15, and if the predetermined time has elapsed, the process proceeds to flow 17, where an output Sout for switching the analog switch circuit 9 from the b-side terminal to the a-side terminal is generated. Thereafter, the process goes to flow 18, where time is taken to advance one address from the address signal Ao stored in flow 12, and then the process goes to flow 19. flow 19
Now, the address signal from counter 6 at that point
Ain is input and compared with the address signal Ao stored in flow 12. When moving from flow 18 to flow 19, Ain = Ao + 1, so it always moves to flow 20, and if switch SW ₃ remains connected to the read-side terminal r, it returns to flow 19, and if the switch SW 3 remains connected to the storage-side terminal n. If so, flow 11
Return to That is, if the switch _SW3 remains connected to the read-side terminal r, the loop of flows 19 and 20 is repeated. Then, when the address goes around and returns to the original Ao, this is detected in flow 19, and the process returns to flow 13.

In the above embodiment, the changeover switch SW ₁ ,
Assume that SW ₂ and SW ₃ are respectively connected to the storage terminal n side. In this case, since the signal received by the radio receiving circuit 1 is applied to the amplifier circuit 2 via the switch SW ₁ , it is applied to the speaker connected after the amplifier circuit 2, as in a normal radio receiver. Therefore, the desired broadcast can be listened to.
In this case, since switch SW ₃ is connected to memory side terminal n, microcomputer 8
Therefore, the output Sout for holding the analog switch circuit 9 at the a-side terminal is output, and the analog switch circuit 9 remains connected to the a-side terminal. Therefore, the clock pulse from the clock pulse generation circuit 7 is applied to the counter 6, and is also applied to the analog-to-digital conversion circuit ₃ and the random access memory 5 via the switch SW2. Therefore, these counters 6, analog-to-digital conversion circuit 3,
Both random access memories 5 become operational, and the signal received by the radio reception circuit 1 is converted into a digital signal by the analog-to-digital conversion circuit 3.
The data will be stored while being updated sequentially.

Now, assume that switches SW ₁ , SW ₂ , and SW ₃ are turned on to the read-side terminal r. In this case, the output side of the radio receiving circuit 1 and the input side of the amplifier circuit 2 are switched.
The input side of the amplifier circuit 2 is connected to the output terminal Aout of the digital-to-analog converter circuit 4 via the switch SW ₁ , and the analog switch circuit 9 is separated from each other by SW _1.
It will be connected to the b terminal of. Then, the microcomputer 8 first detects in flow 11 that the switch SW ₃ is turned on to the read-side terminal r. Therefore, the process moves from flow 11 to flow 12, where the address signal Ain from the counter 6 is detected and stored as Ao. Thereafter, the process moves to flow 13 and the analog switch circuit 9 is switched from the terminal a side to the terminal b side. When the analog switch circuit 9 is switched from the terminal a side to the terminal b side, the clock pulse from the clock pulse generation circuit 7 is no longer applied to the counter 6.
Counter 6 stops counting, and the address signal to random access memory 5 no longer changes. In this state, the output of the warning signal generation circuit 10 is output to the analog switch circuit 9 and the switch.
The signal is applied to the amplifier circuit 2 via SW ₁ , and a warning sound is generated from a speaker connected to the output side of the amplifier circuit 2. Then, the microcomputer 8 further performs flow 13 to flow 1.
Moving on to step 4, the timer starts measuring time. After starting the timer, the microcomputer 8
immediately moves to flow 15, and at this point the switch
Check the status of SW ₃ . If the switch SW ₃ is already connected to the memory side terminal n, the process moves to flow 21 and the analog switch circuit 9 is connected from the terminal b side to the terminal a side, but if the switch SW ₃ is still connected to the read side terminal r. If so, the timer continues to measure time and moves to flow 16. and flow 1
If the certain period of time has not elapsed in step 6, the process returns to flow 15 and the same operation is repeated. If a certain period of time has elapsed, the process moves to flow 17 and the analog switch circuit 9 is switched from the terminal b side to the terminal a side. When the analog switch circuit 9 is switched from the terminal b side to the terminal a side, the clock pulse from the clock pulse generation circuit 7 is applied to the counter 6 via the analog switch circuit 9, and the address to the random access memory 5 is changed. The signals will be switched sequentially. In this case, since the switch SW ₂ is connected to the terminal r side, the clock pulse from the clock pulse generation circuit 7 is simultaneously applied to the digital-to-analog conversion circuit 4. Therefore, from this point on, the random access The signal stored in the memory 5 is read out, converted into the original analog signal by the digital-to-analog conversion circuit 4, and applied to the amplifier circuit ₂ via the switch SW1. At the same time, the output from the warning signal generating circuit 10 is no longer applied to the amplifier circuit 2 because the analog switch circuit 9 is switched from the terminal b side to the terminal a side. That is, at this point, the warning stops, and the signal stored in the random access memory 5 is read out, converted into an analog signal, and applied to the amplifier circuit 2. Thereafter, the microcomputer 8 moves to flow 18, where it takes time to advance one address from the address signal Ao stored in flow 12, and moves to flow 19. In flow 19, the address signal Ain from the counter 6 at each time is inputted and compared with the address signal Ao stored in flow 12. If the address signal Ain from the counter 6 at that time is not the same as the address signal Ao stored in flow 12, flow 2
0, and the state of switch SW ₃ is checked again. If the switch _SW3 is still connected to the read-side terminal r, the process returns to flow 19 and repeats the same operation. If the switch SW ₃ is turned on to the memory side terminal n, the process returns to flow 11. If the switch _SW3 is still connected to the read-side terminal r, the loop of flows 19 and 20 is repeated, so that the address signal Ain from the counter 6 always matches the address signal Ao stored in flow 12 during that time. That is, since the address signal Ain from the counter 6 changes repeatedly in sequence, it always matches the address signal Ao stored in flow 12 after one cycle. When the two match, the microcomputer 8 returns to flow 13 and switches the analog switch circuit from the terminal a side to the terminal b side again.
Repeat the operations described above. That is, according to the above embodiment, if the switches SW ₁ , SW ₂ , and SW ₃ are connected to the memory side terminal n, the output from the radio receiving circuit 1 is directly applied to the amplifier circuit 2 in this state, and the normal radio It can be used as a receiver, and at the same time, the output from the radio receiving circuit 1 can be converted into a digital signal and stored in the random access memory 5 while being updated repeatedly. When switches SW ₁ , SW ₂ , and SW ₃ are connected to read terminal r, a warning sound is first emitted for a certain period of time, and then the random access memory 5
The signals stored in the memory can be sequentially read and reproduced. If the switches SW ₁ , SW ₂ , and SW ₃ are still connected to the read terminal r, a warning sound is emitted for a certain period of time, and the signals stored in the random access memory 5 can be read out repeatedly. can.

In the embodiment, random access memory 5
When reading out a signal stored in a signal, a warning sound is emitted between the end and start of the signal, but instead of the warning sound, a silent section or other delimiter may be provided. good.

As is clear from the above embodiments, the radio receiver of the present invention uses a random access memory, and is configured to repeatedly store the signals received by the radio receiving circuit while sequentially updating them. When reading a signal stored in memory, a warning sound, a silent section, or other delimiter is inserted between the end and start of the signal. When reading, a delimiter section is formed between the end and start of the signal, so even when the signal as a whole is repeatedly reproduced, the end of the signal,
Even if there is a large change in tone between the beginning and end, it does not feel unnatural, which is extremely advantageous in practice.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of one embodiment of the radio receiver of the present invention, and FIG. 2 is a flowchart of a microcomputer used in the receiver. 1...Radio reception circuit, 2...Amplification circuit, 3...
...Analog-digital conversion circuit, 4...Digital-analog conversion circuit, 5...Random access memory, 6...Counter, 7...Clock pulse generation circuit, 8...Microcomputer,
9...Analog switch circuit, 10...Warning signal generation circuit, _SW1 , _SW2 , _SW3 ...Memory/readout switching switch.

Claims (1)

[Claims] 1 A random access memory is used, and the memory is configured to store the signals received by the radio receiving circuit while being sequentially and repeatedly updated, and the memory is configured such that the memory has a constant value between the end and the beginning of the signals stored in the memory. 1. A radio receiver characterized in that the signals stored in the memory can be arbitrarily repeatedly read out and played back in sequence by providing dividing sections.