JPS6217434B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention aims to provide a device capable of displaying an image with inconspicuous scanning lines even when the image is displayed using a television signal of the current standard system or a system similar thereto. The currently used NTSC television standard specifies the number of horizontal scanning lines as 525.
Conventional television receivers are limited to the number of scanning lines when receiving this signal, so they have had the disadvantage that as the screen size increases, the roughness of the scanning lines becomes more noticeable. There are also plans to improve the vertical resolution by increasing the number of scanning lines, but these would change the standard system itself, and there is no compatibility with the current television standard system. It's something that doesn't exist.

Therefore, the present invention provides a television receiver that can increase the number of scanning lines and display images in which the number of scanning lines is inconspicuous even under the current standard system or a system similar thereto (simplified system, etc.). The purpose is to Therefore, in the present invention, the time axis of the received video signal is compressed to 1/n (n is an integer of 2 or more) and supplied to the cathode ray tube, and the horizontal deflection frequency of the cathode ray tube is multiplied by n. It is characterized by the fact that

Hereinafter, the present invention will be described in detail with reference to the drawings showing an embodiment in which n is 2. first,
Figure 1 shows its schematic configuration, where 1 is an antenna, 2
3 is a tuner, 3 is a VIF circuit, and 4 is a video detection circuit, which are similar to conventional ones and receive and process television signals of the current NTSC system. The time axis compression circuit 5 compresses the time axis of the received video signal to one half. At this time, the time is adjusted to the real time by repeating and outputting one horizontal period (hereinafter referred to as 1H period) twice. The video signal subjected to time axis compression in this manner is applied to the cathode ray tube 7 after amplifying the luminance signal in the video amplification circuit 6. Further, the color signal is demodulated by the chroma circuit 8 and also applied to the cathode ray tube 7. However, since the frequency of all signals is doubled due to time axis compression to one half, it is necessary to double the bandwidth of the video amplification circuit 6 and the chroma circuit 8.

On the other hand, a synchronization separation circuit 9 separates a synchronization signal from the received video signal, and based on the synchronization signal, a vertical deflection circuit 10 vertically deflects the cathode ray tube 7 at the same vertical deflection frequency (60 Hz) as in the prior art. Furthermore, the horizontal synchronization signal obtained by separation is multiplied to twice the frequency by the multiplier circuit 11, and based on this, the horizontal deflection circuit 12 uses the horizontal deflection frequency (31.5 KHz), which is twice the conventional horizontal deflection frequency (15.75 KHz). ) performs high-speed horizontal deflection of the cathode ray tube 7. In this case as well, since the horizontal deflection frequency is doubled, it goes without saying that the horizontal deflection circuit 12 and the deflection yawter must be able to operate at high speeds accordingly.

In this way, by compressing the time axis of the video signal by half and expanding the horizontal deflection frequency by twice to drive the cathode ray tube 7, the screen is
525 scan lines (solid lines) plus more in between
This means that 525 scanning lines (dashed lines) can be added, making it possible to project high-quality images with less noticeable scanning lines. Of course, in this case as well, since the two images of the solid line and the broken line are the same, the resolution in the vertical direction will not improve, but since the number of scanning lines has doubled, Since each book no longer stands out, the roughness of the screen disappears, and a high-quality, detailed image can be obtained.

Next, the main parts used in this device will be explained in more detail.

First, a specific circuit example of the time axis compression circuit 5 will be explained with reference to FIG. 3 and a waveform diagram of each part thereof in FIG. 4. In Figure 3, here we use 4 for time axis compression.
A set of charge transfer devices (CTD)
Device) 13 to 16 are used. For example, BBD or CCD can be used. and,
They are used in sets of two, and in a certain horizontal period, the received video signal is written to one set of CTDs 13 and 14, and in the following horizontal period, the CTDs 13 and 14 are
The video signal is read out continuously at twice the speed, compressed in half, and repeats 1H minutes twice, and the video signal received during this readout is sent to the CTD 15 of the other set. , 16. And furthermore, in the next horizontal period, CTD1
While continuously reading from 5 and 16 at twice the speed,
Write the received video signal to CTD13 and 14. By repeating these operations alternately, the time axis of the received video signal is compressed to half, resulting in 1H.
Create a video signal that repeats the minutes twice,
Output from gate 17.

The remaining part in Figure 3 is CTD1 as above.
This is a circuit that creates signals for controlling the operations of Nos. 3 to 16. In this part, first the horizontal pulse is applied to the flip-flop 18 and the frequency is divided in half.
Create an output that is inverted every 1H. With that output 4
Continuously connected monostable multivibrator 19~
22's first stage is triggered. The metastable time of each monostable multivibrator 19 to 22 is all set to H/2, and a pulse of H/2 width with a phase shift of H/2 is generated from each output terminal every 5H.

On the other hand, the oscillation circuit 23 creates a clock for writing and transferring to the CTDs 13 to 16 (hereinafter referred to as a write clock). Here, since the signal to be sampled and transferred is a video signal, 2
Create a write clock with a frequency equal to or higher than sc (sc is the color subcarrier frequency). This may be created by doubling or quadrupling the output of the color subcarrier oscillator, or may be created using an original oscillator. These write clocks are created as a pair of clocks with opposite phases. Further, this clock is doubled by a multiplier circuit 24 to create clocks for transfer and reading to the CTDs 13 to 16 (hereinafter referred to as read clocks). These readout clocks are also created as a pair of clocks with mutually opposite phases. Then, by gates these clocks with gates 25 to 40 using each of the above pulses, a predetermined clock is set to CTD13 to CTD13.
In addition to step 16, time axis compression of the video signal is performed.

The operation will be explained below with reference to the waveform diagram in FIG. First, a video signal such as a is applied from the video detection circuit 4 to each CTD 13 to 16.
On the other hand, in the gate 25, the write clock φ is taken out every 1H like g, for example, at an odd number H, and the CTD is
In addition to the writing sections 13 and 14, the input video signal is sampled. At the same time, the gate 26 extracts the write clock φ to the odd number H, and the gate 27
The sampled video signal is written to the transfer section by applying it to the transfer section of the CTDs 13 and 14 as h and i via 28. In the subsequent even number H, the read clock 2 is taken out at the gate 29 in the first half, and then read out through the gate 27 as in h.
In addition to the transfer section of CTD13, the read clock 2φ is taken out at the gate 30 and transferred to CTD1 as shown in j.
By adding it to the reading section 3, the written video signal is read out at twice the speed, and a video signal whose time axis is compressed to 1/2 as shown in b is read out.
Also, in the latter half of even number H, the read clock 2 is taken out at the gate 31 and sent through the gate 28 as shown in i.
In addition to the transfer section of CTD 14, the read clock 2φ is taken out at the gate 32 and the CTD is transferred as shown in k.
By adding 14 readout parts, 2 like c
Read out the video signal whose time axis has been compressed to one-fold. In this way, the video signals b and c obtained by compressing the video signal of odd number H on the time axis are read out twice in the first half and second half of the next even number H.

At the same time, in this even number H, the write clock φ is taken out at the gate 33 as shown in l, and the CTD15 and CTD16 are
In addition to the writing section, the input video signal is sampled, and the writing clock is taken out at the gate 34 and sent to the CTD as m and n through the gates 35 and 36.
By adding the sampled video signal to the transfer sections 15 and 16, the sampled video signal is written to the transfer section. Then, in the first half of odd number H, gate 37
Take out the read clock 2 and also use the gate 3.
5 to the transfer section of the CTD 15 as indicated by m, and by taking out the read clock 2φ at the gate 38 and applying it to the reading section of the CTD 15 as indicated by o, the written video signal is doubled in speed. The video signal is read out and the time axis is compressed to 1/2 as shown in d. In the latter half of the odd number H, the read clock 2 is taken out at the gate 39 and added to the transfer section of the CTD 16 as indicated by n through the gate 36, and the read clock 2φ is taken out at the gate 40 and added to the readout section of the CTD 16 as indicated at p. By adding to , a video signal whose time axis has been compressed to 1/2, such as e, is read out. In this way, even number H
The video signals d and e obtained by compressing the video signal in the time axis are read out twice in the first half and second half of the next odd number H.

Below, repeat the same operation and CTD13~1
By combining the video signals read out from the gates 6 at the gate 17, it is possible to create a video signal whose time axis is compressed to one-half as shown in FIG.

Next, FIG. 5 shows a circuit diagram of the multiplier circuit 11 for doubling the horizontal synchronizing signal, and FIG. 6 shows its waveform diagram. First, the horizontal synchronizing signal differentiating circuit 41 differentiates the horizontal synchronizing signal as shown in a obtained by the synchronizing separation circuit 10 as shown in b. In addition, the monostable multivibrator 42 with the metastable time set to H/2 is triggered by this horizontal synchronization signal a to create a rectangular wave with a width of H/2 as shown in c, which is also used in the differentiating circuit 43 as shown in d. Differentiate as follows. Then, one polarity of these differential outputs b and d is taken out through diodes 44 and 45 and combined as shown in e, and by triggering the monostable multivibrator 46 with the combined output, 2 It is possible to create a horizontal synchronization signal that is doubled.

In addition, in the above embodiment, the time axis of the video signal is compressed to 1/2, but the time axis may be compressed to an arbitrary 1/n (n is an integer of 2 or more). In that case, the horizontal deflection frequency is also n
All you have to do is multiply it by a factor of two. In that case, if CTD is used for time axis compression, 2n sets of
Using a CTD, in a certain horizontal period, the received video signal is written to n sets of CTDs, and in the following horizontal period, while reading from the n sets of CTDs one after another at n times the speed, the received video signals are written to the remaining n sets of CTDs. All you have to do is write the signal.

As detailed above, in the present invention, the time axis of the received video signal is compressed to 1/n, and the horizontal scanning frequency is multiplied by n to be displayed on the cathode ray tube. Even if a television signal based on the system is used, it is possible to display an excellent image with inconspicuous scanning lines.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a television receiver according to an embodiment of the present invention, FIG. 2 is a front view of its projection state, FIGS. 3 and 5 are specific circuit diagrams of its main parts, and FIG. The figure and FIG. 6 are waveform diagrams of each part. 5... Time axis compression circuit, 7... Cathode ray tube, 11
... Multiplier circuit, 12 ... Horizontal deflection circuit, 13,1
4, 15, 16...Charge transfer element.

Claims (1)

[Claims] 1. A time axis compressor that compresses the time axis of the received video signal to 1/n (n is an integer of 2 or more) and supplies it to the cathode ray tube, and a high speed unit that multiplies only the horizontal deflection frequency of the cathode ray tube by n times. The time axis compression means uses 2n sets of charge transfer elements such as CCDs and BBDs, writes the received video signal to the n sets of charge transfer elements in a certain horizontal period, and writes the received video signal to the n sets of charge transfer elements in a subsequent horizontal period. A television receiver characterized in that the video signals are read out one after another from the n sets of charge transfer elements at a speed n times faster, and the received video signals are written to the remaining n sets of charge transfer elements.