JPS6217758B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a signal generating circuit, and more particularly to a signal generating circuit that receives two input signals and generates an output by adding them in an analog manner. This type of signal generating circuit is applied to a multiple tone generating circuit that simultaneously generates two tones when generating alarms and melodies in electronic meters, electronic desktop calculators, and the like. In other words, in melody generation circuits such as electronic watches and electronic desktop calculators, 1
A melody is generated by controlling two musical tone signal generating circuits and applying the output of the musical tone generating circuit to a speaker or a piezoelectric vibrator. Therefore, when trying to output two tones as a melody sound at the same time, two The two musical tone generating circuits are controlled to output different frequencies. The outputs of these tone generating circuits are added together, and the analog sum output is applied to a speaker or a piezoelectric vibrator. At this time, whether it is possible to output two tones at the same time depends on whether the analog sum of the two musical tone signals can be obtained. Conventionally, a synthesis method using an analog amplifier has been used for such analog sum circuits, but electronic clocks and electronic desktop calculators are usually constructed with complementary MOS logic circuits due to their power consumption. Therefore, the analog summation circuit is also composed of complementary MOS logic circuits. An example is shown in FIG. In FIG. 1, two transistors Q ₁ and Q ₂ having substantially the same absolute value of threshold voltage and transconductance and different polarity constitute a complementary MOS inverter I ₁ , and two musical tone signal generation circuits TG ₁ ,
The outputs of TG ₂ are connected to the inputs of inverter I ₁ through resistors R ₁ and R ₂ , respectively, and the outputs O ₁ of inverter I ₁ are connected to inverter I 1 through resistors R _{3 .}
is returning to the input. The operation of such a signal generating circuit will be explained using the signal waveform diagram of each part shown in FIG. Outputs L 1 and L ₂ of musical tone signal generation circuits TG ₁ and TG ₂ as shown in FIG. ₂ a and b, respectively.
is supplied to the inverter, when the signal levels of the outputs L ₁ and L ₂ are different as in periods S ₁ and S ₂ , the gate voltage of the inverter I ₁ is equal to the voltage of the resistors R ₁ and R ₂
Therefore, both transistors Q ₁ ,
Q ₂ conducts. As a result, the output of inverter I ₁
V ₀₁ can take the voltage level of V _M1 as shown in c in the figure. As in period S ₁ , when both outputs L ₁ and L ₂ are at low level, the output becomes V _H1 , and in the opposite case, it becomes V _L1 . Therefore, the output V ₀₁ of inverter I ₁
is determined by the state of the output signal levels of the musical tone generating circuits TG ₁ and TG ₂ , that is, their analog sum is taken. Now, let V _S1 be the gate voltage at which the conductances of transistors Q ₁ and Q ₂ of inverter I ₁ are equal, and assume that the gain of inverter I ₁ is extremely large, then periods S ₁ , S ₂ , S ₃ and S ₄ , V ₀₁ = V _S1 − _{R 3} {(L ₁ − V _S1 )/R ₁ + (L ₂ − V _S1 )/R ₂ } [1], and if R ₁ = R ₂ , V ₀₁ =V _S1 −(R ₃ /R ₁ )(L ₁ +L ₂ −2V _S1 ) [2]. Further, from the threshold values and transconductance conditions of the transistors Q ₁ and Q ₂ , V _S1 ≈1/2 V _DD . Therefore, if the output in state S ₁ , the output voltage V _H1 of V ₀₁ , is calculated using equation [2], L ₁ = L ₂ = 0
Then, V _H1 =V _S1 +2(R ₃ /R ₁ )V _S1 [3]. As mentioned above, since V _S1 ≈V _DD /2, when R ₃ /R ₁ >1/2, the output O ₁ is suppressed by the power supply voltage, and V _H1 =V _DD [4]. Next, considering the S ₂ and S ₄ states, L ₁ + L ₂ is equal to V _DD , so V _M1 = V _S1 - (R ₃ / R ₁ ) (V _DD - 2 V _S1 ) [5], If V _S1 is V _DD /2, then V _M1 = V _S1 = V _DD /2 [6]. Furthermore, in the S ₃ state, when L ₁ +L ₂ is 2V _DD , V _L1 = V _S1 - (R ₃ /R ₁ ) (2V _DD - 2V _S1 ) [7], and as in S ₁ , R ₃ / When R ₄ >1/2, V _L1 =O _V [8]. In this way, in the conventional example shown in FIG. 1, the analog sum of the musical tone signals L ₁ and L ₂ is obtained as the output O ₁ . However, the intermediate output voltage level mentioned above,
A detailed study of V _M1 reveals that the conventional example shown in FIG. 1 has serious drawbacks. That is, in the above explanation, V _S ≒ V _DD /2, but since the threshold voltages and transconductances of transistors Q ₁ and Q ₂ are not necessarily equal, more precisely V _S1 = V _DD /2 + △V. _S1

[9] Should be. Therefore, the formula [5] becomes V _M1 =V _DD /2+(1+2R ₃ /R ₁ )△V _S1 [10]. This means that the intermediate output voltage level V _M1 is V _DD /
2 by (1+2R ₃ /R ₁ )·ΔV _S1 . As a result, the output voltage of the inverter _I1 , _V01 , loses its symmetry, resulting in distorted sound. In order to reduce this distortion, R ₃ /R ₁ should be made smaller than 1/2, but the above [3]
As shown in formula [7], when R ₃ /R ₁ < 1/2, the output amplitude of the output O ₁ cannot reach both ends of the power supply voltage at the maximum, and the input voltage of the inverter I ₁ This means that most of the voltages operate near V _DD /2. For this reason, the output impedance of the inverter _I1 during operation becomes quite large, making it difficult to drive speakers and the like. In this way, conventional multitone generating circuits that produce two tones simultaneously are forced to choose between distortion or sacrificing the drive ability for the load. An object of the present invention is to provide a signal generation circuit that can generate sound with less distortion without sacrificing the drive ability for a load. According to the present invention, the first logic circuit and the second logic circuit each receive both the first and second signals as inputs.
a logic circuit, first and second transistors each receiving the outputs of the first and second logic circuits, and an output terminal electrically connected to the outputs of the first and second transistors. , the first and second logic circuits are configured to generate an output that causes both the first and second transistors to conduct when the first and second signals have different levels. A signal generating circuit is obtained. Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 3 is a block diagram showing one embodiment thereof. In FIG. 3, the outputs of the musical tone generating circuits TG ₃ and TG ₄ are connected to the inputs of the NOR circuit NR and the NAND circuit NA, respectively, and the output of the NOR circuit NR is connected to the gate of the transistor Q ₃ of the P channel. To,
The outputs of the NAND circuits NA are respectively connected to the gates of N-channel transistors _Q4 . The source of transistor _Q4 is grounded and the transistor
The source of _Q3 is connected to the power supply _VDD , and the drains of each are connected in common to form the output terminal _O2 . This operation will be explained using the signal waveform diagram of each part in FIG. 4. If musical tone generation circuits TG ₃ and TG ₄ supply outputs L ₃ and L ₄ as shown in FIG. Depending on the timing, the outputs L _R and L _A as shown in a and d of the same figure are
It is supplied to Q ₃ and Q ₄ respectively. This results in
The conduction and cutoff states of the transistors Q ₃ and Q ₄ change, and four states S ₅ , S ₆ , S ₇ and S ₈ occur in the output voltage waveform V ₀₂ of the output Q ₂ . The states of S ₅ to _{S 8} will be considered, and it is assumed that transistors Q ₃ and Q ₄ have the same absolute value of threshold voltage and the same transconductance as in the conventional case. First, in the state _S5 , the transistor _Q3 is cut off and the transistor _Q4 is turned on, so that V _O2 =V _L2 =O _(V) [11]. Next, in states _S6 and _S8 , the output L _R of the NOR circuit NR is at a low level, and the NOR circuit
Since the output L _A of NA is at a high level, both transistors Q ₃ and Q ₄ are in a conductive state. Therefore, from the threshold voltage and transconductance conditions, V _O2 =V _M2 =V _DD /2 _(V) [12]. Furthermore, in state _S7 , the transistor
Since Q ₃ is in a conductive state and transistor Q ₄ is in a cut-off state, V _O2 =V _H2 =V _DD(V) [13]. In this way, even in this embodiment, the musical tone signal
The analog sum of L ₃ and L ₄ is obtained. Next, similarly to the conventional example shown in FIG. 1, the distortion of the embodiment shown in FIG. 3 will be evaluated. Similarly to the conventional example shown in FIG. 1, V _M2 in the embodiment shown in FIG. 3 also deviates from V _DD /2 due to the difference in threshold voltage and transconductance of transistors Q ₃ and Q ₄ . However, the gate bias value of both transistors Q ₃ and Q ₄ when determining V _M2 is the ground potential or power supply voltage V _DD , which is a larger value than in the conventional example shown in FIG. Assuming that the threshold voltage and transconductance variations are the same, the deviation △V _S2 of V _M2 from V _DD /2 is |△V _S2 |≦|△s ₁ | [14]. Moreover, in the conventional example, the deviation △V from V _M1
Since _S1 is weighted (H2R ₃ /R ₁ ) and input and feedback resistors are not required in this implementation, |△V _S2 |<|(1+2R ₃ /R ₁ )△V _S1 | [15] . That is, the distortion in the embodiment shown in FIG.
It can be seen that it is smaller than the conventional example shown in the figure. Furthermore, the drive ability of the embodiment shown in FIG. 3 with respect to the load will be examined. As is clear from FIG. 4, in the embodiment of FIG. 3, either transistor Q ₃ or Q ₄ always has its gate biased to the power supply voltage or ground potential. Therefore, since the output impedance of the output terminal _O2 is reduced, it is clear that the drive ability for the load is improved compared to the conventional example shown in FIG.
FIG. 5 shows another embodiment of the present invention, in which the same functional parts as in FIG. 3 are denoted by the same reference numerals. In such an embodiment, a resistor is connected between the drains of transistors Q ₃ and Q ₄ .
R ₄ and R ₅ are connected in series, and the output O ₂ is taken out from the connection point of resistors R ₄ and R ₅ . The operation of this embodiment is the same as that shown in FIG. 2, so a description thereof will be omitted, but this embodiment in particular achieves a reduction in power consumption and ease of circuit design. In other words, in Figure 4
Transistors Q ₃ , Q ₄ in states S ₆ and S ₈
Since both are conductive and their gate biases are deep, their impedances are small. Therefore, the through current between the power supplies increases. Therefore, the through current is limited by inserting resistors R ₄ and R ₅ ,
Reduces power consumption. Also, transistor
Q ₃ and Q ₄ are P-channel type and N-channel type transistors with completely different properties. Therefore, it goes without saying that these transconductances vary. Although the present invention improves the sound distortion caused by this variation, it is still not acceptable in practice unless the ratio of the transconductances of transistors Q ₃ and Q ₄ is suppressed to about 0.5 to 2.0. Further, it is not easy to set the transconductance ratio within the above range by changing the shapes of the transistors Q ₃ and Q ₄ , etc. Therefore, resistance
By inserting R ₄ and R ₅ and adjusting the ratio, the transconductance ratio can be easily set. This resistance ratio may be selected from 0.5 to 2.0. As described above, according to the present invention, it is possible to provide a signal generation circuit that can obtain the analog sum of two input signals, has little distortion in its output, and can easily drive a load. It goes without saying that the present invention is not limited to the above embodiments. That is, an AND circuit and an OR circuit may be applied instead of the NON circuit NR and the NAND circuit NA, respectively. Also, it is possible to combine multiple logic circuits, in short, a musical tone signal generation circuit.
When one of TG ₃ and TG ₄ is at a high level and the other is at a low level, both transistors Q ₃ and Q ₄ may be conductive. Furthermore, the present invention can be applied to any device that needs to calculate the analog sum of two input signals in addition to the multiple tone generation circuit.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a conventional example of a multiple tone generation circuit;
Figures a to c are time charts for explaining the operation of the conventional example in Figure 1, Figure 3 is a diagram showing an embodiment of the present invention, and Figures 4 a to e are diagrams for explaining the operation of the conventional example in Figure 3. A time chart for explaining the operation, FIG. 5 is a diagram showing another embodiment of the present invention. TG ₁ to TG ₄ ...Musical tone signal generation circuit. _R1 ～ _R5 ……
resistance. Q ₁ ~ _{Q 4} ... field effect transistor, O ₁
~O ₂ ...Output terminal, NR...NOR circuit, NA
... NAND circuit.

Claims (1)

[Scope of Claims] 1: first and second logic circuits receiving first and second signals, a first transistor whose input is the output of the first logic circuit;
a second transistor receiving the output of the logic circuit as an input, and an output terminal electrically connected to the output electrodes of the first and second transistors, the first and second logic circuits , said first
and when the signal levels of the second signals are different from each other, both the first and second transistors are made conductive, and both the first and second signals are connected to the first transistor.
signal generation characterized in that the first transistor is made conductive when the signal level is taken as , and the second transistor is made conductive when the first and second signals both take a second signal level. circuit. 2. A patent claim characterized in that the first logic circuit includes an OR circuit, the second logic circuit includes an AND circuit, and the conductivity types of the first and second transistors are different from each other. range 1
Signal generation circuit described in section. 3. The first logic circuit includes an OR circuit and an inverter that inverts its output, and the second logic circuit includes an AND circuit and an inverter that inverts its output. The signal generator according to scope 1.