JPS6218009B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a photometer, and more particularly to a high-sensitivity photometer equipped with a zero adjustment circuit.

Liquid chromatography is a useful tool for separating and analyzing trace mixture components. In order to increase the detection sensitivity of trace components, it is necessary to make the photometer used as a detector highly sensitive.

On the other hand, in a photometer, the sample light and standard light are generally not the same. This is due to factors such as the wavelength used, dirt on the flow cell, and the type of solvent flowing.

FIG. 1 is an example of a photometer used as a detector in a conventional liquid chromatograph.

The eluent sent from the pump 1 passes through a separation column 2 and a flow cell 6 of a photometer, where its absorbance is measured and then drained. On the other hand, one of the sample photometry 4 and standard photometry 5 leaving the spectrometer 3 passes through the absorption cell 6 and reaches the photoelectric conversion element 7, and the other one reaches the photoelectric conversion element 8.
reach. The photocurrent of the photoelectric conversion element 7 is converted into a voltage by a resistor 9 and an amplifier 10, and this voltage is adjusted to a specified voltage by a resistor 11, an amplifier 13, and a variable resistor 12. Similarly, on the standard side, the photocurrent of the photoelectric conversion element 8 is converted into a voltage by a resistor 15 and an amplifier 16, and this voltage is adjusted to a specified voltage by a resistor 17, an amplifier 19, and a variable resistor 18.

The output voltages of amplifiers 13 and 19 are connected to resistors 14,
20 into an absorbance converter 21. The absorbance converter or logarithmic converter 21 is connected to resistors 14 and 2
Outputs the logarithmic difference of the current flowing from 0 as a voltage. Therefore, when both currents are equal, the output voltage is
It is 0V. For example, if the decade is 1V, when the current flowing through resistor 20 is 1/10 of the current flowing through resistor 14, the absorbance is 1 and the output voltage is 1V.
It is. Similarly, when the current flowing through the resistor 20 is 1/100, the absorbance is 2 and the output voltage is adjusted to 2V.

The output voltage of the absorbance converter 21 passes through the output terminal 22 and enters the voltage dividing circuit 60 via the resistor 23. The voltage dividing circuit 60 includes resistors 24, 25, 26, and 27, and is switched to one of terminals _P1 to _P4 by the range changeover switch 28 and recorded by the recorder 30. The capacitor 29 is for removing noise from the signal.

The resistance values of voltage dividing resistors 24 to 27 are sequentially set to 1Ω, 9
Ω, 90Ω, and 900Ω, P ₄ points become 1
Absorbance full scale (AUFS), P ₃ points are
0.1AUFS, P ₂ points is 0.01AUFS, P ₁ point is
This means that measurements can be made with a sensitivity of 0.001 AUFS. Therefore, when the variable resistor 12 is moved by a certain angle, the position of the range changeover switch 28 at which the recorder 30 swings is
The disadvantage is that it is more difficult to adjust the recorder's indication to a predetermined value because it is 1000 times more magnified and swings when it is at point _P1 than when it is at point _P4 .

If the photocurrents of the photoelectric conversion elements 7 and 8 are approximately the same, the variable range of the variable resistor 12 can also be reduced.
The type of eluent flowed through separation column 2 varies depending on the purpose of analysis, and in the case of water-based eluent, the wavelength is between 200 nm and 350 nm.
Although there is almost no absorption in the eluent itself in the ultraviolet region of
For example, if the eluent is methanol, it will absorb 1/10 or 1/100 depending on the wavelength.
The variable resistor 12 of the photometer as a detector must be adjustable over a wide range so that the sensitivity can be increased by a factor of 10 or 100. However, the wider the adjustment range of the variable resistor becomes, the more difficult it becomes to match the high-sensitivity range.

Now, when the resolution of variable resistor 12 is 1AUFS, it is 0.1%.
Then, when the range of the voltage divider circuit 60 is 1AUFS, it can be adjusted with a roughness of 0.1% of the full scale, but when it is 0.1AUFS, it can be adjusted with a roughness of 1% of the full scale, and when it is 0.01AUFS, it can be adjusted with a roughness of 1% of the full scale. At 0.001 AUFS, the roughness will be adjusted to 10% of the full scale. This cannot be considered a practical adjustment.

In this way, in the conventional photometer shown in Figure 1, there is a sensitivity difference of 1000 times between 0.001 absorbance full scale and 1 absorbance full scale, and the adjustment work using a variable resistor for zero adjustment during high sensitivity measurement is difficult. It's tedious and lacks accuracy. In addition, this type of photometer also has the trouble of having to make zero adjustments while checking the readings on the recorder.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly sensitive photometer that allows easy and accurate zero adjustment.

The present invention is provided with a zero adjustment circuit that receives the output from the photometry section and a switch section that supplies a start signal to the zero adjustment circuit, and the zero adjustment circuit includes an addition circuit that takes the output from the photometry section as one of its inputs. A comparison section that compares the output of this addition circuit with a reference voltage, a digital-to-analog conversion section that supplies an analog signal as an input signal to the addition circuit, and a pulse signal to the digital-to-analog conversion section according to the output from the comparison section. It consists of a pulse signal supply circuit that supplies

In a preferred embodiment of the present invention, the output voltage of the absorbance due to the unbalance between the sample light and the standard light is applied to one end of the summing amplifier and the input, and the output voltage of the DA converter is applied to the other end of the input of the summing amplifier. Automatic zero compensation is performed by applying a voltage so that the output voltage of the DA converter has the same magnitude and opposite polarity as the output voltage of the absorbance converter at the summing point.

A preferred embodiment of the invention is applied to a liquid chromatograph. In this example, the separation section consists of a liquid pump and a separation column, a spectrometer, a flow cell, a photoelectric conversion element that receives sample photometry and standard photometry, and an absorbance converter that takes the logarithmic difference between the photocurrents of the photoelectric conversion elements. It is equipped with a photometry section. The automatic zero adjustment circuit includes a summing amplifier that sums the output of the photometry section and the output of the DA converter, a comparator that compares the output of the summing amplifier, and a level converter that converts the level of the output of the comparator. The output of the oscillator and level converter is used as the set input of a flip-flop, the output of this flip-flop is used as the gate signal of the gate circuit, the output of the oscillator is used as the other input of the gate circuit, and the output of the gate circuit is used as the input of a binary counter. , and a DA converter whose input is the output of this binary counter. Furthermore, a reset pulse generator consisting of an inverter that drives a monostable multivibrator with the output of a switch circuit that provides a start signal for automatic zero correction, and a monostable multivibrator that resets the reset terminals of the binary counter and flip-flop. a dividing circuit that divides the output of the summing amplifier;
It is equipped with a recorder for recording the output of the dividing circuit. The reference voltage of the comparison section is preferably 0V, but it can be set to other values if necessary.

In a preferred embodiment of the present invention, a plurality of automatic zero compensation circuits are connected in series, the output of the summing amplifier of the first automatic zero compensation circuit is used as the input of the summing amplifier of the second automatic zero compensation circuit, and The output of the gate circuit of the first automatic zero compensation circuit is input to the monostable multivibrator of the second automatic zero compensation circuit, the output of the second automatic zero compensation circuit is divided by a dividing circuit, and the output of the dividing circuit is recorded. Record with a meter.

FIG. 2 is a schematic diagram of an embodiment of the present invention. Components with the same symbols as in FIG. 1 have the same mechanisms. The photometric sample 4 passes through the flow cell 6 and is irradiated onto the photoelectric conversion element 7 . Similarly, the standard photometry 5 is applied to the photoelectric conversion element 8 . The photocurrents of the photoelectric conversion elements 7 and 8 are logarithmically converted by an absorbance converter 21 and converted into a voltage in units of absorbance. The output of the absorbance converter is directed to an automatic zero adjustment circuit 62. Absorbance converter 2
The output voltage of 1 is passed through a resistor 33 to a summing amplifier 36.
to go into. One of the output voltages of the summing amplifier 36 is connected to the output terminal 22 for recording and enters the voltage dividing circuit 60 via the resistor 23. 35 is a resistance.

The other one of the output voltages of the summing amplifier 36 enters a comparator 37. The comparator 37 operates when the input voltage crosses the reference voltage 0V from positive to negative. The output of comparator 37 goes into the base of transistor 38, and the collector of transistor 38 goes into the set terminal of flip-flop 39. The output T of the flip-flop 39 enters one end of the input of the NAND gate circuit 40, and the other end of the input of the NAND gate circuit 40 is connected to the oscillator 54.
The output of the NAND gate circuit 40 is the binary counter 4
The output of the binary counter 45 is input to the count input terminal IN of the digital-to-analog converter (DA
converter) enters 46. The DA converter 46 has an output voltage of -V ₁ when each bit of the input is 0, an output voltage of 0 V when the most significant bit (MOD) of the input is 1 and all other lower bits are 0, and a voltage of -V 1 when each bit of the input is 0. When it is 1, the output voltage is +V ₁ .
The output voltage of the DA converter 46 is the correction side input terminal 3
A summing amplifier 36 via a resistor 34 connected to
to go into.

When the switch 51 is pressed, a negative logic pulse is generated, which becomes a positive logic pulse at the inverter 53 and input to the monostable multivibrator 42. 52 is a resistance. Monostable multivibrator 42 has resistor 4
4. Generate a pulse with a pulse width determined by the capacitor 43. A positive logic pulse is generated from the Q output terminal of the monostable multivibrator 42 and input to the reset terminal R of the binary counter 45. Further, a negative logic pulse is generated from the output terminal of the monostable multivibrator 42 and inputted to the reset terminal R of the flip-flop 39. In the flip-flop 39, when the reset terminal S is 1 and the reset terminal R is changed from 1 to 0, the output T becomes 1, and when the reset terminal R is 1 and the set terminal S is changed from 1 to 0, the output T becomes 0.

Next, the operation of the automatic zero adjustment shown in FIG. 2 will be explained. FIG. 3 shows the voltage waveforms of each circuit.

First, it is assumed that the output voltage of the absorbance converter 21 is zero.
When switch 51 is pressed, a negative logic pulse is generated.
This pulse is inverted by the inverter 53 and becomes a positive logic pulse, which enters the monostable multivibrator 42. The output of monostable multivibrator 42 resets flip-flop 39 and binary counter 45. The output T of the flip-flop 39 becomes 1 level and enters the NAND gate 40. NAND gate 4
0 inverts and outputs the pulse of the oscillator 54 and enters the binary counter 45. On the other hand, when a reset pulse is input to the reset terminal of the binary counter 45, all bits of the output are set to 0. All bits of binary counter 45 are 0
Then, the output voltage of the DA converter 46 becomes _-V1 . When one end 32 of the input of the summing amplifier 36 becomes negative, the output of the summing amplifier 36 becomes positive, and the comparator 3
Since the output of transistor 7 is negative and the output of transistor 38 is 1 level, the output T of flip-flop 39 is 1.
remains at the level. (39-T in FIG. 3) When pulses are sequentially applied to the binary counter 45, the count value increases and at the same time the output voltage of the DA converter 46 begins to increase from _-V1 to 0V. The output voltage of the DA converter 46 is not smooth as shown at 46 in FIG. 4, but actually increases stepwise for each bit. When the output voltage of the DA converter 46 becomes 0, the output voltage of the comparator 37 also becomes 0. Furthermore, when the binary counter counts one pulse, DA
The output of the converter 46 becomes positive and the summing amplifier 36
The output of the comparator 37 is negative, the output of the comparator 37 is positive, the transistor 38 is turned on, and the output becomes 0. When the set input S of the flip-flop 39 becomes 0, the output T is inverted and changes from 1 to 0, closing the gate circuit 40 and stopping counting.

The automatic zero compensation is now complete.

In the above explanation, the output voltage of the absorbance converter 21 is 0.
Although it has been explained that the sum of the voltages on the measurement side 31 and the correction side 32 of the addition input terminal becomes 0, when the voltage on the addition input terminal 31 is -v, for example, the voltage on the addition input terminal 32 is +v. The circuit operates as follows.

If the resolution is n bits for the DA converter and the output voltage is -V ₁ to +V ₁ , then the resolution per bit is α
is α=1/2 ^n-1 .

For example, in a 12-bit DA converter, α=1/2 ¹¹ =1/2048≈0.0005, and the resolution is about 0.05%.

Furthermore, assuming that the automatic zero compensation speed is n bits for the DA converter 46 and the frequency of the oscillator 54 is F hertz, the time T for the voltage of the DA converter 46 to go from _-V1 to 0 is T=2 ^n-1 /F. It is.

For example, if the DA converter 46 is 12 bits and the frequency of the oscillator 54 is 10 kilohertz, T = 2048/10000 = 0.2048 (SEC) This is much faster than the work that a person would have to do by turning a variable resistor while looking at the instructions on a recorder. It is quick and accurate.

By performing automatic zero adjustment as described above, zero adjustment can be easily, accurately, quickly, and reproducibly performed.

Further, as explained in the above embodiment, for example, in a 12-bit DA converter, the resolution is 0.05%, and in a range of 0.001 AUFS, the roughness can be adjusted in units of 50% of the full scale. However, this is not always practically sufficient in many cases. This is because even if the range is 0.001 AUFS, trying to match the recorder's readings with a roughness of 0.1% requires an additional 500 times the resolution. For this purpose, a 21-bit DA converter with 9 more bits can be used. However, it is actually commercially available
The DA converter is 8 bits to 16 bits.

Another embodiment of the present invention, shown in FIG. 4, provides automatic zero compensation with even higher resolution. Components with the same reference numerals as in FIGS. 1 and 2 have the same functions.

As in FIG. 2, a pulse is applied to the monostable multivibrator 42 after the switch 51 is pressed, and the automatic zero compensation circuit 64 is activated after the reset pulse has finished being output.

The difference from FIG. 2 is that another automatic zero compensation circuit 66 is provided, and the output voltage of the first stage summing amplifier 36 is applied to the input 31a of the second stage summing amplifier 36a. The output of the NAND gate 40 in the second stage is
This is because it is added to the input of the monostable multivibrator 42a in the second stage.

In the embodiment shown in FIG. 4, the resolution of the voltage per bit outputted from the first stage is further increased by an n-bit DA converter 46a, and 2n-bit automatic zero compensation is performed.

Press the pushbutton switch 51, and a zero compensation start pulse is applied to the monostable multivibrator 42.
After the output pulse of the monostable multivibrator 42, that is, the reset pulse, has finished being output, each circuit 31 to 46 of the first stage automatic zero compensation circuit 64 starts operating.

While the first stage automatic zero compensation circuit 64 is counting, the pulse of the oscillator 54 is output to the output 41 of the NAND gate 40, so the output of the second stage monostable multivibrator 42a continues to output a reset pulse.

When the first stage automatic zero correction is completed, the addition amplifier 36
The output voltage corresponds to one bit of the DA converter 46, and the output terminal 41 of the NAND gate 40 stops transmitting pulses.

When the pulse at the output terminal 41 stops, the reset pulse of the monostable multivibrator 42a is no longer output, and the second stage automatic zero compensation is started. Thereafter, in the same manner as in FIG. 2, counting is stopped when the output voltage of the summing amplifier 36a changes from positive to negative. Note that the analog input signal in the second stage is the voltage for one bit in the first stage, and this is applied to the n-bit voltage in the second stage.
Since compensation is performed using a DA converter, the value of the resistor 34a is set to be 2 ^{n -1} times that of the resistor 33a.

By doing the above, you can obtain the same resolution as using a 2n-bit DA converter, so as mentioned above, when a 21-bit DA converter is required, you can achieve the purpose by using two stages of 12-bit DA converters. I can do it.

Further, in the embodiment of FIG. 4, automatic zero compensation is limited to two stages for convenience of explanation, but multi-stage automatic zero compensation can be performed by converting the pulse of the NAND gate to the reset signal pulse of the subsequent stage.

The number of bits of the DA converter does not have to be the same, and the number of bits can be changed to suit the purpose and be economical, such as n bits in the first stage and m bits in the second stage.

As explained above, according to the present invention, zero adjustment can be performed accurately and quickly with just the simple operation of pressing a push button.

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining a conventional photometer type detector, Fig. 2 is a diagram for explaining the schematic configuration of an embodiment of the present invention, and Fig. 3 is a diagram for explaining various parts of the embodiment of Fig. 2. FIG. 4 is an explanatory diagram of another embodiment of the present invention. 3... Spectrometer, 6... Flow cell, 7, 8...
Photoelectric converter, 21... Logarithmic converter, 28... Range selector switch, 36, 36a... Addition amplifier,
37, 37a... Comparator, 40, 40a...
...Gate circuit, 42, 42a... Monostable multivibrator, 45, 45a... Binary counter, 4
6, 46a...DA converter, 51...Switch,
53...Inverter.

Claims (1)

[Claims] 1. In a photometer equipped with a photometry section that irradiates light onto a sample and converts the light from the sample into an electrical signal, an addition circuit that takes the output from the photometry section as one of its inputs, and an output of this addition circuit and a reference. a comparison section that compares the voltage with the voltage, a digital-to-analog conversion section that supplies an analog signal as an input signal to the addition circuit, a pulse signal supply circuit that supplies a pulse signal according to the output from the comparison section, and a pulse signal supply circuit that supplies the pulse signal according to the output from the comparison section; A plurality of stages of zero adjustment circuits each having a counter that counts a signal and outputs a digital signal to the digital-to-analog conversion section are provided, and a switch section that supplies a start signal to the zero adjustment circuit of the previous stage is provided, and the zero adjustment circuit of the previous stage is provided. A high-sensitivity photometer characterized in that the circuit is started by activating the switch section, and when the coarse adjustment of the zero point is completed, the fine adjustment of the zero point by the zero adjustment circuit in the subsequent stage is started.