JPS6218931B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to means and methods for translation between different number systems used in data processors. More specifically, this invention:
An improved means and method for providing fast conversion of binary coded decimal (BCD) numbers to binary format.

In binary system notation, each binary digit (bit) represents a different power of two. The least weighted bit represents ²⁰ , the next weighted bit is ²¹ , the next weighted bit is ²² , and so on. For example, in direct binary notation, the number 11101
is 1×2 ⁴ +1×2 ³ +1×2 ² +0×2 ¹ +1×2 ⁰ (=
Equivalent to 29) in decimal notation.

In the Binary Coded Decimal (BCD) system notation, each group of four bits represents one decimal digit. The same decimal number 29 mentioned above is written in BCD notation as
Represented by 0010 1001.

Automatic digital computers often require converting BCD numbers to binary form.
Various known approaches for providing such BCD-to-binary conversion are described in the article by L.C. Beougher, "Fast BCD-2", Computer Design, March 1973, pp. 53-59.
A Method for High Speed BCD
-to-Binary Conversion). This article should be considered as incorporated herein.

In the Beougher paper mentioned above, an improved BCD−
A binary conversion approach has been proposed.
The design principle following Beougher's BCD-to-binary conversion approach is based on the addition of columns of BCD bits created by a power-of-two expansion of each BCD digit. for example,
The decimal number 89 in BCD notation is 1000 1001, which is more completely (1000) ₂ (10) ₁₀ + (1001) ₂
(1) ₁₀ = (1000) ₂ (8+2) ₁₀ + (1001) ₂ (1) ₁₀
= (1000) ₂ (2 ³ + 2 ¹ ) ₁₀ + (1001) ₂ (2 ⁰ ) ₁₀ . As explained below, the equivalent binary value 1011001 of the BCD number 89 is obtained after multiplication by the appropriate power of 2 value according to the final formula above representing the power of 2 expansion of the BCD number 89. is obtained by adding the rows of BCD bits given by however,
Multiplication by a power of two in binary arithmetic is accomplished simply by shifting to the left a number of binary positions equal to the value of the exponent.

(1001) ₂ (2 ⁰ ) ₁₀ = 1001 = 9 (1000) ₂ (2 ¹ ) ₁₀ = 10000 = 16 (1000) ₂ (2 ³ ) ₁₀ = 1000000 = 64 1011001 89 This invention is based on Beougher's BCD- Directed towards improving the binary conversion approach, thereby
The same power-of-two expansion formula is used as taught by Beougher. However, for implementation purposes, instead of using a complex tree-structured 4-bit binary adder or look-ahead carry generator as in the Beougher paper, the present invention uses a novel array of PROMs (Programmable Read Only). The PROM takes great advantage of Beougher's approach to reduce the required hardware and achieve very fast BCD-to-binary conversion.

The invention also provides improved means and methods for accomplishing addition using PROMs.

BRIEF DESCRIPTION OF THE DRAWINGS Other objects, advantages and features of the invention, as well as its distinctive nature, will become readily apparent from the following detailed description of the preferred embodiments, taken in conjunction with the accompanying drawings.

Like elements are numbered like throughout the figures of the drawings.

In order to enable this invention to be clearly understood, specific preferred embodiments of the invention have been considered for illustrative purposes, in which, for example, a BCD number of 7 digits (which may be GFEDCBA or may be simply expressed as G~A)
is a 24-bit binary number (which is b ₂₃ , b ₂₂ , b ₂₁ ~ _{b 0}
or more simply expressed as b ₂₃ ~b ₀ ). It should be understood that A is the least significant digit of the BCD number, while _b0 is the least significant bit of the binary number. Also, for identification purposes, each of the four bits that make up one BCD digit is a
will be represented by its respective letter along with the number of powers. For example, BCD digit A
is represented by four binary bits A ₈ , A ₄ , A ₂ and A ₁ , where A ₁ is the least significant bit.

As pointed out earlier, this invention
We use the power of two expansion approach described in the Beougher paper. Therefore, using Beougher's power of two expansion approach, the table shown in Figure 2 is drawn representing the various columns of BCD bits, which are considered here. The 7-digit BCD numbers G-A need to be added to convert them into their equivalent 24-bit binary numbers _b23 - _b0 . The table in Figure 2
Specific details regarding aspects that may be derived for use in BCD-to-binary conversion are described above.
Included in the Beougher paper. For the purpose of this invention, which is directed to improved means and methods for realizing such a table, each of the binary bits b ₂₃ to b ₀ of the desired BCD-to-binary conversion is Appears directly below the binary bit in the table of Figure 2, along with any carry resulting from the addition.
It is sufficient to understand that it is obtained by adding a sequence of BCD bits. For example, binary bit b ₃ is added to the BCD bit along with any carry that results from the addition of the previous column.
Obtained by adding A ₈ , B ₄ , B ₁ , C ₂ and D ₁ .

Now, with reference to FIG. 1, by performing the addition shown in the table of FIG. 2, the equivalent binary number b ₂₃ of the 7-digit BCD number G ~ A in the explanation is obtained.
An overall diagram of a preferred embodiment of the invention for providing BCD-to-binary conversion to b ₀ is shown. As illustrated, the preferred embodiment shown in FIG. Ta)
an input register 10 for receiving and storing
First and second level logic (circuits) 12 and 14 implemented using a specially selected arrangement of PROMs as illustrated in FIG. 2, and a third level using conventional addition and carry generation techniques. logic (circuit) 16 and the 24-bit binary number b ₂₃ given by the output of the third level logic 16
b Output register 18 for receiving and storing ₀
including. The BCD-to-binary conversion according to the preferred embodiment of FIG. 1, as was the case for the full adder implementation disclosed in the Beougher paper mentioned above, is preferably accomplished in a parallel manner in less than one clock. , it must be understood that.
Embodiments of the present invention for converting decimal numbers having different numbers of BCD digits also include BCD-
It will become clear from the explanation of binary conversion. That must also be understood.

At this point in the discussion, logic level 1 in FIG.
In order to arrange and realize 2, 14 and 16,
It may be useful to note that almost infinite variations in logical arrangement are possible.
According to the invention, the logical level 1 provided
The implementation of the specific logic used for each level as well as the specific divisions of 2, 14, and 16 derives not only from the specific features of the BCD-to-binary conversion but also from Beougher's approach mentioned earlier. are specifically chosen to take advantage of specific characteristics that also arise from

The first objective of the preferred embodiment of FIG. 1 is to step through a relatively long string of BCD bits that must be added according to the table of FIG. 2 using the three logic levels 12, 14 and 16 described. It is to reduce the number of people. The first and second logic levels 12 and 14 are high speed PROMs that are individually programmed in each of levels 12 and 14.
are realized in a particularly advantageous manner by using a special arrangement of , each of which significantly reduces the number of PROMs that would otherwise be required for this purpose. The resulting logic provided by levels 12 and 14 reduces the bits to be added in each column to only 2 bits per column. This means that each of the binary output bits b ₂₃ -b ₀ of the equivalent binary number are then immediately given by the third logic level 16 in FIG. 1 using conventional addition and carry generation techniques. allow yourself to be

Referring to Fig. 3, this Fig. 3 corresponds to Fig. 1.
1 schematically illustrates a preferred embodiment for logic level 12; The table in FIG. 2 was specially selected to be used for the first logic level 12.
Note that it has been replaced directly with FIG. 3 for use in explaining the PROM layout. This provides convenient identification of specific BCD bits and their respective column positions to be added by each of the 12 PROMP ₁ - P ₁₂ provided for the first logic level 12. It is done for the purpose of That is, PROMP ₁ to _{P 12} of the first logic level 12 shown in FIG.
It will be appreciated that the particular columns of BCD bits to be added by each of the PROMs are those columns containing the particular BCD bits enclosed within the border representing each PROM. For example, PROM
P ₁ is BCD bit A ₂ , A ₄ , A ₈ , B ₁ , B ₂ , B ₄ and
Give the addition of the columns constituted by G ₁ , where
BCD bits A ₂ and B ₁ are column b ₁ of the table,
BCD bits A ₄ , B ₂ and C ₁ are in column b ₂ of the table, and BCD bits A ₈ and B ₄ are in column b ₃ of the table.

At this point in the discussion, it will be appreciated why the PROM arrangement shown for the first logic level 12 of FIG. 3 was chosen specifically in accordance with the present invention.
It would be appropriate to think about it. Obviously, many different types of PROM arrangements are possible. This is because not only the size and programming of the PROM is variable, but the particular combination of selected inputs to be applied to the PROM is also variable. It will be appreciated that one straightforward approach to providing a PROM implementation is to arrange the PROM to provide a simple addition of each of the columns in the table of FIG. This was not done in accordance with this invention. Instead, and as previously mentioned, the present invention exploits the previously mentioned Beougher approach and specific features of BCD-to-binary conversion, thereby providing a highly advantageous overall implementation. In particular, the advantageous use of these features is considered in detail here, in the special PROM used for the first logic level 12 in FIG.
The choice of placement has been made.

Note that in the table in Figure 2 derived from Beougher's approach, certain BCD bits appear in multiple columns in the table. For example, C ₁ is in columns b ₂ , b ₅ and b ₆
and D ₁ appears in columns b ₃ , b ₅ , b ₆ , b ₇ , b ₈ and b ₉ . As will be considered in more detail shortly, the present invention allows the PROM to add columns containing a greater number of input BCD bits than would otherwise be possible based on the capabilities of the PROM's actual inputs. The format takes advantage of the presence of these duplicate bits in the table.

Another feature utilized in selecting the PROM layout for the first logic level of FIG. 3 is derived from the fact that the value of the BCD digits does not exceed nine. Therefore, combinations of values of certain BCD bits in the table corresponding to BCD digits greater than or equal to 9 cannot occur. This feature is also shown in Figure 1 in Figure 2.
The particular configuration useful in selecting the logic level 12 PROM placement will also be considered in more detail shortly.

PROM for the first logic level 12 of FIG.
Other characteristics used in choosing the placement of each
Based on selecting the BCD input to each PROM such that the resulting output from the PROM is free of carry. This means that no carries need be propagated or calculated between PROMs at the first logic level 12 or
It offers the advantage of not having any connection to logic level 14.

The features summarized above and their application to the preferred embodiment of the invention are illustrated for the first logic level 12 in FIG.
It will be considered in more detail with particular reference to the arrangement of PROMs P ₁ -P ₁₂ . Each of PROM P ₁ -P ₁₂ is typically implemented as a 256.times.4 bit PROM using, for example, a Fairchild No. 93427 integrated circuit chip.
Such a 256 x 4 bit PROM has a maximum of 8 inputs and 4 outputs. PROM P ₅ at the first logic level 12 in FIG. 3 shows how the presence of duplicate BCD bits occurring in the table of FIG. We provide one good example of how it may be useful in accordance with this invention to allow a PROM to provide column additions from a containing table. In Figure 3, there are two columns containing 12 input BCD bits, even though only 8 inputs are available for a 256 x 4 bit PROM.
Note that PROM P ₅ gives addition. This means that these 12 from the table
By judicious selection of the BCD bit input of
PROM P ₅ is achieved and therefore meets the following conditions: _{( 1 )} Only 8 _of these _{12 input BCD} bits are _unique ; The remaining four input BCD bits C ₄ , D ₁ , D ₂ and D ₄ are duplicated), and (2) these
The sum of 12 selected input BCD bits is never
15 or 1111, thereby preventing carries from the PROM.

Achieving condition (2) above is aided by the fact that the value of the BCD digit cannot exceed 9.
For example, in relation to PROM P ₅ , if a BCD of 12
If all of the bit inputs have binary ones at the same time, the sum is 19 or 10011, then
Since carry is generated from PROM, condition (2) is not met. However, since it is known that the 12 inputs to PROM P ₅ are BCD bits whose corresponding BCD digits cannot be greater than 9, the two most significant bits of the same BCD digit are both 2 at the same time. It never has a base 1. For example, two BCD digits C and D
The two most significant BCD bits C ₄ , C ₈ and D ₄ , D ₈ are
Each is included in the 12 inputs provided to PROM P ₅ . These two top levels of the same BCD
Since both BCD bits do not have binary 1 at the same time, the 12 bits to be added by PROM P ₅ are
The maximum possible sum for the two columns containing BCD bits is 15 or 1111, which is within the maximum sum limit of condition (2) above.

The table in Figure 2 for addition according to PROM P ₅
The same principle as illustrated above for selecting a particular column of BCD bit inputs can also be used to select a particular column of BCD bits to be applied by another PROM of the first logic level illustrated in FIG. It is used whenever appropriate to select columns, so that very little overall hardware is required compared to what would otherwise be required. will be understood. Furthermore, this savings in hardware means that the logic provided by the first logic level 12
Since there is no carry propagation required between PROMs,
It allows economical use of one level of PROMs operating in parallel with each other and independently of the others.
It must then be considered that each of the first logic level PROMs _P1 to _P12 illustrated in FIG. It is a particular form of being independently programmed to provide the addition of . For this purpose, attention is first drawn to the following general formula, which at the first logic level 12 of the preferred embodiment of the invention considered here:
Used to determine the programming provided for the PROM.

where S is the binary sum given by the PROM in response to the binary input applied to it, and n
is the maximum number of inputs that the PROM can receive, B _k = B ₁ , B _{2 .} . . B _o represents the specific unique BCD inputs given to the PROM, and W _k =
W ₁ , W ₂ , . . . W _o are the respective weight values for the BCD inputs that the PROM is programmed to take into account in order to give the appropriate value of the sum S. Each weight value is chosen to represent both column positions as well as the presence of any overlap. This should be added by a PROM as shown in Figure 3 starting from the least significant column (rightmost column) of bits and continuing to the most significant column (leftmost column).
This is done by assigning a power of two (1, 2, 4, etc.) to a string of BCD bits. Thus, the lowest column is assigned a value of 1, the next column to the left is assigned a value of 2, the next column is assigned a value of 4, and so on. Where there are no duplicate BCD bits, the value of this column is equal to the weight value W in equation (1). Where there is overlap, the weight value W is obtained by adding together the values of all the overlap columns.

Also, in order to eliminate the carry from PROM,
The sum S from each PROM must satisfy the following equation.

S2 ^q −1 ...(2) where q is the available individual 2 from PROM
It is the number of advance forces.

As previously noted, in the illustrative PROM arrangement for the first logic level 12 shown in FIG. It is PROM.
Therefore, n in the above equation (1) becomes 8, and q in the above equation (2) becomes 4. Equations (1) and (2) are
Therefore S= ^24-1 =15 or 1111...(2A).

PROM P ₅ is again used as an example to explain how equations (1A) and (2A) above are used to implement each PROM in FIG. Therefore, from Figure 3, PROM
The eight unique BCD inputs given to P ₅ are C ₂ , C ₄ , C ₈ , D ₁ , D ₂ , D ₄ , D ₈ contained in columns b ₇ and b ₈
and E ₁ . Equation (1A) above will be expanded as follows when applied to PROM P ₅ .

S ₅ = C ₂ +3C ₄ +2C ₈ +3D ₁ +3D ₂ +3D ₄ +2D ₈ +2E ₁ … (1B) BCD in the above equation (1B) for PROM P ₅
The weight values for the bits are chosen to take into account both column positions and the presence of overlap, as explained above. That is, the weight value for each of the overlapping BCD bits C ₄ , D ₁ , D ₂ and D ₄ is 3 in equation (1B) above. this is,
Each occurs once _in both columns b _{7 and} b ₈ in FIG.
This is because the presence of the BCD bit gives a weight value of 2. For the remaining non-overlapping BCD bits, BCD bit C ₂ is only present in column b ₇ and therefore has a weight value of 1 in equation (1B), and BCD bits C ₈ , D ₈ and E Note that ₁ is present only in column _b8 so each has a weight value of 2 in equation (1B).

The above embodiment in which equation (2A) above is advantageously adapted for PROM P ₅ has already been considered earlier for PROM P ₅ , so repetition is avoided.

Now a summation equation similar to equation (1B) above for PROM P ₅ can also be readily given in a similar manner for each of the other PROMs in the first logic level 12 of FIG. The specific sum formula for each PROM is:
That should be clear.

PROM P ₁ :S ₁ =A ₂ +2A ₄ +4A ₈ +B ₁ +2B ₂ +4B ₄ +2C ₁ PROM P ₂ :S ₂ =B ₁ +2B ₂ +2B ₈ +C ₂ +2C ₄ +5D ₁ +2D ₂ +2E ₁ PROM P ₃ :S ₃ =B ₄ +2B ₈ +3C ₁ +2C ₂ +C ₈ +D ₄ +E ₂ +F ₁ PROM P ₄ :S ₄ =D ₁ +D ₂ +D ₈ +E ₄ +2E ₈ +F ₂ +G ₁ PROM P ₅ :S ₅ =C ₂ +3C ₄ +2C ₈ +3D ₁ +3D ₂ +3D ₄ +2D ₈ +2E ₁ PROM P ₆ :S ₆ =4D ₁ +F ₁ +2F2+F ₄ +2F ₈ +4G ₁ +G ₂ +2G ₄ PROM P ₇ :S ₇ =C ₈ +3D ₂ +3D ₄ +3D ₈ +3E ₁ +3E ₂ +2F ₂ +2F ₈ PROM P ₈ :S ₈ =4E ₂ +2E ₄ +3F ₁ +F ₄ +2G ₂ +G ₈ PROM P ₉ :S ⁹ =D ₄ +3D ₈ +3E ₄ +3E ₈ +F ₂ +3F ₄ +6F ₈ +2G ₈ PROM P ₁₀ :S ₁₀ =E ₄ +2E ₈ +3F ₁ +2F ₂ +2G ₁ +G ₂ +2G ₄ +4G ₈ PROM P ₁₁ :S ₁₁ =F ₂ +3F ₄ +6F ₈ +3G ₁ +3G ₂ +2G ₄ +4G ₈ PROM P ₁₂ :S ₁₂ =G ₁ +3G ₂ +7G ₄ +14G _8Each of the PROMs P ₁ to _{P 12} in FIG. 3 can be individually programmed by one skilled in the art to operate in accordance with its respective sum formula shown above. , so that even if the number of BCD bits to be added by the PROM exceeds the capability of the input of the PROM, the number of BCD bits to be added by the PROM as shown in FIG.
It will be appreciated that this will give an output sum that will correctly represent the sum of a particular column of BCD bits. Also, as explained earlier, in order to obtain the advantage of not having to be concerned with the generation of carry by PROM, the sum is, whenever possible, the fact that the BCD digits cannot have a value greater than 9. PROM while making more use of
Judicious selection of the particular row of BCD bits to be added by will prevent reaching values that would cause carry. Further, that each PROM can be programmed to provide the individual programming required according to its respective summation formula set forth above without the need to modify or add to the internal PROM hardware. It will be appreciated that because of the ease of implementation, the use of PROMs to implement the preferred implementation shown in FIG. 3 is well suited.

Referring to FIG. 4, consideration must now be given to the preferred embodiment of the second logic level 14 shown generally in FIG. From the previous description of the preferred embodiment of the first logic level 12 shown in FIG.
It will be appreciated that this provides the addition of specific selected columns of BCD bits as required by the table of FIG. The second logic level 14 is the first
provides the addition of selected columns of bits applied to the outputs of the logic levels 12 of the table column b ₀ ~
b Continue the gradual decrease of bits in ₂₃ and
The output of logic level 14 remains two bits for each column to be summed with the output of its second logic level 14. For this purpose, the second logic level 14 also preferably uses a PROM implementation, the PROM being a PROM P ₁₃
~P ₁₇ in the preferred embodiment of FIG. For ease of comparison with FIGS. 2 and 3, it may be noted that FIG. 4 repeats the identification of b ₀ -b ₂₃ . In this regard, it will be recalled that each of b ₀ -b ₂₃ represents a respective bit of the equivalent binary number to which a given BCD number is being converted. Also, these bits b ₀ ~
b Each value of ₂₃ is calculated from the corresponding column in the table of Figure 2, taking into account any carry from the previous column.
Recall that it is obtained by adding all of the BCD bits together.

In more detail, now considering FIG. 4, this FIG. 4 shows that the result of the addition accomplished by the first logic level 12 of FIG. It must be understood that this indicates the remaining additions to be made. Similar to Figure 3, Figure 4 shows the PROMs P ₁₃ to _{P 17} of Figure 4 enclosed within a border representing each
A format similar to that of FIG. 3 is used for the particular column of bits to be added by each of the following. In FIG. 4, bits A ₁ , E ₁ , E ₂ , E ₈ , G ₁ and G ₄ which were not given to any of the PROMs P ₁ to P ₁₂ in FIG. 3 due to the addition
Note that the have been replaced unchanged in FIG. 4 in their appropriate column positions as shown. Figure 3 PROM
The 4-bit outputs representing the sum of additions accomplished by P ₁ -P ₁₂ have also been transferred to FIG. 4 in their appropriate column positions. For identification purposes, each of the four bits representing the sum of PROMs represents its respective PROM followed by a power of two number (1, 2, 4, or 8) representing the weight order of that bit. It is indicated in FIG. 4 by a capital letter S with a subscript representing. For example, the four bits representing the sum S ₅ from PROM P ₅ in FIG. 3 are the symbols P ₅ 1, P ₅ 2, P ₅ 4 and _{P 5} 8 in FIG. ).

Regarding Figure 4, PROM in Figure 3
Note that the same type of 256 x 4 bit PROM as used for each of P ₁ -P ₁₂ can be used for each of PROMs P ₁₃ -P ₁₇ . Furthermore, for the size of the PROM and the particular choice of BCD-to-binary conversion example considered here for illustrative purposes, the number of bits in each column achieved by the PROM implementation of FIG. Because of the huge reduction in only 5 PROM P ₁₃ ~
Note that P ₁₇ is required at the second logic level 14 to achieve the desired gradual reduction of the bits to be added in each column to just 2 bits per column. . Therefore, the particular diagram shown in FIG.
The PROM is characterized by the features of this invention used in the realization of the PROM shown in FIG.
There is no need to take advantage of the PROM size, which allows more bits to be added by the PROM. However, in different situations, such as where different PROM sizes are chosen and/or where different numbers of BCD digits are to be converted, one or more Advantages of using this feature may also be envisaged at subsequent levels, and the invention should therefore be considered to include such embodiments as well.

There is no need for the PROM implementation of Figure 4 to provide addition of a larger number of bits than a normal PROM can input, but the lack of carry from the PROM as explained earlier means that here This is the most advantageous in the contemplated preferred embodiment. The particular bits selected to apply to each of the PROMs _P13 to _P17 of FIG. 4 therefore meet this condition in the same manner as described in connection with the implementation of the PROM of FIG. selected to meet.

Using the general formula (1) presented above for the sum S and the same principle as used for PROM P ₁ to _{P 12} in FIG. 3, PROM P in the specific realization of FIG. The formula for the sum for each of ₁₃ to _P17 is as follows.

PROM P ₁₃ :S ₁₃ =P ₁ 4+2P ₁ 8+P ₂ 1 +2P ₂ 2+ _4P 2 4+4P ₃ 1 PROM P ₁₄ :S ₁₄ =P ₂ 8+P ₃ 2+2P ₃ 4 +P ₄ 1+2P ₄ 2+2P ₅ 1+2P ₆ 1+
4P ₆ 2 PROM P ₁₅ :S ₁₅ =P ₃ 8+P ₄ 4+P ₅ 2 +2P ₅ 4+2P ₆ 4+2P ₇ 1+4P ₇ 2+
2P ₈ 1 PROM P ₁₆ :S ₁₆ =2G ₄ +P ₅ 8+P ₆ 8 +2P ₇ 4+P ₈ 2+2P ₈ 4+4P ₈ 8+
2P ₉ 1 PROM P ₁₇ :S ₁₇ =2E ₁ +4E ₂ +2E ₈ +4G ₁ +P ₇ 8+P ₉ 2+2P ₉ 4 As previously pointed out, for the particular preferred embodiment considered here, FIG. 2 logic level 14 reduces the bits to be added in columns b ₀ -b ₂₃ of the table of FIG. without reducing the high speed operation afforded by the PROM implementation.
The third logic level 16 of the figure allows conventional adder and carry generation circuitry to be provided economically. A preferred embodiment of the third logic level 16 will now be considered in more detail with reference to FIG.

The third logic level 16 illustrated in FIG. 5 is of a form similar to that of FIGS. 3 and 4, and as in FIG. The column symbols b ₀ -b ₂₃ of the table in FIG. 2 are repeated to immediately indicate the remaining additions to be performed by the third logic level 16 on the bits applied thereto. In this regard, the outputs of PROM P ₁ -P ₁₂ are shown in the second logic level 1 of FIG. 2 in the same manner as they are represented in FIG.
The 4-bit output from each of the 4 PROMs _P13 to _P17 is output to the third logic level 16 shown in FIG.
Please note that it is expressed in

The preferred embodiment of the third logic level 16 shown in FIG. 5 will now be considered in more detail. Third
The logic level 16 typically includes 4-bit binary adders 31-34, one look-ahead carry generator 36, one AND gate 38 and one exclusive-OR gate 4 operating in conjunction with them.
It can be seen that it includes 0. Adders 31-3
Each of 4 is implemented using, for example, a Texas Instrument integrated circuit chip number 74S181, and each of the carrier generators 3
6 is implemented using, for example, a Texas Instruments number 74S182 integrated circuit chip, and gates 38 and 40 are implemented using, for example, a Texas Instruments number 74S08 and 74S86 integrated circuit chip.
Each can be realized using The particular columns of bits that are added to each of adders 31-34 in FIG. 5 for the addition thereof are shown within the block representing each adder. and gate 3
8 and the bits added to exclusive-or gate 40 are shown in conventional form. Also note that the lowercase letters c, g, and p in FIG. 5 indicate carries that occur and propagate to the input and output, respectively, in the conventional configuration.

Therefore, from FIG. 5, the adders 31 to 34 output bits _b23 to _b7 (output bits _b23
is the carry generated by adder 34. ), while the AND gate 3
8 and exclusive-or gate 40 serve to provide the output bit b ₆ as well as its carry to adder 31 and carry generator 36. As far as the remaining output bits b ₀ to b ₅ of the equivalent binary number are concerned, FIGS.
From the table in Figure 2 related to the figure, the lowest
BCD bit A ₁ is equal to b ₀ and therefore propagates unchanged through the logic levels, bits b ₁ and b ₂ are given directly by the outputs P ₁ 1 and P ₁ 2 of PROM P ₁ , respectively. , and that bits b ₃ , b ₄ and b ₅ are PROM P ₁₃
It will be understood that the outputs of P ₁₃ 1, P ₁₃ 2 and P ₁₃ 4 are given directly.

The formula for the equivalent binary bits b ₀ to b ₂₃ representing the logic achieved by the third logic level of FIG. 5 is: is represented by a lowercase letter "c" with

b ₀ = A ₁ b ₁ = P ₁ 1 b ₂ = P ₁ 2 b ₃ = P ₁₃ 1 b ₄ = P ₁₃ 2 b ₅ = P ₁₃ 4 b ₆ = P ₁₃ 8 + P ₁₄ 1 b ₇ = P ₁₄ 2 + c ₆ b ₈ =P ₁₄ 4+P ₁₅ 1+c ₇ b ₉ =P ₁₄ 8+P ₁₅ 2+c ₈ b ₁₀ =P ₁₅ 4+P ₁₆ 1+c ₉ b ₁₁ =P ₁₅ 8+P ₁₆ 2+c ₁₀ b ₁₂ =P ₁₆ 4+P ₁₇ 1+c ₁₁ b ₁₃ =P _{1 6} 8+P ₁₇ 2+c ₁₂ b ₁₄ =P ₁₇ 4+P ₉ 8+c 13 b _{15 =} P ₁₇ 8+P ₁₀ 1+c ₁₄ b ₁₆ =P ₁₀ 2+c ₁₅ b ₁₇ =P ₁₀ 4+P ₁₁ 1+c ₁₆ b ₁₈ =P ₁₀ 8+P ₁₁ 2+c ₁₇ b ₁₉ = P ₁₁ 4 + P ₁₂ 1 + c ₁₈ b ₂₀ = P ₁₁ 8 + P ₁₂ 2 + c ₁₉ b ₂₁ = P ₁₂ 4 + c ₂₀ b ₂₂ = P ₁₂ 8 + c ₂₁ b ₂₃ = c ₂₂ This invention contemplates modifications in structure without departing from the scope of this invention. and is subject to a wide variety of modifications, arrangements and uses. The invention is therefore to be regarded as including all possible modifications and variations within the scope defined by the appended claims.

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram of a preferred embodiment of a BCD-to-binary converter according to the present invention. FIG. 2 is a diagram for explaining the addition achieved by the embodiment of FIG. 1 which implements the BCD-to-binary conversion described in accordance with the present invention. FIG. 3 is a schematic diagram illustrating a preferred embodiment of the first logic level 12 of FIG. FIG. 4 is a schematic diagram illustrating a preferred embodiment of the second logic level 14 of FIG. Figure 5 is the third part of Figure 1.
1 is a schematic block diagram illustrating a preferred embodiment of logic level 16 of FIG. In the figure, 10 is the input register, 12 is the first
14 is the second logic level, 16 is the third logic level, 18 is the output register, 31-
34 is a 4-bit binary adder, 36 is a look-ahead carry generator, 38 is an AND gate, and 40 is an exclusive OR gate.

Claims (1)

[Claims] 1. 2 for adding multiple columns of input binary signals
a base adder comprising a first level logic circuit comprising a plurality of individually programmed PROMs, each of said first level PROMs having a predetermined plurality of said two PROMs in consideration of their column positions; each PROM of said first level is programmed to provide a PROM output binary signal representing an addition of a binary input signal; It is of such a size that it will not occur,
further comprising a second level of logic circuitry provided with an output binary signal from said first level, said second level comprising a plurality of individually programmed PROMs, each said second level PROM being connected to said first level; in response to a predetermined plurality of binary signals selected from and applied thereto from the PROM output binary signals provided by the first level and the input binary signals not yet applied.
Each PROM of said second level is programmed to provide a PROM output binary signal, and each PROM of said second level is sized such that no carry occurs therefrom depending on the addition accomplished with the binary signal provided thereto. be,
Binary adder. 2. the adder includes an additional logic circuit provided with any input binary signal and the residual first and second level PROM output binary signals to be added in each column; 2. A binary adder as claimed in claim 1, wherein the logic circuit is operative to provide the final addition required for a sequence of input binary signals. 3. At least one additional level logic circuit and a final level logic circuit are provided, and said first, second and additional level logic circuits are operative to progressively reduce bits in said column. , so that only two bits per column remain to be added by said final level logic circuit. 4. The particular binary signal applied to at least one PROM and its programming are selected to add more binary signals than the maximum number of available PROM inputs.
3. The binary adder according to claim 1, 2 or 3. 5 2 given to said at least one PROM
Binary signals are available in a number of unique binary signals.
The maximum number of PROM inputs is chosen not to exceed, the remaining binary signals are redundant, and these unique binary signals are provided as PROM inputs, and the programming of said at least one PROM is , wherein the addition provided thereby is chosen to take into account the presence of any duplication of the unique inputs as well as their position in the column. . 6. said at least one PROM is programmed according to the formula: where S is the binary sum given to the output of said at least one PROM and n is the available
Maximum number of PROM inputs, Bk = B ₁ , B ₂ − Bn
denotes a unique binary signal (any additional binary signal is a duplicate), and Wk = W ₁ , W ₂ −Wn are the weight values, each weight value being the presence of each duplicate. 6. A binary adder as claimed in claim 5, having a value that takes into account the presence and column position of each unique binary signal as well as its respective column position. 7.2 for adding multiple columns of input binary signals
a binary adder comprising at least one level of logic comprising a plurality of individually programmed PROMs, each PROM providing a PROM output binary signal representing the addition of a predetermined plurality of said binary input signals; and at least one PROM having an input binary signal and programming selected to add more binary signals than the maximum number of PROM inputs available. vessel. 8. The particular binary signals applied to said at least one PROM are chosen such that the number of unique binary signals does not exceed the maximum number of PROM inputs available and the remaining binary signals are duplicated. and these unique binary signals are provided as PROM inputs, and programming of said at least one PROM ensures that the additions provided thereby apply not only to their column positions but also to any of said unique binary signals. 8. A binary adder as claimed in claim 7, selected to take into account the presence of overlap. 9. said at least one PROM is programmed according to the formula: where S is the binary sum given to the output of said at least one PROM and n is the available
is the maximum number of PROM inputs, Bk = B ₁ , B ₂ −Bn represents a unique binary signal (any additional PROM input binary signals are redundant), and Wk = W ₁ ,
W ₂ −Wn are weight values, such that each weight value has a value that takes into account not only the presence of each overlap and its respective column position, but also its respective unique binary signal presence and column position. 9. A binary adder according to claim 8, wherein the adder is selected as follows. 10. A binary adder as claimed in claim 8, wherein each PROM is of a size such that no carry occurs therefrom depending on the addition accomplished with the binary signals applied thereto. 11 Each PROM is chosen to prevent carries from being generated according to the following equation: S≦2 ^q −1 where S is the sum represented by the PROM output binary signal; and q is the number of individual binary outputs available from the PROM.
Binary adder described in item 0. 12 The input binary signal to be added by the binary adder is a BCD bit representing a decimal BCD digit, and the selection of the size of each PROM is made in order to prevent carries from being generated therefrom. , the first claim takes into account that the BCD digits cannot exceed a value of 9.
Term, 2nd term, 3rd term, 7th term, 8th term, 9th term,
A binary adder according to any one of paragraphs 10 and 11.