JPS6219759B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument that has a plurality of musical tone generation sequences and can apply vibrato independently to each sequence, and particularly relates to an electronic musical instrument that has a plurality of musical tone generation sequences and can apply vibrato independently to each sequence. Regarding electronic musical instruments that have been removed. 2. Description of the Related Art Conventionally, there is an electronic musical instrument that has a plurality of musical tone generation sequences and is configured to independently impart a vibrato effect to the musical tones generated for each sequence. This electronic musical instrument is
A vibrato signal generator is provided for each series, and the musical tones in each series are frequency-modulated by a vibrato signal having an appropriate repetition frequency (vibrato frequency) generated from the vibrato signal generator. However, in the conventional electronic musical instruments mentioned above, there is no problem if the phases of the vibrato signals generated from each vibrato signal generator are exactly the same, but if the phases are shifted, the musical tones generated from each series will interfere with each other. The drawback is that it generates a humming sound that becomes unpleasant. This invention aims to eliminate the above-mentioned drawbacks. According to the present invention, when a vibrato signal generator of a certain series starts generating a vibrato signal from a vibrato signal generator of another series, the vibrato signal of the certain series ( The phase of the vibrato signal that has already been generated is forcibly synchronized with the phase of the vibrato signal of the other series (vibrato signal that will be generated later). The present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of an electronic musical instrument to which the present invention is applied, which has a plurality of musical tone generation series (musical tone signal generation sections) and can independently impart a vibrato effect to each series. It is. The solo musical tone signal generating section 100 of the first series generates a musical tone signal corresponding to the highest pressed key among the keys pressed on the keyboard, and the orchestral musical tone signal generating section 200 of the second series generates a musical tone signal corresponding to the highest pressed key among the keys pressed on the keyboard. Generates musical tone signals corresponding to all pressed keys. Musical tone signals generated from each series 100 and 200 are mixed by a mixing circuit 4 and sent to a sound system 5. Note that vibrato signals VBS1 and VBS2 generated from a vibrato signal generator 300 are added to each series 100 and 200, and these vibrato signals VBS1 and VBS2 independently produce a vibrato effect on each series 100 and 200. It is now possible to grant. The keyboard circuit 1 includes a plurality of key switches corresponding to the number n of keys on the keyboard, and when a key is pressed on the keyboard, the key switch corresponding to the pressed key is turned on. The key scanning circuit 2 receives a scanning clock pulse φ
Each key switch of the keyboard circuit 1 is sequentially and repeatedly scanned from the treble side to the bass side in accordance with the output of the counter 3 of the modulo n+1 that counts the number of keys. ”, and “0” when the key is released) to the time slot corresponding to each key, and outputs this as the key time-division signal KTDM, as well as a synchronization signal for each scanning cycle.
Output SY. FIG. 2 is a timing chart of the above signals KTDM and SY. As shown in FIG. 2c, the synchronizing signal SY is generated at the start of each scanning cycle, that is, each time the output of the counter 3 becomes "0" (see FIG. 2b), and its pulse width is determined by the counter 3.
The period coincides with the period of the scanning clock pulse φ (FIG. 2a) applied to the clock pulse φ. Also, the key time division signal
KTDM is “1” only in the time slot corresponding to the key being pressed, as shown in Figure 2d.
Each time slot corresponds to the period of the scanning clock pulse φ. In addition, the second
The key time division signal KTDM shown in FIG. d indicates that the second and fourth keys from the treble side are pressed on the keyboard. Synchronous signal SY output from key scanning circuit 2
is supplied to the solo tone signal generating section 100 and applied to the set terminal S of the flip-flop 102 provided in the highest note detection circuit 101.
is added to demultiplexer 104. In addition, the key time division signal output from the key scanning circuit 2
KTDM is added to the AND circuit 103 of the highest pitch detection circuit 101. First, when the synchronizing signal SY ("1") is output from the key scanning circuit 2 at the start of each scanning cycle, this synchronizing signal SY is applied to the set terminal S of the flip-flop 102, and the rise of the synchronizing signal SY causes the flip-flop to be turned off. 102 is set.
The set flip-flop 102 outputs a signal "1" from the output terminal Q to the AND circuit 103. AND circuit 103 inputs the key time division signal to other inputs.
KTDM and scanning clock pulse φ are applied, and the signal “1” is output from flip-flop 102.
When the key time division signal KTDM of "1" is added from the key scanning circuit 2, the signal "1" is output. This signal “1” is the demultiplexer 1
04 and flip-flop 1
It is applied to the reset terminal R of 02. The flip-flop 102 is reset by the fall of this signal "1", and the AND circuit 103 is thereby reset.
make it inoperable. Therefore, the AND circuit 103 outputs a signal "1" only when the input key time division signal KTDM becomes "1" for the first time, that is, only in the time slot of the highest pressed key. In addition, AND circuit 1
The reason why the scanning clock pulse φ is added as the AND condition in 03 is that if the key immediately below (on the bass side) the key pressed at the highest note is also pressed at the same time, the signal "1" will be output until the time slot of this pressed key. This is to prevent this from happening. The demultiplexer 104 has output lines (n lines) corresponding to each key, and the highest note detection circuit 1
Based on the signal applied from 01, the synchronizing signal SY, and the scanning clock pulse φ, a signal "1" is output only to the output line corresponding to the highest key pressed. The opening/closing signal 105 is transmitted to the tone generator 106
It includes a gate circuit that selectively opens and closes the sound source signal corresponding to each key output from the demultiplexer 104 according to the output of the demultiplexer 104.
The sound source signal corresponding to the output of 04 is selectively opened/closed and output. Here, the tone generator 106 is configured to frequency-divide the clock pulse oscillated from the master clock oscillator 107 and generate a sound source signal with a frequency corresponding to each key. Further, master clock oscillator 107 is a voltage-controlled oscillator, and its oscillation frequency is controlled in accordance with vibrato signal VBS1 applied from vibrato generator 300. Now, since the demultiplexer 104 is applying the signal "1" only to the output line corresponding to the highest note pressed key, the opening/closing circuit 105 selectively opens/closes only the sound source signal corresponding to this output line.
This is added to the tone circuit 108. The tone color circuit 108 adds a desired tone to the sound source signal and outputs it as a musical tone signal corresponding to the highest pressed key. This musical tone signal is applied to the sound system 5 via the mixing circuit 4, and is produced as a solo musical tone. In addition, the synchronization signal output from the key scanning circuit 2
SY and the key time division signal KTDM are applied to the demultiplexer 201 of the second musical tone signal generation sequence 200. Demultiplexer 201 has output lines (n lines) corresponding to each key, and distributes and controls the input key time division signal KTDM to each output line based on synchronization signal SY and scanning clock pulse φ. As a result, a signal "1" is generated on the output line of the demultiplexer 201 corresponding to the pressed key. The opening/closing circuit 202 is connected to the solo musical tone signal generating section 10.
Similar to the opening/closing circuit 105 provided in the tone generator 203, the circuit includes a gate circuit that selectively opens/closes the sound source signal corresponding to each key output from the tone generator 203 using the output of the demultiplexer 201. The corresponding sound source signal is selectively opened/closed and outputted accordingly. Note that the tone generator 203 and the master clock oscillator 204
are the tone generator 106 and master clock oscillator 107 of the solo tone signal generation section 100.
The master clock oscillator 204 also receives the above-mentioned vibrato signal VSB2.
is added. The sound source signal corresponding to each pressed key opened and closed by the opening/closing circuit 202 is applied to the tone circuit 205,
Here, a desired tone color is added and output as a musical tone signal corresponding to each pressed key. This musical tone signal is applied to a sound system 5 via a mixing circuit 4, and is produced as an orchestral musical tone. In addition, the synchronization signal output from the key scanning circuit 2
SY and key time division signal KTDM are applied to any key-on detection circuit 400. This new any key-on detection circuit 400 detects when a new key is pressed in a state where no key has been pressed on the keyboard, and sends a new any key-on signal.
Generate NAKON. The synchronizing signal SY output from the key scanning circuit 2 is applied to the AND circuit 403, and the flip-flops 401 and 40
2, and its rise resets the flip-flops 401 and 402. In addition, the key time division signal KTDM output from the key scanning circuit 2 is
The bits are added to the bit shift register 404 and sequentially shifted in synchronization with the scan clock pulse φ.
A NOR circuit 405 that takes a NOR condition for the contents of all stages of the shift register 404 applies a signal "1" to the AND circuit 403 when the contents of all stages are "0". The AND circuit 403 is enabled to operate by this signal "1", and when the synchronizing signal SY is added here, the synchronizing signal SY is applied to the set terminal S of the flip-flop 402. The flip-flop 402 is set by the fall of the synchronizing signal SY, and outputs the signal "1" from the output terminal Q to the AND circuit 40.
Add to 6. That is, when no key was pressed in the previous scan cycle, flip-flop 402 is set and AND circuit 406 is enabled. On the other hand, the flip-flop 401 receives the synchronizing signal SY.
The key time division signal is reset by the rising edge of
Set by the rise of KTDM. That is, when a key is pressed in each scan cycle, the flip-flop 401 applies a signal "1" to the AND circuit 406 from the time slot corresponding to the highest-pitched pressed key until the synchronization signal SY of the next scan cycle is generated. Therefore, when no key was pressed in the previous scan cycle, when a key is pressed in the current scan cycle, the AND circuit 406 selects the next time slot from the time slot corresponding to the highest note of the pressed key. Any key-on signal NAKON until the scanning cycle synchronization signal SY is generated.
Outputs (“1”). This new any key-on signal NAKON is applied to the vibrato signal generator 300. As shown in detail in FIG. 3, the vibrato signal generator 300 includes a solo-type normal vibrato/delay vibrato selection switch 301 and an orchestra-type normal vibrato/delay vibrato selection switch 302.
Vibrato signals VBS1 and VBS2 are generated depending on the operating states of switches 301 and 302. First, the case where the solo switch 301 is off will be described. In this case, the OR circuit 302 outputs a signal “0”, and this signal (“0”) is inverted by the inverter 303 and applied to the B input select terminal SB of the selector 304. This allows selector 3
04 is the signal (voltage (-
V/2)) and outputs it as the vibrato signal VBS1. This vibrato signal VBS1(-
V/2) is applied to the master clock oscillator 107 (FIG. 1), but since this signal VBS1 (-V/2) corresponds to the frequency modulation degree of "0" of the master clock oscillator 107, the signal VBS1 (-V/2) is applied to the master clock oscillator 107 (FIG. 1). The generated sound source signal has a regular musical tone frequency.
That is, no vibrato is added to the musical tone signal generated from the solo musical tone signal generating section 100. Next, a case will be described in which the movable contact piece 301a of the switch 301 is connected to the connection terminal 301b and solo type normal vibrato is selected. In this case, since the signal "1" is applied to the A input select terminal SA of the selector 304 via the OR circuit 302, the selector 304 selects the signal applied to the A input. Here, in order to explain the signal applied to the A input of the selector 304, the vibrato prohibition control circuit 305 and the waveform memory circuit 306 will be explained first. The vibrato prohibition control circuit 305 is a circuit for imparting a delay vibrato effect to a solo musical tone, and when the movable contact piece 301a of the switch 301 is connected to the connection terminal 301c, the any key-on detection circuit 400 (FIG. 1) The vibrato prohibition control signal VC1 of the signal "0" is output for a predetermined time (delay time) from when the new any key-on signal NAKON outputted from the rises to "1". Outputs prohibition control signal VC1. That is, when the movable contact piece 301a of the switch 301 is connected to the connection terminal 301c, the AND circuit 307 becomes operable. Here, when the new any key-on signal NAKON of "1" is output, this signal
Differentiator circuit 308 that takes the rising differential of NAKON
applies a reset pulse to the counter 309 of the vibrato inhibition control circuit 305 via the AND circuit 307. As a result, the AND circuit 310 that takes the AND condition for each bit output of the counter 309 is
A vibrato inhibition control signal VC1 of signal "0" is output. Signal VC1 output from AND circuit 310
(“0”) is inverted by the inverter 311 to enable the AND circuit 312 to operate. On the other hand, AND circuit 3
Since the clock pulse from oscillator 313 is applied to the other input of 12, AND circuit 312 applies this clock pulse to counter 309.
Counter 309 counts input clock pulses. When all the bit outputs of the counter 309 become "1", the AND circuit 310 outputs the signal VC1.
(“1”) is output. This signal VC1 (“1”) is inverted by an inverter 311 and sent to an AND circuit 312.
, and disables the AND circuit 312. That is, the AND circuit 310 (vibrato prohibition control circuit 305) outputs the vibrato prohibition control signal VC1 of signal "0" until each bit output of the counter 309 becomes "1" after the counter 309 is reset. Note that the delay time can be changed as appropriate by changing the frequency of the clock pulse generated by the oscillator 313. The waveform memory circuit 306 includes a resistor voltage divider circuit 314 in which a voltage division ratio corresponding to each sample point amplitude of a desired waveform is set, and a plurality of resistor voltage divider circuits 314 provided corresponding to each voltage division point of the resistor voltage divider circuit 314. FET (field effect transistor) gate 315. In this waveform memory circuit 306, the resistor voltage divider circuit 31
4, a half-cycle waveform of a symmetrical waveform such as a sine wave or a triangular wave is stored over 8 sample points from addresses 0 to 7, and one cycle of the symmetrical waveform is read out by folding back and reading out this half-cycle waveform. I have to. Both ends of the resistor voltage divider circuit 314 are connected to the FET gate 31
7,318 to the ground voltage and the reference voltage (-V), and is also connected to the resistive voltage divider circuit 314.
A voltage (-V/2) that is 1/2 of the reference voltage (-V), that is, a center voltage of the amplitude of the sine wave is applied to the midpoint 319 of the voltage. A FET gate 320 and a capacitor 321 are connected in parallel between the voltage division point corresponding to address 0 at the lower end of the resistor voltage divider circuit 314 and the midpoint 319, and the voltage division point corresponding to address 7 at the upper end and the midpoint 319 are connected in parallel. There is a FET gate 32 between the point 319 and
2 and a capacitor 323 are connected in parallel. When adding vibrato, gate 317
and 318 are turned on and a voltage (-V) is applied to the resistor voltage divider circuit 314 so that a sine wave signal appears on line 324. To inhibit vibrato, turn on the gates 320 and 322 to make both ends of the resistive voltage divider circuit 314 have the same potential (center voltage -V/2), so that a constant voltage (-V/2) appears on the line 324. do. Gates 317 and 318, 320 and 32
2 is turned on and off by the vibrato prohibition control signal VC1 supplied from the vibrato prohibition control circuit 305 described above. Address decoder 316 is FET gate 315
The count value of the address counter 325 is inputted as an address signal, and the gate opening/closing control signal is output in accordance with this address signal. When the vibrato prohibition control signal VC1 is "1", the address counter 325 outputs the vibrato frequency control oscillator 3.
The clock pulses oscillated from the address decoder 316 are inputted via the AND circuit 327, and the clock pulses are counted and the counted value is sent to the address decoder 316.
output as an address signal. The address decoder 316 outputs a gate opening/closing control signal to the FET gate 315 based on the address signal supplied from the address counter 325, and sequentially and repeatedly opens and closes each gate. As a result, the waveform memory circuit 306 supplies a sine wave signal of the center voltage (-V/2) to the line 324. Therefore, the movable contact piece 301 of the switch 301
When a is connected to the connection terminal 301b and solo-type normal vibrato is selected, the vibrato prohibition control signal VC1 remains at "1", so a sine wave signal is always output from the waveform memory circuit 306.
The selector 304 selects the sine wave signal applied to the A input and outputs it as a vibrato signal VBS1. This vibrato signal VBS1 is applied to master clock oscillator 107 (FIG. 1) and modulates the frequency of the clock pulses generated by oscillator 107. As a result, normal vibrato is added to the musical tone signal generated from the solo musical tone signal generating section 100. Next, a case will be described in which the movable contact piece 301a of the switch 301 is connected to the connection terminal 301c and a solo delay vibrato is selected. In this case as well, the signal "1" is applied to the A input select terminal SA of the selector 304 via the OR circuit 302, and the selector 304 selects the signal applied to the A input. Further, the AND circuit 307 becomes operational, and the output of the differentiating circuit 308 that takes the differentiation of the rising edge of the new any key-on signal NAKON is applied to the counter 309 of the vibrato prohibition control circuit 305. As a result, the vibrato prohibition control circuit 305 outputs the vibrato prohibition control signal VC1 of "0" for a predetermined period of time as described above (see FIG. 4a). This vibrato inhibition control signal VC1 (“0”)
makes the AND circuit 327 inoperative, and
It is inverted by an inverter 328 and applied to the reset terminal R of the address counter 325 via an OR circuit 329, thereby resetting the address counter 325. In addition, the vibrato inhibition control signal VC1
(“0”) is added to the waveform memory circuit 306 and the FET
The gates 317 and 318 are made non-conductive and the inverter 330 inverts the FET gate 32.
0,322 is turned on, and both ends of the resistor voltage divider circuit 314 are made to have an equal potential (center voltage -V/2). The signal appearing on line 324 is therefore a constant voltage signal (Figure 4b). When the vibrato inhibition control signal VC1 returns to "1" after a predetermined time, the address counter 325 starts counting and the FET gates 317 and 318 are turned on. However, because of the capacitors 321 and 323, the voltage across the resistor voltage divider circuit 314 does not rise to the reference voltage -V immediately, and the voltage between the resistor _R1 and the upper end of the resistor voltage divider circuit 314 and the midpoint 319 Combined resistance of resistors (parallel resistance value) and capacitor 3
21, the time constant determined by the resistor _R2 , the combined resistance (parallel resistance value) between the lower end of the resistor voltage divider circuit 314 and the midpoint 319, and the capacitor 323. stand up.
Therefore, as shown in FIG. 4b, the waveform memory circuit 30 generated immediately after the "vibrato prohibition time"
6 is given an envelope corresponding to the time constant. In addition, two capacitors 321 and 323 are connected to the center point 319 of the resistance voltage divider circuit 314.
(and a time constant circuit including resistors R ₁ and R ₂ ) is provided to give a symmetrical envelope to both amplitudes of the output signal of the waveform memory circuit 306. The signal supplied to the line 324 (a sine wave signal with a constant voltage (-V/2) for a predetermined time and then an envelope added according to the time constant) is supplied to the selector 3
The selector 304 outputs this as the vibrato signal VBS1. This vibrato signal VBS1 is applied to the master clock oscillator 107 (FIG. 1), and the frequency of the clock pulses oscillated from the oscillator 107 is changed to the master clock oscillator 107 (FIG. 1).
Modulate according to VBS1. As a result, a delay vibrato effect is imparted to the musical tone signal generated from the solo musical tone signal generating section 100. Next, the operating state of the orchestral switch 302 will be explained. The vibrato signal generator 300 generates the orchestral vibrato signal VBS2 in the same manner as the solo vibrato signal VBS1. That is, when the switch 302 is off, the OR circuit 331 outputs a signal "0", and this signal ("0") is inverted by the inverter 332 and applied to the B input select terminal SB of the selector 333.
The selector 333 selects the signal (voltage (-V/2)) applied to the B input and outputs it as a vibrato signal VBS2. Furthermore, when the movable contact piece 302a of the switch 302 is connected to the connection terminal 302b and orchestral normal vibrato is selected, the signal "1" is applied to the A input select terminal SA of the selector 333 via the OR circuit 331. , selector 333
selects the signal applied to the A input. Since the vibrato inhibition control circuit 334, address counter 335, address decoder 336, and waveform memory circuit 337 have the same configuration as that used to generate the solo vibrato signal VBS1, the waveform memory circuit 337 now has the center voltage A sine wave signal of (-V/2) is supplied to the A input of the selector 333. Therefore, the selector 333 selects the sine wave signal applied to the A input and converts it into the vibrato signal VBS.
Output as 2. Further, when the movable contact piece 302a of the switch 302 is connected to the connection terminal 302c and orchestral delay vibrato is selected, the AND circuit 3
38 becomes operational, the vibrato prohibition control circuit 334 outputs the new any key-on signal NAKON.
A vibrato prohibition control signal VC2 of "0" is applied to the waveform memory circuit 337 for a predetermined period of time in synchronization with the rising edge of the waveform memory circuit 337. As a result, the waveform memory circuit 33
7 is a constant voltage (-V/2) for a predetermined time, and then outputs a sine wave signal to which an envelope is applied according to a time constant circuit provided in the waveform memory circuit 337. On the other hand, the selector 333 selects the signal applied to the A input as described above, so the waveform memory circuit 3
The above signal output from 37 is used as a vibrato signal.
Output as VBS2. By the way, the above vibrato signals VBS1 and
When VBS2 is generated simultaneously, these signals VBS
1. The phase of VBS2 must be synchronized.
Table 1 summarizes situations where phase synchronization of vibrato signals VBS1 and VBS2 is required.

【table】

[Table] In each case shown in Table 1, according to the present invention, the already generated vibrato signal VBS1
Alternatively, the phase of VBS2 is synchronized with the phase of vibrato signal VBS2 or VBS1 generated later. In other words, in the case shown in Table 1, switch 3
When the movable contact piece 301a of 01 is connected to the connection terminal 301b, a signal "1" is applied to the connection terminal 301b, and the differentiation circuit 339 which takes the differential of the rising edge of this signal outputs a reset pulse. This reset pulse is applied to the reset terminal R of the address counter 325 via the OR circuit 329, and
It is applied to the reset terminal R of the address counter 335 via OR circuits 340 and 341, and resets the address counters 325 and 335, respectively.
As a result, the waveform memory circuit 3 outputs a waveform according to the count values of the address counters 325 and 335.
06,337 selector 3 selector 3 for sine wave signals of the same phase.
04,333, selector 304,333
outputs vibrato signals VBS1 and VBS2 of the same phase. It should be noted that an oscillator 32 applies a clock pulse to the count input T of the address counters 325 and 335.
No. 6,342 uses the same oscillation frequency. Further, for the above-mentioned reason, one oscillator may also be used. In the case shown in Table 1, when the movable contact piece 301a of the switch 301 is connected to the connection terminal 301c, the AND circuit 307 becomes operational, and the vibrato prohibition control signal VC1 is synchronized with the rise of the new any key-on signal NAKON. falls to "0". The signal VC1 (“0”) is sent to the AND circuit 32
7 is rendered inoperative, and is inverted by an inverter 328 and resets the address counter 325 via an OR circuit 329. After a predetermined period of time (vibrato prohibition time), when the signal VC1 (“0”) rises to “1”, the AND circuit 327 becomes operational, and the differentiating circuit 343 that takes the differential of the rising edge of the signal VC1 sends the reset pulse to the OR circuit 340. ，
341 to the reset terminal R of the address counter 335, and resets the address counter 335. As a result, the address counter 325,
335 both start counting from "0", and selectors 304 and 333 select vibrato signals VBS of the same phase.
1. Output VBS2. In the case shown in Table 1, as in the previous case, when the movable contact piece 302a of the switch 302 is connected to the connection terminal 302b, a signal "1" is applied to the connection terminal 302b, and the rising differential of this signal is taken. Differentiator circuit 344 outputs a reset pulse. This reset pulse is the OR circuit 345, 32
9 to the reset terminal R of the address counter 325, and also to the reset terminal R of the address counter 335 via the OR circuit 341, thereby resetting the address counters 325 and 335, respectively. In the case shown in Table 1, as in the case described above, when the movable contact piece 302a of the switch 302 is connected to the connection terminal 302c, the AND circuit 338 becomes operational, and a new any key-on signal is generated.
In synchronization with the rise of NAKON, the vibrato prohibition control signal VC2 falls to "0". Signal VC2
(“0”) disables the AND circuit 346 and is inverted by the inverter 347 and outputs the OR circuit 346.
1 to reset the address counter 335. After the specified time (vibrato prohibition time), the signal
When VC2 (“0”) rises to “1”, the AND circuit 346 becomes operational, and the differentiating circuit 348 that takes the differentiation of the rising edge of the signal VC2 resets the address counter 325 by sending a reset pulse via the OR circuits 345 and 329. In addition to terminal R, address counter 325 is reset. In the case shown in Table 1, for example, as shown in FIG. 4 a and c, the vibrato inhibition control signal VC
1. When the time when VC2 is “0” (vibrato prohibition time) is different, the vibrato signals VBS1 and
It becomes necessary to synchronize the phase of VBS2. In this case, the phases of the vibrato signals VBS1 and VBS2 are synchronized as described above by the rise of the vibrato prohibition control signal having the longer vibrato prohibition time. In this embodiment, the present invention was applied to an electronic musical instrument with a single keyboard, but a vibrato effect could be applied independently to musical tones corresponding to keys pressed on each keyboard with a two-level keyboard. This invention can also be applied to electronic musical instruments. Furthermore, the vibrato signal generator is not limited to the present invention, and may be one using a conventional CR oscillator or the like. As explained above, according to the present invention, even when vibrato effects are independently applied to musical tones generated from a plurality of musical tone generation sequences, the phases of vibrato signals for applying vibrato effects are synchronized. Therefore, generation of beat can be prevented.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of an electronic musical instrument to which the present invention is applied, Fig. 2 is a timing chart of various signals in Fig. 1, and Fig. 3 is a block diagram showing an embodiment of the main part of the invention. 4 is a timing chart of various signals in FIG. 3. DESCRIPTION OF SYMBOLS 1...Keyboard circuit, 2...Key scanning circuit, 3...Counter, 5...Sound system, 100...Solo musical tone signal generation section (first musical tone generation series), 200...Orchestra musical tone signal generation section (second musical tone generation system) generation sequence), 300... vibrato signal generator, 301...
Solo normal vibrato/delay vibrato selection switch, 302... Orchestral normal vibrato/delay vibrato selection switch,
304, 333... Selector, 305, 334... Vibrato inhibition control circuit, 306, 337... Waveform memory circuit, 316, 336... Address decoder,
325, 335...Address counter, 400...Any key-on detection circuit.

Claims (1)

[Scope of Claims] 1. In an electronic musical instrument having a plurality of musical tone generation sequences and having an independent vibrato signal generator for each sequence, when at least one vibrato signal generator operates, the other vibrato signal generators are activated. When starting the operation, the vibrato signal generator includes synchronization means for forcibly synchronizing the phase of the vibrato signal generated from the vibrato signal generator in operation with the phase of the vibrato signal generated from the other vibrato signal generator. electronic musical instrument. 2. The electronic musical instrument according to claim 1, wherein the vibrato signal generator starts operating a predetermined time after a key is pressed. 3. The electronic musical instrument according to claim 1, wherein the synchronization means resets the operation of the currently operating vibrato signal generator to an initial state in synchronization with the start of operation of the other vibrato signal generator. .