JPS6220486B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an encoder output device that outputs an angle signal in the form of a sufficiently accurate digital code. In such cases, two or more encoders are usually provided, of which, for example, the second encoder has the highest bit (hereinafter abbreviated as MSB) of the digital code output from the first encoder. The lowest bit of the code (LSB)
) are connected to represent the same angular unit. For example, when expressing an angle within 2π with a 14-bit binary digital code, the first encoder is
The second encoder outputs ^{a 4-bit digital code in which the MSB is the bit representing π and the LSB is the bit representing π/2 3 (} for example, the first encoder ^The axis of the second encoder is connected to a gear device in which the angle of the ^axis of Concatenate and read the encoder output
Obtain a 14-bit digital code where the MSB is the bit representing π. However, in such a case, a phenomenon occurs in which the change points of the output logics of the two encoders do not exactly match, depending on the accuracy of the encoder and the accuracy of the device that interconnects the encoders. In the above example using the first and second encoders, the first encoder output is logic "000, 1" and the output of the second encoder is logic "111, 111, 111, 11" with the MSB at the left end. ” and concatenated with “000,
111, 111, 111, 11”, then the second
The minute angle corresponding to 1 bit of the LSB of the encoder increases, and the angle read by connecting the first encoder and the second encoder becomes "001, 000,
000, 000, 00", this angle becomes "000, 000, 000,
However, the first encoder may not be able to accurately detect the increase in the minute angle, and the angle may remain as "000, 1". In this case, since the logic of the LSB of the first encoder and the logic of the MSB of the second encoder do not match, it is known that the display is incorrect, but this error cannot be corrected. In the device conventionally used for the above-mentioned error correction, the rotational tracks of the first encoder are doubled, and an angle corresponding to 1/4 of the LSB of the encoder is separated between the two tracks. Correction is made by setting the deviation and using the MSB of the second encoder to determine whether to use the output of the earlier track or the output of the later track among the dual tracks. Summer. However, the disadvantage of this device is that the rotating tracks must be doubled. In addition, in other conventionally used devices,
The output of the first encoder is mechanically shifted in one predetermined direction leading or lagging relative to the actual angle, and the logic of the LSB of the first encoder and the logic of the MSB of the second encoder do not match. In this case, the output of the first encoder is corrected based on the output of the second encoder, but the drawback of this device is that the output of the first
The point is that the output of the encoder must be mechanically shifted. The present invention eliminates the above-mentioned drawbacks of conventional devices and uses a plurality of encoders (each of which rotates at a different speed when the angle changes) to generate a high-resolution digital angle signal. (Let's call it a speed encoder)
An object of the present invention is to provide an encoder output device that can output error-free codes without finely adjusting the mechanical mounting accuracy of these multi-speed encoders. Embodiments of the invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a logic correction circuit, 2 is a one-shot multivibrator, 3 is an output register, 4 is an encoder output, of which 8 are the first encoder output,
9 is the second encoder output, the first encoder takes θ ₁ as MSB, θ ₁ represents the angle π, and θ ₁
The second encoder takes the sign of the binary 4 bits of ~θ ₄ as the MSB of θ ₄ ' which is the same digit as θ ₄ which is the LSB of the output of the first encoder, and therefore θ ₄ ' is the angle π/ 2 ³ and outputs an 11-bit binary code of θ ₄ ' to θ ₁₄ . 5 is a correction signal using the upper two bits θ ₄ ' and θ ₅ of the second encoder output 9, 6 is a clock pulse that determines the timing of input to the output register 3, and 7 is the output register 3.
, 10 is the data before correction, and 11 is the data after correction. FIG. 2 is a waveform diagram showing an example of the relationship between the first encoder output 8 and the second encoder output 9. The horizontal axis indicates the angle, and in the example shown in FIG. The case where the encoder output 9 of No. 2 is delayed is shown. That is, if the second encoder output 9 is correct, the correct form of the first encoder output 8 is as shown by the dotted line in FIG. In other words, the solid line 10 in FIG. 2 is the data before correction, and the dotted line 11 is the data after correction. As is clear from FIG. 2, in this digital code, when each bit changes from logic "1" to logic "0", the logic of the upper bit changes, and each bit changes from logic "0" to logic "0". At the time when the bit changes to "1", the logic of the upper bit does not change. From this, it is possible to determine the bit to be corrected when the LSB of the first decoder output 8 (θ ₄ in FIG. 2) does not match the MSB of the second decoder output 9 (θ ₄ ' in FIG. 2). can. Third
The figure is a waveform diagram showing the bits to be corrected in the first encoder output 8, and the shaded part in the figure is θ ₄ '≠ _θ4 , indicating the part with the bit to be corrected. However, there is no need to correct the part θ ₄ ′=θ ₄ , and to correct θ ₄ , use θ instead of θ ₄ .
Just output ₄ ′. A, B, C, and D in Fig. 3 show the case where θ ₄ '≠ θ ₄ exists at θ ₅ = "1" (θ ₄ is ahead of θ ₄ '), of which A is θ ₄ ' = "0" or θ ₄ is the place where the value changes from "0" to "1" and θ ₃
indicates the case where there is no change, B is θ ₅ = “1”,
θ ₄ ′ = “1”, θ ₃ = “1”, and θ ₄ is also θ ₃ for θ ₄ ′
also requires modification, but when _θ3 changes from “0” to “1”
Similarly, C requires correction of θ ₄ , θ ₃ , and θ ₂ , but _{θ 1 indicates} no change, and D indicates θ
₄ , θ ₃ , θ ₂ , and θ ₁ all require correction. Also, E, F, G, and H in Fig. 3 are θ ₄ ′≠θ ₄ , so θ
₅ = "0" (θ ₄ lags θ ₄ '), and E is F if only θ ₄ requires correction.
is θ ₄ , and if θ ₃ requires modification, G is θ
₄ , θ ₃ , θ ₂ need modification, then H is θ
₄ , θ ₃ , θ ₂ , and θ ₁ require modification. When FIG. 3 is expressed as a signal logic table, it becomes as shown in Table 1.

[Table] However, ₃ , ₂ , _{and 1} each represent a signal whose logic is inverted. The bit logic lines 1 to 8 shown in Table 1 correspond to Figure 3 A to H, respectively, and the 9th and 8th lines correspond to FIG.
Line 10 indicates a state where no modification is required. As is clear from Table 1, the bit patterns in each row, including the 9th and 10th rows, are distinct from each other. In addition, in Fig. 3, θ ₅
When θ 5 = "1", only the changing point on the right side (as viewed from the drawing) of θ ₄ was explained, and when θ ₅ = "0", only the left changing point of θ ₄ was explained. For example, when θ ₄ in FIG. 3A At the left side change point, the bit pattern of "θ ₅ θ ₄ 'θ ₄ " becomes "110", which is shown in Figure 3B,
It is the same as the right-hand side change point of C and D. Therefore, in this part, it is sufficient to perform the correction processing shown in the second _, third, and fourth rows of Table ₁ according to the bit patterns of θ 3 and θ 2. , and the bit pattern of "θ ₅ θ ₄ 'θ ₄ " at the left changing point of θ ₄ in FIGS. 3B, C, and D is "101", which is the same as the right changing point in FIG. 3A, Therefore, in this part θ ₃ , θ
₂ , the correction process shown in the first row of Table 1 may be performed. Similarly, for example, θ in FIG.
₄ , the bit pattern of "θ ₅ θ ₄ 'θ ₄ " becomes "001" and is shown in Figure 3 F, G, H.
Therefore, in this part, the correction processing shown in the 6th, 7th, and 8th rows of Table 1 can be performed according to the bit patterns of θ ₃ and θ ₂ . As mentioned above, the bit pattern "θ ₅ θ ₄ 'θ ₄ θ ₃ θ ₂ " does not go beyond the range described in the "Bit" column of Table 1, and there is no overlap among these 10 types of bit patterns. The corrected data is uniquely determined by this bit pattern. FIG. 4 is a circuit diagram showing an example of the logic correction circuit 1 shown in FIG. 1, in which the same symbols as in FIG. 1 indicate the same parts, 12 is an exclusive OR gate, 13 is a NAND gate, 14 is an inverter, and 15 is an AND gate. gate, 16 is multiplexer, 17 is lead
The lag switching signal H indicates a logic "HIGH" or logic "1" signal. The circuit in Figure 4 is configured according to the logic shown in Table 1, and the logic shown in Table 1 may be configured using circuits other than the circuit in Figure 4, so please refer to Figure 4 for details. Further explanation will be omitted. As shown in FIG. 1, among the first encoder outputs 8, θ ₁ , θ ₂ , and θ ₃ are corrected by the logic correction circuit 1, and the second encoder output 9 is input as is to the output register 3. This input point is controlled by clock pulse 6. clock pulse 6
is generated as soon as possible from the time when the logic of LSB θ ₁₄ of the second encoder output 9 changes in the one-shot multivibrator 2, but after a delay time sufficient for the operation in the logic correction circuit 1 to be completed. In the embodiment shown in FIG. 1, a case has been described in which the first encoder output 8 is 4 binary bits. 1st
Even if the encoder output 8 is 5 bits or more, it is easy to create a logic table like Table 1 and configure a logic circuit according to it, but it is easy to create a logic table like the one shown in Table 1 and configure a logic circuit accordingly. Corrections of 5 bits or more can be made. FIG. 5 is a block diagram showing another embodiment of the present invention, in which the same reference _numerals as in FIG _. 1 indicate the same or corresponding parts, and I _{a ,} . , and the LSB of I _a is the MSB of I _b (not shown in Figure 5 in the lower row of I _a ).
and the LSB of I _k is the MSB of I _l and the LSB of I _l is I _n
It shall be classified to match the MSB. I _o is the second encoder output 9 shown in FIG.
4 of I _n in the logic correction circuit 1 using the correction signal 5 taken from the upper two bits of I _o .
Modifying the bits is similar to that described with respect to FIG. Next, the top two corrected I _n
Modify the 4 bits of I _l using the modification signal taken from the bits. The corrected output is sequentially corrected in this way and is input to the output register 3 by the clock pulse 6. For example, the first encoder is
The MSB is θ ₁ bit representing π, and θ ₁ to _{θ 10} 2
The second encoder θ′ ₁₀ ~
If we output 10 binary bits of θ ₁₉ (θ _o = θ ₁₉ in Fig. 5), then I _a is θ
₁ , θ ₂ , θ ₃ , θ ₄ , I _b is θ ₄ ',
4 bits θ ₅ , θ ₆ , θ ₇ , I _c is θ ₇ ', θ
₈ , θ ₉ , θ ₁₀ , corrects I _c by θ ₁₀ ′, θ ₁₁ of the output of the second encoder, and corrects θ ₇ ′, θ ₈ of I _c after correction. I _b can be corrected by , I _a can be corrected by θ ₄ ′ and θ ₅ of I _b after correction, and the corrected values θ ₁ to θ ₁₉ can be input to the output register 3. Although the above has described an output device for obtaining a high-resolution digital angle signal using a multi-speed encoder, this invention is not limited to this, and is applicable to the control of mechanical systems with large gear ratios that are subtly affected by backlash, etc. It can be applied to the generation of control signals when digitally performing As described above, in the output device of the multi-speed encoder according to the present invention, the overlapping signal of the multi-speed section only needs to be 1 bit, and the absolute value of the error of the multi-speed overlapping section is calculated as one bit of the MSB of the second encoder output. If the resolution is kept within the bit resolution, there is an advantage that an arbitrary high-resolution angle signal can be obtained by connecting encoders in multiple stages.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the relationship between the first encoder output and the second encoder output, and FIG. 3 is a waveform diagram showing the relationship between the first encoder output and the second encoder output.
4 is a diagram showing an example of the logic correction circuit shown in FIG. 1, and FIG. 5 is a block diagram showing another embodiment of the present invention. be. In the figure, 1 is a logic correction circuit, 2 is a one-shot multivibrator, 3 is an output register, 4 is an encoder output, 5 is a correction signal, 6 is a clock pulse, 7 is the output of output register 3, and 8 is the first encoder output , 9 is the second encoder output, 1
0 is data before correction, 11 is data after correction, 12 is exclusive or gate, 13 is NAND gate, 14 is inverter, 15 is AND gate, 1
6 multiplexers, and 17 is a lead/lag switching signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first encoder that outputs a first binary digital code representing an angle, and a second encoder that represents the angle with the angular unit corresponding to the lowest bit of the first binary digital code as the highest bit. A second encoder that outputs a hexadecimal digital code, and inputs the upper two bits of the output of the second encoder and all bits of the output of the first encoder, and outputs the encoder to the first encoder according to the bit pattern of this input. a logic correction circuit that corrects and outputs the logic of each bit of the output of the encoder; a register that stores a third digital code obtained by connecting the output of the logic correction circuit and the output of the second encoder; and a clock generating circuit for generating a clock pulse for inputting the third digital code to the register after a predetermined delay time from the time of change of the lowest bit of the digital code.