JPS6221129B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program sequencer that effectively generates conditional branch addresses in microprograms and the like.

In general, microprograms often use a large number of conditional branch instructions. The conditional branch instruction in this case refers to an instruction that performs an operation and changes the execution sequence based on the result. Normal assembler instructions generally have a two-instruction format that executes an arithmetic instruction and then executes a conditional branch instruction in the next instruction cycle, but in microprograms with a large number of conditional branch instructions,
Various efforts have been made to execute an arithmetic instruction and a conditional branch instruction in one program instruction.

A typical n-way is to store program memory in n-way.
The program is divided so that n program instructions can be read at the same time, and the n program instructions can be freely selected. When determining the next program instruction to be executed, select one of n program instructions read at the same time depending on the result of the program instruction executed in the previous instruction cycle. good. This example is the first
In the figure, the one-way method that has traditionally been adopted and the n-
This is shown as a time chart for comparison with the way method.

The horizontal axis t indicates the time axis. First, in the conventional method shown in Figure 1-1, the instruction cycle for executing an arithmetic instruction is 500t, and the instruction cycle for a conditional branch instruction for determining the condition of the arithmetic result and branching is 501t.
If t, two instruction cycles of 500t+501t are required to execute a branch based on the operation result.

Next, by using the n-way method shown in 1-2 in the figure, it is assumed that the instruction cycle 500t for executing an operation is processed in the same time as the conventional method. However, after a time 502t for selecting the program instructions read simultaneously from the n-divided program memory, the next operation instruction 50 is selected.
Moving to 0t. As a result, when branching based on the calculation result, the conventional method requires 500t+50
It requires 1 t of time, and in the n-way method it becomes 500 t + 502 t, which is 500 t + 501 t.
>500t+502t is clear from the figure. However, in the n-way method, the programmer himself or herself divides the n-way branch addresses for the calculation result into n-divided program memory in advance.
It has the disadvantage that program instructions must be allocated, which places restrictions on instruction allocation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a program sequencer that can process program instructions at a high speed similar to a 2-way system and does not require consideration of allocation of program instructions to a program memory.

According to the present invention, a program memory that can access the memory by dividing the memory into an even address and an odd address for an address to which a program instruction is allocated, and two adders that generate respective execution addresses for the program memory; It consists of a multiplexer that selects the current execution address from the even address and the odd address for the next instruction cycle, an address register that stores the current execution address, and a selection circuit using a simple logic circuit.

In order to show the principle before explaining the embodiments of the present invention, n-
Among the way conditional branch instructions, 2-way (YES/
NO) is the most basic. In this case, if the program instruction has a displacement that determines the next execution address, the branch address can be either the current execution address + 1 address, the current execution address + the displacement address, or the current execution address There are two methods: address + displacement address or current execution address + displacement + 1 address.
If the program instruction has displacement, the above two methods are almost equivalent. Therefore, in the latter case, if the current execution address + displacement address is an even number, the current execution address + displacement + 1 address will always be an odd number, and if the former is an odd number, the latter will be an even number. You can see that it is a street address. Therefore, the program memory is divided in advance into two parts, one for even addresses and the other for odd addresses, to achieve this purpose.

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2 shows a general block diagram of one embodiment of a program sequencer according to the present invention. The program memory 4 is composed of the arithmetic unit 100, the decoder 200, the sequencer 300, the program memory 400, and the clock generator 500.
The program 400S stored in the clock generator 500 is decoded by the decoder 200, and various calculations are performed in the arithmetic unit 100 synchronously by the control signals 200S and 201S and the synchronization signal 500S from the clock generator 500. It is something that can be done. In addition, conditions based on the calculation results of the calculation device 100 (hereinafter referred to as flags and symbols are used. However, when the flag is OFF, it takes a value of 1, and when it is ON, it takes a value of 0). Controlled by 300, execution address 30
It is a device that points to the program memory 400 as OS. These arithmetic device 100 and decoder 200
The configuration and operation of clock generator 500 may be well known to those skilled in the art, and detailed description thereof will be omitted.

FIG. 3 is a block diagram illustrating the sequencer 300 and program memory 400 in detail as a first embodiment. First, logical values other than flags are taken as legitimate values, as an example, and are made to correspond to numerical signals of "0" and "1". The current execution address is “A” (A=2a+α) in the address register 340.
shall be. However, “a” is a positive integer “α” is “0”
or takes a value of “1”. ) as output signal 340S
Assume that it is output to .

At this time, the least significant bit of "A" is represented by "α" and is exclusive OR (hereinafter referred to as EX.OR) 350
The input signal 341S is assumed to be 341S. The displacement 202S in the instruction cycle when the current execution address is "A" is "B" (B = 2b + β. However, "b" is an integer, and "β" is a value of "0" or "1". ).
At this time, the least significant bit of "B" is represented by "β" and is the input signal 203S of EX.OR 350. Therefore, the input signal 340S of adders 310 and 320
The values of and 202S are "A" and "B", respectively. Also, the carry input signal 3 of the adder 310
50S is “αβ” (
indicates exclusive OR. ). Adder 320
The carry input signal 370S is an inversion circuit (hereinafter referred to as NOT) of the carry input signal 350S.
The signal via 370 is "". Therefore, the addition result 310S of the adder 310 at the current execution address is A+B+(αβ)=2a+α+2b+β+(αβ)=2(a+b)+α+β+(αβ). Therefore, "α+β+(αβ)" becomes an even number as shown in FIG. 4, and the addition result 310S is
Always an even number. Addition result 320 of adder 320
S is A+B+()=2a+α+2b+β+()=2(a+b)+α+β+(). Therefore, “α+β+()” is the fourth
As shown in the figure, it is an odd number, and the addition result 320S is always an odd number. Therefore, the program memory 41
For program instructions stored in 0,
For a program instruction stored in the program memory 420 at the address "A+B+(αβ)", the address "A+B+()" is accessed. Therefore, gates 430 and 44 with enable
0 enable control signals 360S and 450S
are "(αβ)" and "()". By these enable control signals, when flag 100S is OFF (=1), {[A+B+(αβ)]∧[αβ)]}∨{[A+B+()]∧[)]} ={[A+B+ (αβ)]∧()}∨{[A+B+()]∧(αβ)}=A+B, and when the flux 100S is ON (=0), {[A+B+(αβ)]∧[(αβ)]} ∨{[A+B+()]∧[()]} = {[A+B+(αβ)]∧(αβ)}∨{[A+B+()]∧()}=A+B+1. Note that ∧ indicates logical product, and ∨ indicates logical sum.
As a result, when flag 100S is determined,
The execution address in the next instruction cycle is always “A”.
+B" or "A+B+1". However, the program memory is 410 and 4
20, so the adders 310 and 3
20 addition results 310S and 320S are shifted by 1 bit and connected as shown in FIG.
O ₀ , O ₁ , ......, O _o , program memory 4
Each bit (n bits) at addresses 10 and 420
If M ₀ , M ₁ , ......, _Mo , connect so that O _o = M _o-1 (where n is a positive integer). ]
There is a need to. As a result, the address “A+B+(αβ)/2” is assigned to the program memory 410, and the address “A+B+(αβ)/2” is assigned to the program memory 420.
This means that the memory address "A+B+(αβ)/2" is being accessed.

At this time, the addition result 3 of adders 310 and 320
Select 10S or 320S by the output signal 360S of EX.OR360 (“(αβ)” “0”
A multiplexer 33 that selects the addition result 310S when it is "1" and selects the addition result 320S when it is "1"
0 generates the execution address of the next instruction cycle. Then, the execution address of the next instruction cycle is determined by the synchronization signal 500 from the clock generator 500.
set in address register 340 by S;
The next instruction cycle begins.

In FIG. 6, when reading a program 400S from a program memory 410 or 420, a block diagram showing a second embodiment is constructed using a multiplexer 460 in place of the enable gates 430 and 440 in FIG. It is a diagram.

In FIG. 7, an element that can perform chip enable control is used in the storage element itself constituting the program memory, and the enable gate 430 used in FIG. 3 or FIG. 6 is used.
440 or multiplexer 460, and is a block diagram showing a third embodiment in which the program 400S can be directly read. FIG. As a result of the above, conditional branch instructions can be used without considering the allocation of programs to program memory. In addition, there is no need to adopt a two-instruction format in which an arithmetic instruction is executed and a conditional branch instruction is executed in the next instruction cycle. Just add it after the instruction cycle that executed. This eliminates the need to use conditional branch instructions, which were used very often, and greatly speeds up program processing.

Also, as shown in FIG. 8, the address register 340
The output signal 340S of the multiplexer 380
By configuring the duder 200 to input other input signals (such as all bits "0") 204S and a selection signal 205S as input signals, it is possible to execute various sequence controls such as unconditional branching. FIG. 2 is a block diagram showing an embodiment of the invention.

All of these have very simple and regular circuit configurations, so they can be easily implemented as integrated circuits.

[Brief explanation of the drawing]

Figure 1 is a time chart showing the instruction cycle.
Fig. 2 is a block diagram of the entire embodiment of the program sequencer, Fig. 3 is a detailed block diagram of the first embodiment of the sequencer and program memory, Fig. 4 is a diagram showing the truth, and Fig. 5 is the diagram of Fig. 3. Fig. 6 is a detailed block diagram of the second embodiment of the sequencer and program memory, Fig. 7 is a detailed block diagram of the sequencer and program memory of the third embodiment, and Fig. 8 is a connection diagram of the adder and program memory. 2 is a detailed block diagram of a fourth embodiment of the sequencer and program memory; FIG. In the figure, 100... central processing unit, 200
……decoder. 300...Sequencer, 400...
...Program memory, 500...Clock generator, 310,320...Adder, 330,4
60...Multiplexer, 340...Address register, 350, 360...EX.OR, 370,
450...NOT, 410,420...Program memory, 430,440...3-S.gate, 1
00S~500S...Output signal of each device, 500
t to 502t... each instruction cycle is shown.

Claims (1)

[Claims] 1. A program that enables a conditional branch instruction in which a conditional branch address is determined to one of two consecutive branch addresses in a group of program instructions.In the sequencer, the above program instructions are divided into two, one at an even address and one at an odd address, and held. program memory and said 2
Two adders that generate the two branch addresses for the divided program memory, two program instructions of the divided program memory that are read by the outputs of the adders, and the next execution address. It consists of a selection circuit that selects depending on the branch condition, and an address register that holds the execution address.If the conditional branch address is two consecutive branch addresses, it is assigned to any program address, and is used during the operation to determine the condition. simultaneously reading two program instructions to be selected according to conditions from the program memory;
A program sequencer characterized in that as soon as a condition is determined based on an operation result, one of the two program instructions being read out is set as the next execution instruction.