JPS6221138B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a function macro that simulates the operation of a custom LSI.

Custom LSI ( Large Scale Integrated)
In order to respond to the era of circuits), custom
It goes without saying that a tool is needed to simulate the logical behavior of the entire system composed of LSI. This is because, unlike when a circuit is realized using a commercially available IC, errors in logic design appear as logic in the custom LSI, and cannot be easily corrected. CAD and PLA are conventional methods, but they have the following drawbacks. As a tool for simulating logical operations, 1
One can think of CAD (Computer Aided Design). The feature of CAD is that you can input the circuit configuration of a custom LSI.
It is possible to imitate the logical operation of However, on the other hand, when attempting to simulate the operation of an entire system composed of a large number of custom LSIs, a huge amount of computer time is required, making it unsuitable for practical use. Another method for simulating logical operations is to realize equivalent functionality using hardware, such as PLA (Programmadle Logic Array). Implementation using this hardware has the advantage of greatly shortening the time required to simulate logic operations, but on the other hand, when a change is made to the circuit, the PLA becomes unusable, and the configuration must be reconfigured with a new PLA. It has the disadvantage that there is

Under these circumstances, there is a need for a tool that has both the flexibility of CAD and the high speed of hardware implementation. An object of the present invention is to provide a function macro that simulates logical operations at high speed.

Function macros aim to facilitate correspondence with the circuit configuration of a custom LSI.The function macro divides the custom LSI circuit itself into several blocks and displays the input/output relationship of each block as a bit pattern. and written it into memory. In the function macro, the custom LSI logic is written into memory. Therefore, if a change occurs in the custom LSI, the change can be handled by rewriting the contents of the memory, and the logical operation of the custom LSI can be simulated by performing several memory accesses. It has the advantage of being able to

To simulate the logical operation of the entire system configured with custom LSIs, we store the state table for storing signal values at the input pins and output pins of each custom LSI, and the connection relationships between output pins and input pins between custom LSIs. This is done based on the connection table created and the event list for storing the custom LSI where a signal change occurred at the input pin.

The basic principle of conventional logic operation simulation systems for existing ICs is as follows. Pick up one IC registered in the event list and simulate the operation of that IC. That is, by calling a program that simulates the operation of this IC and executing it, the output of the IC is obtained. Next, check whether there is a change between the previous output and the output you just got, and if there is a change, replace the signal on the output pin with the one you just got.
Furthermore, it finds the IC and input pin to which the signal is propagated from the connection table, registers this IC in the event list, and replaces the signal of that input pin. This ends the simulation of the operation of one IC and moves on to the simulation of the operation of the next IC registered in the event list. This operation can be done from the event list.
This will continue until the IC runs out. After this, a new input is added to the system, thereby registering the new IC in the event list and restarting the operation simulation.

Function macros are a type of firmware designed to replace conventional programs that simulate IC operations. This can be expected to significantly shorten the simulation time.

A function macro has characteristics similar to macro instructions widely used in the software field. Custom LSI simulation is performed by calling a function macro. That is, there is one function macro for each type of custom LSI, and this function macro consists of several functions. The functions here are for each functional block when the custom LSI is divided into several functional blocks. A function macro has global data that is commonly used within the function macro and local data that is used as input to each function. When simulating a certain custom LSI, call the corresponding function macro and set the input data to this custom LSI in the global data section. The called function macro executes individual functions sequentially or in parallel, but before executing the function, input data necessary for executing this function is retrieved from the global data area provided for this function. to the local data area. The function produces an output based on this input, and this output is stored in a predetermined location in the global data area. This output will be used as input for the function to be executed later. Or it becomes the final output of a function macro. When all the functions constituting the function macro have been executed in this way, the execution of this function macro ends.
The execution result of this function macro can be obtained from the global data area.

How to divide a custom LSI into functional blocks is as follows.
Not uniform. The constraint conditions for dividing into functional blocks are the number of inputs and outputs allowed for each functional block. Now, it is assumed that up to 8 inputs and 1 output are allowed.

FIG. 1 is a circuit diagram showing an example of a 4-bit full adder. Let us consider this 4-bit full adder under the above constraints. One way to create functional blocks is to divide the circuit according to the signal propagation level. For example, the full adder shown in the figure is as follows. One NAND gate and one NOR gate, where the input signal undergoes conversion for the first time.
Nine functions are created here as one function block. Next, 19 functions are created by using each AND gate whose outputs undergo conversion as one functional block. Furthermore, these outputs are converted into NOR gates, and EOR gates are used as one functional block to create eight functions. Some of the functions created in this way have the same function, just the name of the input signal is different, so we will summarize them here. This is an example of dividing the circuit according to the signal propagation level. This method has the advantage of being easy to correspond to the circuit, but has the disadvantage of increasing the number of functional blocks.

Another method is to create as large a functional block as possible within the constraints and try to reduce the total number of functional blocks. For example, in the full adder shown in the figure, Σ1, Σ2, Σ3, Σ4, C
4, T1, T2, T3, T4, and T5 can be divided into functional blocks. The logical formulas for T1 and Σ4 are as follows.

T1=・1・1・2・2・3・3+2・2・3・3・1+1 +3・3・2+2+3+3 (1) Σ4=T14・4 (4+4) (2) These logical formulas are used as logic elements. The memory element is expanded as follows.

FIG. 2 is a block diagram in which equation (1) is realized using a memory element. It is assumed that the memory element of FIG. 2 has 16K addresses, and each address can store 1 bit of information.

FIG. 3 is a diagram showing the function of equation (1) using a truth table. Input signal CO, A1, B1, ..., A
By associating 3 and B3 with the address lines A0 to A6 of the memory element, the left side of the truth table can be regarded as an address, and the right side can be regarded as its contents.
Therefore, by writing the contents given in the truth table to each address of the memory element, Equation (1)
It is possible to realize the function of Further, the value of a function for a certain input can be obtained by applying that input to an address line and reading the contents of that address. Note that A8 to A15 are used to select a function.

In order to realize a function macro, it is necessary to realize the following functions using hardware. (1) A circuit for calling the functions included in the function array in sequence or in parallel when the function array is called, (2) Registers for global data, (3) Registers for local data, ( Four)
When a function is called, a circuit moves the data necessary for executing the function from the global data area to the local data area, (5) a memory element as a logic element that realizes the function, (6) the function A circuit for moving the output obtained as a result of execution to the global data area.

The function macro of the present invention is
A function specification part that sequentially generates the numbers of function sequences to be executed according to the LSI number, a status register for storing the input pins, output pins, and states of the custom LSI during processing, and the logic of the function block. an input register for storing the input data to the function part, an input selection part for transferring the state in the state register to the input register according to the function number, and an input register for storing the output of the function. It is composed of an output selection section that is stored in a status register.

The present invention will be explained in detail with reference to Examples.
FIG. 4 is a block diagram showing one embodiment of the function macro of the present invention. In the figure, 1 is a function designation section, 2 is a state register, 3 is a function section, 4 is an input register, 5 is an input selection section, and 6 is an output selection section. The function specification section 1 has a sequence of functions to be executed for each custom LSI, and when the custom LSI number is given from 7, the function section 3, input selection section 5,
The function numbers are sequentially output to the output selection unit 6 according to the execution order. The status register 2 is a register for global data, and stores the status of the input pin and output pin of the custom LSI given by 8, and also stores the output of the function section, that is, the status during processing. The function section 3 stores the logic of the function block, and outputs the value of the function for the data stored in the input register 4 when the function specifying section 1 gives the function number. input register 4
is a local data register that stores the data needed for the function you are about to execute. When the input selection section 5 obtains the number of the function to be executed from the function specification section 1, it transfers input data necessary for execution of the function from the status register 2 to the input register 4. The output selection section 6 includes the function specification section 1
When the number of the function to be executed is obtained, the function section waits for the value of that function to be output and transfers it to the status register 2.

Next, let's follow the movement of this function macro. Now, when trying to simulate a 4-bit full adder, the custom
Assume that the LSI number is given and the status register 2 is given inputs CO, A1, B1, . . . , A4, B4. At this time, for custom LSI simulation, Σ1, Σ2, Σ3,
In order to obtain T1, Σ4, T2, T3, T4, T5, and C4, it is necessary to sequentially execute 10 functions. Therefore, the function specifying unit 1 first performs Σ1
The number of the function for determining the value of is given to the function section 3, input selection section 5, and output selection section 6. In response to this, the input selection unit 5 sends CO, A1, and B1 necessary to obtain Σ1 from the status register 2 to the input register 4. The function unit 3 determines the value of Σ1 for the data currently stored in the input register 4 and outputs it. The output selection section 6 is the function section 3
The output of is transferred to status register 2. status register 2
The output selection unit 6 also specifies the storage location. When this is completed, the function specifying unit 1 generates a function number for determining the value of Σ2, and finally obtains this value in the status register 2 by the same process as just described. When all functions from Σ1 to C4 are executed, Σ1, Σ2, Σ3, Σ are stored in status register 2.
4, the value of C4 is stored. By applying this to the 8 side, the simulation of the 4-bit full adder is completed.

If the output data provided by the inspection specifications for the input data differs from the results obtained through simulation, an error exists in the logic of the custom LSI. In this case, correct the logic of the custom LSI, write the logic newly into the function section,
Run the simulation again. By continuing this debugging operation until the same output data as the inspection specification is obtained through simulation, and manufacturing the custom LSI only when the logic is correct, the man-hours and cost for manufacturing the custom LSI can be greatly reduced. can do.

Note that this function macro can be used as a custom
It can also be used for LSI failure detection, as a controller built into equipment, etc.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a 4-bit full adder, Fig. 2 is a block diagram of a memory element, Fig. 3 is a diagram showing a truth table in the memory element, and Fig. 4 is a block diagram of a funk of the present invention. FIG. 2 is a block diagram showing one embodiment of a macro. In the figure, 1 is a function command part;
2 is a state register, 3 is a function section, 4 is an input register, 5 is an input selection section, and 6 is an output selection section.

Claims (1)

[Claims] 1 In a function macro in a system that implements a given logical function, the specified
A function specification part that sequentially generates the numbers of function sequences to be executed according to the LSI number, a status register for storing the input pins, output pins, and states of the custom LSI during processing, and the logic of the function block. an input register for storing the input data to the function part, an input selection part for transferring the state in the state register to the input register according to the function number, and the output of the function. and an output selection section for storing the output in a status register.