JPS6221432B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording and reproducing apparatus that records signals such as video or audio at high density on a recording medium and reproduces the recorded signals.

2. Description of the Related Art Optical recording and reproducing apparatuses are known as recording and reproducing apparatuses that search for and reproduce a video or audio signal at a specific address from among a large number of video or audio signal information recorded on a recording medium by adding an address signal. This device converges a light beam generated from a light source onto a disc-shaped record carrier, records a video or audio signal concentrically or spirally on this record carrier, and writes the above on the track of the recorded signal. The position of the light beam is controlled, and a photodetector detects the reflected light reflected from the light beam or the transmitted light transmitted through the record carrier, and the signal is read. Generally, a He--Ne laser or a semiconductor laser is used as a light source, and images or video and audio signals are recorded on the recording carrier with unevenness or shading. The light beam is focused to about 1 .mu.m for high-density recording, with a signal track width of about 1 .mu.m and a track pitch of about 2 .mu.m. Focus control is performed to constantly irradiate the focused light beam onto the record carrier, and tracking control is performed to position the focused light beam on a track on the record carrier.

In the above-mentioned recording and reproducing apparatus, the address signal is output to the video or audio signal every rotation of the disk or continuously in synchronization with the vertical synchronization signal in the case of a video signal, and in synchronization with the rotational phase in the case of an audio signal. In addition, functions for recording, reproducing, and searching the track position at the desired location can be considered. However, in this case, if a dropout or the like occurs in the address signal portion during playback and an address is missing, the address will be read incorrectly and the desired search will not be possible.

The present invention provides a recording/reproducing apparatus that solves the above-mentioned problems, and will be described below along with embodiments thereof.

FIG. 1 shows a device that adds an address signal as binary information to a video signal during vertical blanking of the video signal and modulates and records the signal.The means for transforming the binary information before adding the address information is as follows. NRZ (Non Return to
Zero), PM (Phase Modulation), FM
(Frequency Modulation) is well known, but in this example, self-clocking is possible.
Use PM method.

1 is a terminal to which a video signal is input, 2 is a circuit for separating horizontal synchronizing signals, 3 is a counter, 4 is a circuit for separating vertical synchronizing signals, 5 is a decoder that generates pulses for 3 horizontal scanning sections, 6 is an address 7 is a parallel-in/serial-out type shift register; 8 is a clock generator;
9 is a monostable multivibrator, 10 is a pulse mixing circuit that prevents the generation of output only during the period when the output of monostable multivibrator 9 is generated, 11 is a flip-flop, and 12 is a mixer.

In Fig. 2, A is the video signal applied to terminal 1;
B is the vertical synchronization signal, C is the output of the decoder 5, D,
E is the output of the clock generator 8, F is the output of the shift register 7, G is the output of the monostable multivibrator 9, H is the output of the pulse mixing circuit 10, and I is the output of the flip-flop 11. Note that A, B, C
The time axes of and D to I are different from each other.

Next, the operation will be explained. A video signal A to be recorded is inputted from an input terminal 1, and a vertical synchronizing signal B is obtained via a separation circuit 4. On the other hand, the video signal A is separated by the separation circuit 2.
The horizontal synchronizing signal is separated and input to the counter 3. The horizontal synchronization signal input to the counter 3 is gated by the vertical synchronization signal B mentioned above, and is controlled to count the 3H section (1H is the horizontal synchronization signal interval, hereinafter abbreviated) immediately after the equivalent pulse after the vertical synchronization signal. . The output of the counter 3 is used by the decoder 5 to obtain a waveform C which is a positive pulse only in the 3H period mentioned above. Waveform C is used as a gate signal for recording the same address information about three times every 1H period during the 3H period in which the pulse is a positive pulse.
In addition, the address signal generator 6 generates address information in BCD.
(Binary Coded Decimal).

Now, suppose that one frame (two fields) of a video signal is recorded in one revolution of the disk-shaped record carrier, and if the straight shape of the disk-shaped record carrier is about 30 cm, the track pitch of the aforementioned light beam aperture will be about 2 μm. Approximately 50,000 frames can be recorded concentrically. For that purpose, if you give the address information in BCD, 20 bits
is also required. Furthermore, if you add "1010" or "1111", etc., which are not found in the BCD signal, to the beginning of the address information as an address identification signal, the address signal will be 24 in total.
Becomes a bit. 24 generated by the address signal generator 6
Bit address information is input to the shift register 7. The shift register 7 serially outputs data in response to the clock pulse train D generated by the clock generator 8, and outputs a waveform F. In order to input approximately 24-bit address information in the 1H section, the horizontal synchronization signal retrace period, etc. must be removed from the 1H section to approximately 50μ.
sec, one bit is about 2 μsec, and therefore the clock pulse train D is about 500 KHz. The shift register 7 is controlled by the gate pulse C described above so that the output F is output only during the 3H period, which is the positive period of the pulse C.

The clock pulse generator 8 generates a clock pulse train D.
A clock pulse train E having the same frequency but a phase difference of 180° is also output at the same time. This is done by selecting a fixed oscillator, such as the X-tal oscillator, at approximately 1MHz,
Pulse trains D and E can be easily obtained by triggering the rise and fall of the output using monostable multivibrators (not shown), respectively. On the other hand, the output F of the shift register 7 is input to a monostable multivibrator (hereinafter abbreviated as mono-multi) 9 which is triggered by the rise and fall of the signal, and as a result, an output G is obtained. The width of the output G of the monomulti 9 is selected to be smaller than the period of the clock pulse train D, but larger than 1/2 of that period. The pulse mixing circuit 10 mixes the positive pulse period pulse train E of the output G with the positive pulse waveform removed and the pulse train D to obtain a pulse train H. The first positive pulse of this pulse train H is removed and input to flip-flop 11, resulting in output I. This output I is mixed with the video signal A as an address signal in a mixer 12,
After each vertical synchronization signal, the same address is input to the modulator 13 in a superimposed form three times in the 3H interval, and then recorded on the disc-shaped record carrier.

To further describe the characteristics of signal I, when the same sign continues in the address signal, inversion is performed in the middle.

Next, a device for reproducing address signals will be explained. In Fig. 3, 14 is an input terminal to which the demodulated video signal is applied, 15 is a circuit that separates the horizontal synchronizing signal, 16 is a counter, 17 is a circuit that separates the vertical synchronizing signal, 18 is a decoder, and 19 is a clamp for the video signal. 20 is a monomulti, 21 is a clock pulse shaping circuit, and 22 is a block for obtaining address information. 23 is a serial/iso-parallel out type shift register, 24 is a detection circuit for detecting the first address, 25 is a flip-flop, and 26 is a flip-flop 25.
27 is a fixed oscillator, 28 is a 1/4 frequency dividing circuit, 29 is a memory for storing address information, 30 is a counter for counting the frequency-divided output, 31 is a decoder, and 32 is a microcomputer.

In FIG. 4, A is the output of the clamp circuit 19;
B is the output of the monomulti 20, C is the output of the shaping circuit 21, D is the output of the switching gate 26, E is the output of the detection circuit 24, F is the output of the frequency dividing circuit 28, and G is the reading command signal of the microcomputer 32. It is.

Next, the operation of this embodiment will be explained.

As mentioned above, the reflected light or transmitted light of the light beam irradiated onto the disc-shaped record carrier is detected by the photodetector to obtain a reproduced video signal, which is demodulated by the demodulator, and the obtained video signal is Connect to input terminal 14. As with the video signal during recording, the vertical synchronization signal separation circuit 17, the horizontal synchronization signal separation circuit 15, the counter 16, and the decoder 18 obtain a gate signal that is a positive pulse in the 3H period immediately after the equivalent pulse after the vertical synchronization signal. The detailed explanation will be omitted since it is exactly the same as that at the time of recording. With this gate signal, an address reproduction signal A similar to the signal during recording is obtained from the clamp circuit 19. This signal A is input to the monomulti 20, which is triggered by the rising and falling edges of the signal A, and is waveform-shaped into a signal B having a constant positive pulse width. The output width of the monomulti 20 is selected so that the positive pulse width of the signal B is smaller than the period of the clock pulse train mentioned at the time of recording, but larger than 1/2 of the period. Signal B is input to a clock pulse shaping circuit 21 to obtain signal C delayed by a certain period of time from the rising edge of signal B. This delay time is 1/1/2 of the period of the clock pulse train mentioned above.
Select it so that it is smaller than 2. If the information of the signal A at the timing of the clock pulse signal C is read out, it can be obtained as the address signal BCD signal.

The configuration described above is the basic configuration for recording and reproducing address signals. However, with this configuration, if part of the signal A is missing due to dropout or the like, the clock pulse signal C will be missing in that part, leading to erroneous reading of address information. In this embodiment, in order to eliminate this drawback, three identical address signals are recorded in each field to obtain six address information within one frame. , the address information of that 1 section is not adopted and the address information is searched for the next 1H section, and 3 or more of the 6 pieces of address information are obtained, this is imported into the microcomputer 32, and the majority decision is made. A determination is made to obtain address information. The structure for this purpose is block 22, which will be explained in detail below.

The shift register 23 transfers the address reproduction signal A, which is the serial data mentioned above, in accordance with the clock pulse signal C, and outputs it in parallel. The shift register 23 has 24 bits connected in series. This can be achieved by, for example, cascading three 8-bit parallel shift registers SN74164 (manufactured by Texas Instruments) in series. The output 4 bits of the final stage of the shift register 23 are input to the start address detection circuit 24. The address signal A is now transferred within the shift register 23 by the clock pulse signal C, but when 24 clock pulse signals C are input, the address identification signal ", which was explained at the time of recording, is written to the output 4 bits of the final stage of the shift register 23. 1010" or "1111" will be output.
Therefore, at this point, the output signal E is output to the head address detection circuit 24.

Now clock pulse signal C due to dropout etc.
If the number of pulses is missing and the number of pulses is less than 24, the address signal A cannot be transferred through the shift register 23 and no address identification signal is output to the output 4 bits of the final stage. Therefore, signal E is also not output. Furthermore, shift register 2
3 is cleared for each horizontal synchronization signal by the output of the separation circuit 15 described above. For this reason, for example, the clock pulse signal C is missing one from the normal number of 24, which is 23.
If the address identification signal is "1111", the output of the final stage of the shift register 23 will be "0111" and the transfer will be stopped. Therefore, signal E is never output.

When the signal E is output, that is, assuming there is no dropout, the address signal A stored in the shift register 23 is transferred at high speed until the next horizontal synchronization signal arrives, and is stored in the memory 29 as address information.
It is necessary to store it in Therefore, shift register 2
Transfer clock D of No. 3 is initially input with clock pulse signal C, and when signal E is output, fixed oscillator 2
It is switched by the switching gate 26 so that the output signal of No. 7 is inputted. Flip-flop 25 is set by signal E and reset by fixed oscillator 2.
The frequency of the 7 clock pulses is divided by the 1/4 frequency dividing circuit 28, and the frequency-divided output signal is counted by the counter 30 and then reset via the decoder 31.
That is, the reset was performed when 24 clock pulses from the fixed oscillator 27 were counted.

Here, the fixed oscillator 27 is a flip-flop 25
is gated to oscillate only when the output signal G of is a positive pulse. Therefore, the decoder 31 will generate a pulse if it counts 24 clock pulses from the fixed oscillator 27 when the signal E is generated every 1H period of the 3H period after the vertical synchronization signal mentioned above. The address signal A is generated by the clock pulse of the fixed oscillator 27.
is transferred and the address signal output in parallel from the final stage 4 bits of the shift register 23 is sent to the memory 29.
Enter data into.

The memory 29 may be, for example, SN7489 (manufactured by Texas Instruments), which is a non-destructive readable R/W memory with a 16 word x 4 bit configuration.

In this case, the timing of writing into the memory 29 is determined by the signal G obtained from the output of the fixed oscillator 27 via the 1/4 frequency dividing circuit 28. That is, the parallel output of the last stage 4 bits of the shift register 23 is written into the memory 29 every time 4 bits of the address signal A are transferred. Further, the write address of the memory 29 can be determined by counting the signal E using a 4-bit binary counter 30 and using this output as the write address.

Therefore, the 20-bit address signal A of the 1H section is stored in addresses 0 to 4 of the memory 29 as 4 bits x 5 words.

The 20-bit address signal A of the next 1H section is similarly stored at addresses 5 to 9. Here, the counter 30 is reset by the aforementioned separation circuit 17 every frame (every two fields). Therefore, when signal E is not generated due to dropout, etc., the address signal for that 1H section is ignored, and the address signal for the next 1H section is ignored.
The address of the section is subsequently stored in the memory 29,
In the end, of the six address information in two fields, three pieces of valid information are stored in the memory 29 at addresses 0 to 15.

The decoder 31 notifies the microcomputer (hereinafter abbreviated as microcomputer) 32 that the address information has been stored in the memory 29. As a result, the read command signal H is sent from the microcomputer 32 to the memory 2.
9, and three pieces of address information are taken into the microcomputer 32. Thereafter, the microcomputer performs a majority decision, and if two or more of the three data are the same, it is used as address information.

According to the embodiment, address data is stored in one frame6.
However, it goes without saying that the number of recorded address data should be as large as possible.

Further, although the case where the video signal is recorded concentrically has been described, the present invention is also applicable to the case where the video signal is recorded spirally. Furthermore, in the case of audio signals, it is clear that the present invention can be applied if the address signal is recorded in synchronization with the phase of the disc-shaped record carrier.

As is clear from the above embodiments, according to the present invention, the same address is recorded in each field in one frame, and the address is determined by excluding those pieces of address information that are missing due to dropouts, etc. For example, even if the address in the first field is affected by a dropout, the address information in the next field is located on the opposite side of the disk in the straight direction, so it is less likely to be affected by the same dropout, making it possible to read the address more accurately. It's convenient.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an address signal recording system of a recording/reproducing apparatus according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram thereof, FIG. 3 is a block diagram of an address signal reproducing system, and FIG. 4 is a block diagram of the signal. FIG. 6...Address signal generation unit, 23...Shift register, 29...Memory.

Claims (1)

[Claims] 1 Distinguish between a disk on which multiple address signals are written with a fixed number of bits including a leading identification code during one revolution of a concentric or spiral track, and a block of multiple address signals. means for counting clock pulses obtained based on the reproduced address signal for each output of the identifying means; coincidence detecting means for detecting a coincidence between the number of clock pulses and a fixed number of bits; code identification means for identifying the first identification code of A recording and reproducing device that detects address signals from signals by majority vote.