JPS6221442B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay automatic gain control circuit, in which a second AGC circuit, which operates on the output of a first gain control (hereinafter referred to as AGC) circuit, is connected to the output peak of the first AGC circuit. It consists of a circuit that extracts the difference between the peak value and the threshold value and detects the peak value, and it is stable with a high loop gain without fluctuations or decreases in the loop gain.
The purpose of this invention is to provide an AGC circuit that can extract AGC output.

FIG. 1 shows a block diagram of a general delay AGC circuit used in television receivers. In the figure, an RF signal that enters an input terminal 1 is amplified by a tuner (first amplification stage) 2 and an IF amplifier (second amplification stage) 3 to become an IF signal, and a detector 4
The signal is detected at the output terminal 5 and taken out from the output terminal 5. At this time, the IF AGC circuit 6 controls the gain of the IF amplifier 3 so that the peak value of the synchronization signal is constant, while the RF AGC circuit 7 operates when the output of the IF AGC circuit 6 exceeds a predetermined threshold. to control the gain of tuner 2.

FIG. 2 shows a conventional concrete block diagram of the IF AGC circuit and RF AGC circuit in FIG. 1. In this device, the peak value of the synchronization signal is detected by the error amplifier 8 and peak value detector 9 of the IF AGC circuit ₆₁ , and the gain control voltage for the IF amplifier 3 is extracted from the low-pass filter 10. The error amplifier 11 of the RF AGC circuit 7 ₁ compares the signal from the IF AGC circuit 6 ₁ with a predetermined threshold to obtain an error voltage, and the DC amplifier 12
A gain control voltage to the tuner 2 is taken out via the low-pass filter 13. However, in this case, the error amplifier 11 must be provided with a threshold value adjustment terminal, and the low-pass filter 10 must be provided with a filter capacitance terminal, so it is impossible to configure the device with a small number of pins.

Therefore, conventionally, there is a delay AGC circuit as shown in FIG. 3, which serves both as a threshold value adjustment terminal and a filter capacitance terminal. In this circuit, a level shift circuit 14 is provided in the IF AGC circuit ₆₂ , which is integrated with a low-pass filter 10', and is provided with a terminal for threshold value adjustment and a terminal for filter capacitance.

By the way, the input of the RF AGC circuit ₇₁ of this circuit is the output a of the peak value detector 9 of the IF AGC circuit ₆₂ .
(Fig. 4), it generally includes a ripple component, and a pulse output corresponding to the difference from the fixed threshold value b is taken out from the error amplifier 11' and sent to the DC amplifier 1.
2, a pulse output d as shown in FIG. 5 is taken out, averaged by a low-pass filter 13, and an output signal e as shown in FIG. 5 is taken out. Note that the signal a is level-shifted by the level shift circuit 14, averaged by the low-pass filter 10', and becomes the signal c.
and is supplied to the IF amplifier 3. However, if the pulse width of the output d of the DC amplifier 12 fluctuates like the output h, the output signal e will fluctuate accordingly, making it impossible to obtain an accurate AGC output.
Moreover, since the output e is an average of the pulse output d, only a low DC value can be obtained.

Therefore, in this conventional AGC circuit, the RF AGC loop gain fluctuates and decreases, and the RF AGC circuit does not operate sufficiently.On the other hand, in order to increase the RF AGC loop gain, it is necessary to You can increase the constant, but if you do this, AGC
There were drawbacks such as extremely slow response speed and inability to follow fluctuations in the RF signal entering the input terminal 1.

The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described below with reference to FIGS. 6 and 7.

FIG. 6 shows a block system diagram of an embodiment of the delay AGC circuit according to the present invention, and the same parts as in FIG. 3 are given the same numbers. This device is used by being connected to the circuit shown in FIG. 1, similar to the devices shown in FIGS. 2 and 3. IF AGC circuit ₆₂ shown in Fig. 6 is the first
The IF AGC circuit 6 in the figure and the RF AGC circuit 7 ₂ are the first
Each corresponds to the RF AGC circuit 7 shown in the figure. In FIG. 6, the low-pass filter 10' of the IF AGC circuit ₆₂ and the level shift circuit 14 are constructed as one unit, similar to the one in FIG. It is being
On the other hand, the RF AGC circuit ₇₂ is composed of an error amplifier 11', a peak value detector 15, and a low-pass filter 13, and forms the main part of the circuit of the present invention.

In _the same figure, an output signal a containing a ripple component as _shown in FIG. A pulse output corresponding to the difference from the fixed threshold value b is extracted from the amplifier 11' and supplied to the peak value detector 15. In the peak value detector 15, the peak value of the input pulse of the error amplifier 11' is detected, and the peak value detector 15 generates a signal shown in FIG. 7 which is proportional to the peak value of the output pulse of the error amplifier 11'. f is extracted. That is, since the peak value detector 15 detects the peak value of the output pulse of the error amplifier 11', the output of the peak value detector 15 is unrelated to the pulse width of the error amplifier 11'; It is not affected by pulse width variations.

The output f of the peak value detector 15 is passed through the low-pass filter 13.
The voltage is averaged and extracted as the RF AGC voltage g as shown in FIG. Since this voltage g is obtained by averaging the output f of the peak value detector 15, it can be extracted at a sufficiently higher level than the conventional RF AGC voltage e shown in FIG.
Loop gain can be kept sufficiently high.

As mentioned above, the delay AGC circuit according to the present invention is
An error circuit that extracts the difference between the peak value of the output of the first AGC circuit and the threshold value, which operates when the output of the first AGC circuit exceeds the threshold; It consists of a peak value detection circuit that detects the peak value, and a low-pass filter that removes unnecessary frequency components from the output of the circuit. When the output of the first AGC circuit exceeds the threshold value, the second AGC circuit is activated. The circuit operates to control the gain of the first amplification stage by obtaining a DC output from the second AGC circuit that is proportional to the difference between the peak value of the output of the first AGC circuit and the threshold value. Therefore, the output of the peak value detection circuit of the second AGC circuit is independent of the pulse width obtained by the difference between the output peak value of the first AGC circuit and the threshold value, and therefore, this pulse width Since the output of the second AGC circuit is obtained from the output of the peak value detection circuit, the output of the first AGC circuit is The output of the second AGC circuit is obtained by averaging the pulses obtained by the difference between the output peak value and the threshold value.It is possible to obtain a higher level than the conventional method, which obtains the output of the second AGC circuit, and the AGC loop gain is higher than that of the conventional method. It has the advantage of being able to obtain a sufficiently high value.

[Brief explanation of the drawing]

Figure 1 is a block system diagram when a general delay AGC circuit is applied to a television receiver, Figures 2 and 3 are block system diagrams of each example of a conventional delay AGC circuit, and Figure 4 is a conventional circuit. and a diagram showing the relationship between the output of the peak value detector and the threshold value of the IF AGC circuit in the circuit of the present invention, FIG. FIGS. 6 and 7 are block diagrams of an embodiment of the circuit of the present invention, and diagrams of the output waveforms of the peak value detector and the low-pass filter, respectively. 6, 6 ₂ ... IF AGC circuit, 7, 7 ₂ ... RF
AGC circuit, 8, 11'...Error amplifier, 9, 15
... Peak value detector, 10', 13 ... Low-pass filter, 14 ... Level shift circuit.

Claims (1)

[Claims] 1 comprising a first amplification stage, a second amplification stage and a detector connected in cascade, and first and second gain control circuits connected in cascade, the input signal being connected to the first amplification stage and the second amplification stage The output signal is amplified by the amplification stage, detected by the detector, and outputted. The output signal is supplied to the first gain control circuit, and the output of the first gain control circuit is used as the gain of the second amplification stage. and the second
In the automatic gain control circuit, the output of the gain control circuit controls the gain of the first amplification stage so that the level of the output signal is constant;
an error amplifier that extracts the difference between the peak value of the output of the first gain control circuit and a predetermined threshold; and a peak value detection circuit that detects the peak value of the output of the error amplifier. and a low-pass filter that removes unnecessary frequency components from the output of the peak detection circuit, and when the output of the first gain control circuit exceeds the threshold, the second gain control circuit operates. The second gain control circuit operates to obtain a DC output proportional to the difference between the peak value of the output of the first gain control circuit and the threshold value to control the gain of the first amplification stage. A delay automatic gain control circuit characterized by: