JPS62214595A - Nonvolatile memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a nonvolatile memory device, and particularly to an electrically rewritable ROM (EEPROM: Elec
trically and
Programmable Read 0nl
The present invention relates to a nonvolatile storage device that can prevent data loss due to power down during rewriting.

[Conventional technology]

EEFROM allows the user to decide the contents of the ROM,
It is also possible to write information, and it is also possible to erase and rewrite information. Non-volatile memory devices, some of which vary considerably in structure and operation, are typically used to store , 1 u, II O by allowing charge to and discharge from the floating gate.
A method is used in which H information is stored in correspondence with the magnitude of the threshold voltage of the MOS-FET.

In the conventional EEPROM, for example, Electronic Design August 23, 1984 issue, pages 197 to 204,
23.1984), the power supply voltage supplied to the device is automatically checked before write control, and if the voltage range is within which operation is possible.

It is designed to perform rewriting control.

[Problem that the invention seeks to solve]

In this way, in the conventional device, the power supply voltage is automatically checked first, and then rewriting is performed. However, although this method can handle a gradual power supply voltage drop with a small circuit scale, it cannot follow a sudden power supply drop after entering write control.
The information that should be written will be lost.

The purpose of the present invention is to improve such conventional problems and prevent data destruction of non-selected words that do not require rewriting during sudden power down during data rewriting, as well as prevent data destruction of selected words that are about to be rewritten. An object of the present invention is to provide a nonvolatile storage device that can be prevented from being destroyed.

[Means to solve the problem]

In order to achieve the above object, the nonvolatile memory device of the present invention includes means for recording a drop in power supply voltage, and a second group of nonvolatile memory elements that stores data to be rewritten when the power supply voltage drops, When a drop in the power supply voltage is detected, the voltage drop is recorded in the recording means, the data erasing operation to the first non-volatile memory element group is interrupted, and the first and second non-volatile memory elements are The feature is that the write data is started to be written to the memory element group.

[For production]

In the present invention, a backup EEFROM that is always in an erased state is provided, and when the 5'R source suddenly goes down, it can be written quickly, and a non-volatile flag is set to remember the power down during writing, so that the power can be restored. By checking the information of the non-volatile flag at the time of writing or the first time after the power is turned on, it is possible to determine whether the power has been turned down during writing and take appropriate measures. In addition, the EEPROM for writing and reading and the EEPROM for backup are mounted on the same board along with other control circuits, or on the same IC (LSI) chip as the processor that executes the user's job. By doing so, an easy-to-use and highly reliable nonvolatile storage device is realized.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to one drawing.

FIG. 1 is an overall block diagram of a non-volatile memory device according to an embodiment of the present invention.

In FIG. 1, IO is an EEPROM matrix, which is connected to a selector 12 for selecting a page, and when selected by the selector 12, an arbitrary word in the EEPROM matrix IO is selected. An address latch 14 that latches information on the address line 13 is connected to the decoder 11 and the selector 12.
The address information latched in the address latch 14 is decoded by the decoder 11 to determine the page to be selected. In addition, there is a column latch 18 for latching rewritten data to the EEPROM matrix 10, a data input/output circuit 20 for setting data to be written or read data, a data latch circuit 31 for latching written data, and a data latch circuit 31 for latching written data. a detection circuit 25 that detects and amplifies one word of data, a control latch circuit 29 that latches a control signal, a main power supply detection circuit 37 that detects a down state of the main power supply VCC, and a high voltage power supply VPP (for example,
A booster circuit 35 that generates +15V) and a control circuit 26 that controls the entire system are provided.

All of these circuits have been conventionally provided. In this embodiment, in addition to this, the backup EEPR
OM16 and non-volatile flag 17 are newly installed.

This backup EEPROM 16 has a capacity to store one page of data, and rewrite data is written there by the column latch 18 when the power is turned off. In addition, the non-volatile flag 17 is provided to record the fact that the power is down and take appropriate measures when the power is restored.
Here, a 1-bit capacity is provided to indicate two states, power-down and normal, but a 2-bit or more capacity may be provided to indicate the time to record the time from erase to power-down. can. Further, the capacity of the column latch 18 is the same as that of the page, and is a volatile memory. Data input/output to/from the outside of the storage device is performed from a data line 19 via a data input/output circuit 20 having a tri-state control function. To read data from the EEFROM matrix 10 to the outside of the device, if the information on the control signal line 21 is read information, decoding) jl
The data of the selected page 23 selected by l is input to the selector 12 via the bit line 24, and address information 1 is input to the selector 12 via the bit line 24.
After an arbitrary word is detected by the detection circuit 25 in accordance with 3, it is amplified and passed through the input/output circuit 20 controlled in the output direction by the input/output control signal 27 of the control circuit 26.
It is output to the data line 19.

Data in the EEFROM matrix 10 can be rewritten by supplying address information to the address information line 13, write information to the data line 19, and write information to the control signal line 21, thereby controlling the latch signal 28 from the control circuit 26. In synchronization with this, the control signal is latched into the control latch 29, and the write data is latched into the data latch 31 via the input/output circuit 20 controlled in the input direction and the input data line 30, and rewrite control is started. be done.

Data in the EEPROM matrix 10 is rewritten by erasing old data from the memory element and adding new data. Erasing means that the threshold voltage v of the memory element
th to a low level, this state is logic 11
It represents H14. Writing also means raising the threshold voltage Vth of the memory element to a high level, and this state represents logic II L 77.

Next, the rewriting sequence will be explained in detail.

When address data is given and writing is activated by the control signal 21, control is performed in the following order.

(b) Latch address, data, and control signals. (b) All bits of the memory information of the page 23 selected by the decoder 11 are transferred to the column latch 18 via the bit line 32.

(c) Data of the word to be rewritten (selected word) is transferred from the data latch 31 via the selector 12 to the column latch 18 via the bit line 33, and one word of data is updated. The content of non-selected words within the same page remains unchanged. (d) All bits of the contents of the selected page 23 are erased. That is, as memory logical information, IIH″′
give. (e) Transfer the contents of column latch 18 to bit line 3
EEPROM of page 23 selected via 4
Write to matrix 10 and finish rewriting.

The above control is executed sequentially according to the timing generated by the control circuit 26, but during the erasing operation (d) and writing operation (e), the memory element is operated for a long time (for example, 5 mS). It is necessary to apply a high voltage of approximately In this embodiment, a booster circuit 3 is provided in the storage device.
5 and high voltage VPP (+15V) from the main power supply VCC.
is generated and supplied to the EEPROM matrix 10. However, as mentioned above, since erasing and writing take a long time, if the power is cut off during this time, correct data will be lost not only in the selected word but also in non-selected words in the same page. In this embodiment, in order to prevent data loss due to power down,
During the erase operation (during the above-mentioned operation (d)), the main power supply detection circuit 37 always checks the Vcc level, and if a power down is detected, the information is transmitted to the control circuit 26 and the backup control is started immediately. is carried out.

The second @(&) is a logic circuit diagram of the timing generation circuit in the control circuit in FIG. 1, and (b) and (c) are operation timing charts during normal operation and power down, respectively. In FIG. 2(,), fl is a clock obtained by dividing the basic clock fo by a frequency divider 50, f2 is a clock obtained by further dividing fl by a 1/2 frequency divider 51, and f3 is a clock obtained by further dividing fl by a 1/2 frequency divider 51. A clock whose frequency is divided by a 1/2 frequency divider 52,
E/C is an enable signal for the timing generation circuit, 5 stones is a clear signal, PR is a write signal, and ER is an erase signal. As shown in FIG. 2(b), only while the enable signal is being generated, a clock f2 obtained by dividing the basic clock fo by 1/4 is generated, and is passed through an inverter to the AND circuit of the write signal PR and the erase signal. Send each to the AND circuit of ER. Since the II H1H level of tarlock f3, which is obtained by dividing the basic clock fo by 1/8, is input to both AND circuits, the period of rL L II of clock 2 becomes the write signal PR, and the period of H''' becomes the erase signal ER. During normal operation, the timing is as shown in (b). Alternatively, as shown in c), if a power down is detected at time tE during erasing, erasing is interrupted at one time tE, and
The clear signal σ is asserted 7 times to clear the 1 frequency dividers 50 and 51. Next, writing is started by negating CL. In this way, in this embodiment, new data is written by sending the write signal PR in a short period of time before the power is turned off.

FIG. 3 is a diagram showing specific data movement during erasing and writing in the present invention. Figure 3 (a) to (g)
, 18 is the column latch, 16 is the backup E
EPROM, 23 is an EEPR○M matrix selection page, and 17 is a non-volatile plug. Further, A represents the content of word 1 in the selection page 23, and B represents the content of word 2. Further, N is new data to be rewritten.

In FIG. 1, address information is input from the address line 13 and data is input from the data line 19, and the control signal gA21
When rewriting information is given to , under the control of the control circuit 26,
The address information, data, and control signals are each latched and operated in a first-order manner. That is, first, the third
Figure (a) shows the initial state layer of each circuit, and the EEP
The contents of the selected page 23 in the ROM matrix 10 are A in word 1 and B in word 2, the contents of the nonvolatile flag 17 and the backup EEPROM 16 are all II 1 '' (i.e., erased state), and the contents of the column The contents of the latch 18 are undefined. Next, as shown in FIG.
Now, in response to a rewrite instruction, the contents of the selected page 23 are sent to the column latch 18 via the data line 32 and copied. Next, in FIG. 3(c), the data latch 31 of FIG.
The data N to be written that is latched to the data line 3 is transferred to the data line 3.
3 to the column latch 18. In this embodiment, an example will be shown in which word 2 of the first selected page 23 is rewritten. That is, word 2 of column latch 18 is rewritten from B to N. Next, in FIG. 3Cd), the contents of the one-choice page 23 are erased. In other words, by being erased normally,
The data on the selected page is all "1". Figure 3 (e
), the contents of the column launch 18 are transferred to the selected page 23 via the data line 34, A of word 1 and N of word 2 are copied, and the normal write operation is completed.

FIGS. 3(f) and (g) are? ! ! This shows the contents of the operation when the power supply is down. That is, in FIG. 3(f),
If a power down is detected during erasing (d), first the erasing sequence is interrupted. , the selection page 23 of EEPROM7 tricks 10 contains all the contents of A and H.
Because the power went down while erasing to state 11,
It will be in a halfway erased state. Now, the incompletely erased state is represented by A' and B'. Also, the contents of the column latch 18 are A and N, and the contents of the non-volatile flag 17 are in the erased state II.
Continue at I 11 until the power is completely shut down. In addition, the contents of the backup EEPROM 16 will remain erased until the power is completely shut down.
hold.

In this embodiment, the contents of the column latch 18 are stored in the backup EEPROM 16 until the power supply is completely shut down.
and the selected page 23 at the same time, and 11011 is written in the nonvolatile flag 17 to record that the power has been turned down (see FIG. 3(g)). This completes the backup control operation. At this time, EEPRO
Regarding the unselected word (word l) in the selected page 23 of the M matrix 10, since the data A' being erased and the data A in the column latch 18 are the same data,
Data A is written to the selection page 23 in a short time, and normal data is saved. Selected word (word 2
) is the data B' being erased and the column latch 18.
Since the data N is different, the write result is indeterminate (II
(denoted by II).

FIG. 4 is a detailed fIII explanatory diagram of the write operation during power-down in FIG. 3.

As shown in Figure 3(f), at the time of power down,
The selected word of column latch 18 is N, and the selected word of selected page 23 of EEPROM matrix 23 is B'. The logical operation when writing N of the column latch 18 to the selected page 23 is an AND operation of N and B'. now,
As shown in (a), N of column latch 18 is “0011”
Assuming that B' of the selected page 23 = "0101", when N is written on B', the AND operation results in "0001" as shown in (b). This value is undefined. Also, as shown in (c), N=“001
1" and B="1111", the result of the AND operation is "0011", and normal writing is possible.

Also, as shown in (d), with N=”OOL t”,
Even when B' = "OO11", the result of the AND operation is "0011", and normal writing is possible. In this way, in the write operation when the power is down, normal writing is possible only when the value of the selected page 23 is "1111" or the same value as the value of the column latch 18, but otherwise the value is undefined. .

Therefore, for the unselected word (word 1), since the value of the column latch 18 and the value of the selected page 23 are the same value, normal writing is performed even when the power is turned off, and the correct value is maintained even after the power is turned off. left behind.

FIG. 5 is a flowchart of the operations of FIGS. 2 and 3.

First, when writing is started to rewrite data in the EEPROM matrix 10 from the outside (step 10
1) Under the control of the control circuit 26, the value of the selected page 23 of the EEPROM matrix 10 is saved in the column latch 18 (step 102). Next, the write data given from the outside is transferred to the column launch 18, The data of the selected word is updated (Sten': fi103).

Next, the contents of the selected page 23 are erased under the control of the control circuit 26 (step 104). At this time, if the main power detection circuit 37 does not detect 5 power downs (step 105), writing is executed to the selected page 23 and the data rewriting of the selected page 23 is completed (step E). When the power supply detection circuit 37 detects that the power supply is down, it interrupts the erase operation (step 107) and immediately erases the selected page 2 from the column latch 18.
3 and the backup EEPROM 16 (step 108). As a result, new data to be written is held in the backup EEPROM 16, and the normal value of the non-selected word is held in the one selected page 23. Note that the method and circuit for interrupting writing can be easily realized using conventional technology. Further, the nonvolatile storage device shown in Figure 1 can be mounted on one IC (or LSI), and it is also possible to mount this nonvolatile storage device on the same chip as the processor.

FIG. 6 is a block diagram when the nonvolatile storage device of the present invention is mounted on the same chip as a processor. In FIG. 6, 6I is a processor, and 62 is a memory (memory) for storing user programs and data executed by the processor 61.
63 is a memory (ROM) in which a control program such as an operating system for the processor 61 is stored.
), 64 is an EEPROM of the present invention, and 65 is an engineering/○ port. These circuits are connected to a common bus 66, and one of them occupies the bus 66 to exchange data with the other circuits or with the outside via the I10 port 65. VCC is the main power supply, VsS is the negative or zero voltage power supply,
CLK is a basic clock signal, and RESET is a reset control signal.

In this way, in this embodiment, after detecting a power down, by holding the voltage that enables operation for at least the time required for writing, data destruction of unselected words is prevented, and data destruction of selected words is prevented. An EEPROM that is also effective in preventing destruction can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, when the power supply voltage drops during erasing, data is written at high speed to the backup EEPROM that is always in the erased state, and furthermore, power abnormality is recorded in the nonvolatile flag. When the power is restored, this non-volatile flag can be checked and appropriate measures such as data recovery can be taken, thereby realizing a highly reliable non-volatile storage device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a nonvolatile memory device showing an embodiment of the present invention, FIG. 2 is a logic block and operation timing chart of the control circuit in FIG. 1, and FIG. 3 explains data changes in the present invention. 4 is a diagram explaining the detailed logical operation operation of FIG. 3, FIG. 5 is an operation flowchart of FIGS. 2 and 3, and FIG. 6 is an IC diagram showing an application example of the present invention.
(LSI) A block diagram on a chip. lO: nonvolatile memory matrix, 11: decoder,
12: Selector, 14 Near address latch, 16 EEPROM for backup, 17: Non-volatile flag, 18;
Column latch, 20: Data input/output circuit, 23: Selected page, 25: Selected word detection circuit, 26 Two control circuits, 2
9: Control latch, 35: Boost circuit, 31: Data latch, 37: Main power supply detection circuit. Patent applicant Hitachi, Ltd. Figure 1 Data to Figure 2 Figure 3 Figure 1 (a) (b) (c)
(a) (e) (f) n23 Figure 4 B:1111 [3:0011(C
I N:0011 (dl #+0
011ANDOOII ANDOOI
IFigure 6

Claims (1)

[Claims] 1. A nonvolatile storage device comprising a first electrically rewritable nonvolatile memory element group, in which data is rewritten to the nonvolatile memory element group by erasing old data and writing new data. The storage device has means for recording a drop in power supply voltage, and a second group of nonvolatile memory elements that stores data to be rewritten when the power supply voltage drops, and when a drop in power supply voltage is detected, the voltage recording the drop in the recording means, interrupting the data erasing operation to the first non-volatile memory element group, and starting writing of write data to the first and second non-volatile memory element groups; A nonvolatile storage device characterized by: 2. The nonvolatile memory device according to claim 1, wherein the first and second nonvolatile memory element groups are mounted on the same semiconductor substrate together with other control circuits. 3. The nonvolatile memory according to claim 1, wherein the first and second nonvolatile memory element groups are mounted on the same semiconductor substrate as the processor, together with other control circuits. Device.