JPS6221463B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a register control circuit used in a center polling type telemeter system.

In a center-polling type telemeter system, a central station sends a paging signal to a slave station belonging to the central station as necessary, and requests a response from the slave station. In such a system, the slave station must always be in a state where it can receive the paging signal sent from the central station, and after receiving the paging signal from the central station, the slave station responds to the central station.
When the response is completed, it is necessary to immediately return to the receiving state.

A commonly adopted method for realizing this operation is as shown in Figure 1.
The receiving circuit 4 of the slave station 3 receives a calling signal sent from the slave station via the transmission line 2, sets the register 5 in the slave station in response to the calling signal, and thereby activates the response circuit 6 in the slave station. The purpose is to reset the register 5 at the end of the response, thereby operating the receiving circuit 4 and making it ready to receive information. That is, whether the mobile station is receiving or responding is stored in the register 5, and the electronic circuit within the slave station 3 is switched depending on the state of the register 5.

In a center-polling type telemeter, the time the slave station waits to receive a paging signal from the central station is usually longer than the time it spends sending a response signal. Therefore, during this long waiting period, the register may malfunction due to external noise, etc., and there is a risk that the slave station may become responsive even though no paging signal is sent from the central station. There is.

An object of the present invention is to provide a register control circuit that is free from the risk of malfunction due to external noise as described above.

The present invention provides a circuit as shown in FIG.
An oscillator is provided, and the oscillation signal of this oscillator is supplied as a register set signal when a call signal exists, and is supplied as a register reset signal when a call signal is absent, and there is no connection between the register and the response circuit. The above object is achieved by providing a timer to activate the response circuit only when the register is set for more than a predetermined period of time which is longer than the period of the oscillator.

FIG. 2 shows an embodiment of the invention.

In FIG. 2, 7 is an oscillator, 8, 9 is an AND circuit, 10 is a timer, 11 is an AND circuit, 12 is an inverter, and other reference numbers indicate the same components as shown in FIG. .

Next, the operation of the circuit shown in FIG. 2 will be explained.

The slave station 3 supplies a reset signal to the register 5 via the AND circuit 9 at the cycle of the oscillator 7 while waiting for a paging signal from the central station 1, ie, without reception and without activation of the response circuit. When a paging signal is received from the central office and the oscillation signal from the oscillator 7 is supplied as a set signal to the register 5 via the AND circuit 8, the register 5 is set. When the register 5 is set, a start signal is supplied to the response circuit 6 via the AND circuit 11 after the timer 10 has expired, and at the same time, the transmission line 2 is connected to the reception circuit 4.
The response circuit 6 is then switched to the response circuit 6. When this response is completed, register 5 is reset.

Conversely, if the register 5 is set due to external noise while no paging signal is received from the central station 1, the time limit of the timer 10 is set sufficiently longer than the period of the oscillator 7. Before the time limit is reached, register 5 is reset and response circuit 6 is not activated.

As described above, according to the present invention, a control circuit is provided which can prevent erroneous setting or resetting of the register 5 due to external noise.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a register control circuit according to the prior art, and FIG. 2 is a diagram showing an embodiment of the present invention. 1: Central station, 3: Slave station, 4: Receiving circuit, 5: Register, 6: Response circuit, 7: Oscillator.

Claims (1)

[Claims] 1. In response to a paging signal sent from the central station to a slave station, a register is set, thereby activating a response circuit in the slave station, and when the response circuit finishes responding, the register is reset, thereby causing the In a register control circuit configured to enable a receiving circuit of a slave station to receive data, the register control circuit outputs an activation signal to the response circuit only during a period from when the register is connected to the register and the register is set for a predetermined period of time or more until the register is reset. an oscillator that outputs an oscillation signal with a cycle sufficiently shorter than the predetermined time; a first gate circuit that supplies the oscillation signal to the register as a set signal during the reception operation of the reception circuit; A second gate circuit that supplies the oscillation signal to the register as a reset signal during a period when the circuit is not in a receiving operation and the start signal is not output from the timer means. circuit.