JPS6222453B2 - - Google Patents
Info
- Publication number
- JPS6222453B2 JPS6222453B2 JP54007092A JP709279A JPS6222453B2 JP S6222453 B2 JPS6222453 B2 JP S6222453B2 JP 54007092 A JP54007092 A JP 54007092A JP 709279 A JP709279 A JP 709279A JP S6222453 B2 JPS6222453 B2 JP S6222453B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- interlayer insulating
- insulating film
- sog
- scribe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は多層配線構造を有するる半導体装置お
よびその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a multilayer wiring structure and a method for manufacturing the same.
多層配線構造を有する高密度集積回路等におい
ては、配線層間に形成された絶縁膜にスルーホー
ルを形成して配線層間の電気的接続がはかられ
る。 In high-density integrated circuits and the like having a multilayer wiring structure, electrical connections between the wiring layers are established by forming through holes in an insulating film formed between the wiring layers.
ところで、上記層間絶縁膜は通常CVD法によ
るSiO2膜あるいはPSG膜等によつて約8000Åの厚
さに形成されるが、配線層の上部と他の部分との
間に段差が生じているため、上記段差部分ではシ
ヤドウイング作用によりその上層に形成される配
線膜が非常に薄くなり、断線不良を発生する欠点
があつた。そこで、従来より、CVD法により層
間絶縁膜の形成工程前にSi（OH）4の低重合体溶
液等を回転塗布し、しかる後にベーキングを施し
て、いわゆるSOG（Spin on Glass）膜と称する
薄いSiO2膜を介在せしめ、このSOG膜により段
差をゆるやかにした後、前述のCVD法による層
間絶縁膜を形成する方法が採られてきた。第１図
は、このような多層膜構造を示すもので、半導体
基板１上のエピタキシヤル成長層１Ａ上には、熱
酸化SiO2膜２、１層目Al配線層３、SOG膜４及
び層間絶縁膜５が積層状に形成されている。 By the way, the interlayer insulating film mentioned above is usually formed with a thickness of about 8000 Å by using CVD method such as SiO 2 film or PSG film, but because there is a step between the upper part of the wiring layer and other parts. However, due to the shadowing effect in the stepped portion, the wiring film formed on the upper layer becomes extremely thin, resulting in a defective disconnection. Therefore, conventionally, before the step of forming an interlayer insulating film using the CVD method, a low polymer solution such as Si(OH) 4 is spin-coated, and then baking is performed to form a thin film called SOG (Spin on Glass). A method has been adopted in which a SiO 2 film is interposed, the SOG film is used to soften the step, and then an interlayer insulating film is formed by the aforementioned CVD method. FIG. 1 shows such a multilayer film structure. On an epitaxial growth layer 1A on a semiconductor substrate 1, a thermally oxidized SiO 2 film 2, a first Al wiring layer 3, an SOG film 4, and an interlayer The insulating film 5 is formed in a layered manner.
しかし、上述のSOG膜４は他の膜に比してエ
ツチング速度が高いため、スルーホール形成のた
めのホトエツチング時に、特にウエハ上のスクラ
イブ領域Ｓとアクテイブ領域Ａとの境界において
露出するSOG膜端面が深くサイドエツチされ、
この部分において層間絶縁膜５にはがれが生じた
り、エツチング液が残留して除々に配線層部まで
浸透したりする欠点があつた。さらに、第２図に
示すように層間絶縁膜５上にフアイナルパツシベ
ーシヨン膜６をCVD法で形成した後、スクライ
ブ領域Ｓを露呈させるようにホトエツチした場合
においても同様にSOG膜４がサイドエツチされ
上記層間絶縁膜５のはがれが一層広げられる欠点
もあつた。 However, since the above-mentioned SOG film 4 has a higher etching rate than other films, during photoetching for forming through holes, the edge surface of the SOG film exposed especially at the boundary between the scribe area S and the active area A on the wafer is removed. is deeply side-fucked,
In this area, the interlayer insulating film 5 may peel off, and the etching solution may remain and gradually penetrate into the wiring layer. Furthermore, as shown in FIG. 2, when the final passivation film 6 is formed on the interlayer insulating film 5 by the CVD method and then photo-etched to expose the scribe region S, the SOG film 4 is side-etched as well. However, there was also a drawback that the peeling of the interlayer insulating film 5 was further increased.
本発明は、上述の如き従来技術の欠点を解消し
た新規な半導体装置およびその製造方法を提供す
る目的でなされたものである。 The present invention has been made for the purpose of providing a novel semiconductor device and a method for manufacturing the same, which eliminates the drawbacks of the prior art as described above.
本発明の装置は、層間絶縁膜の周縁部がアクテ
イブ領域周縁部側面までを十分被覆するように、
スクライブ領域上まで残存せしめられてなること
を特徴とするものである。上述の如き本発明の装
置は、スルーホール形成時のホトレジストパター
ンを適宜調整することにより容易に得ることがで
きる。 In the device of the present invention, the peripheral edge of the interlayer insulating film sufficiently covers the side surface of the peripheral edge of the active region.
It is characterized in that it remains on the scribe area. The device of the present invention as described above can be easily obtained by appropriately adjusting the photoresist pattern when forming the through hole.
第３図は本発明の一実施例を示す要部断面図で
あり、基板１上のエピタキシヤル成長層１Ａ内に
複数個形成されたアクテイブ領域Ａとスクライブ
領域Ｓとの境界部を示したものである。即ち、基
板１の表面部分において、スクライブ領域Ｓはエ
ピタキシヤル成長部からなり、アクテイブ領域Ａ
は熱酸化SiO2膜２で覆われた拡散層が形成され
ている。第１層配線層３は上記熱酸化SiO2膜２
上に形成され、スルホール（図示せず）を介して
基板１上の素子（図示せず）と接続されている。
上述の配線層３上にSOG膜４およびCVDによる
PSG膜からなる層間絶縁膜５が形成されている。
この層間絶縁膜５に配線層３に達するスルーホー
ル（図示せず）を形成するのと同時のホトエツチ
ングによりスクライブ領域Ｓを露呈させるわけで
あるが、本発明においては、上記ホトエツチング
時にスクライブ領域Ｓ上に層間絶縁膜５の一部が
残存せしめられるようホトマスクパターンすなわ
ち、ホトレジストパターンを作成しておくことに
よつて図の如く、SOG膜４およびPSG膜５の周
縁部が、熱酸化SiO2膜２の周縁部側面を被覆し
た状態を維持する。かかる状態においては、スル
ーホール形成のホトエツチング時におけるSOG
膜４のサンドエツチは熱酸化膜２との段差部にお
いて完全に停止され、層間絶縁膜５のはがれがア
クテイブ領域Ａ上に大きく広がるのを効果的に防
止することが可能となる。 FIG. 3 is a sectional view of a main part showing an embodiment of the present invention, showing the boundary between a plurality of active regions A and scribe regions S formed in the epitaxial growth layer 1A on the substrate 1. It is. That is, in the surface portion of the substrate 1, the scribe region S consists of an epitaxial growth part, and the active region A
A diffusion layer covered with a thermally oxidized SiO 2 film 2 is formed. The first wiring layer 3 is the thermally oxidized SiO 2 film 2
It is formed on the substrate 1 and connected to elements (not shown) on the substrate 1 via through holes (not shown).
SOG film 4 and CVD film are formed on the above wiring layer 3.
An interlayer insulating film 5 made of a PSG film is formed.
The scribe region S is exposed by photoetching at the same time as forming a through hole (not shown) reaching the wiring layer 3 in the interlayer insulating film 5. In the present invention, the scribe region S is exposed during the photoetching. By preparing a photomask pattern, that is, a photoresist pattern, so that a part of the interlayer insulating film 5 remains, the peripheral edges of the SOG film 4 and the PSG film 5 are formed into a thermally oxidized SiO 2 film 2, as shown in the figure. Keep the peripheral side surfaces covered. In such a state, the SOG during photoetching for through hole formation is
The sand etch of the film 4 is completely stopped at the step between it and the thermal oxide film 2, making it possible to effectively prevent the peeling of the interlayer insulating film 5 from spreading significantly over the active region A.
このようなサイドエツチ防止効果は、第４図に
示すようにフアイナルパツシベーシヨン膜６を形
成した場合のホトエツチング時においても維持さ
れる。すなわち、パツシベーシヨン膜６のホトエ
ツチング時において、パツシベーシヨン膜６の周
縁部がスクライブ領域上にのびた層間絶縁５上に
重なるようなホトレジストパターンを形成してお
けばパツシベーシヨン膜６のホトエツチング時に
おける段差部でのサイドエツチングによるパター
ンのにじみも少なくなり、上記にじみがアクテイ
ブ領域Ａ上にまで広がることはほとんどなくな
る。また、この場合においては、スクライブ領域
Ｓに相当するエピタキシヤル層１Ａの表面レベル
からはかつた層間絶縁膜５の段差が膜５の厚さに
相当する8000Å程度になり、従来14000Åもあつ
たのに比べてほぼ半減する。このため、フアイナ
ルパツシベーシヨン膜６をCVD法で形成する際
にシヤドウイング形成される膜厚が減り、シヤド
ウイング部を除去するホツトエツチングが短時間
ですむため、一層サイドエツチ防止効果が大き
い。 Such a side etch prevention effect is maintained even during photoetching when the final passivation film 6 is formed as shown in FIG. In other words, if a photoresist pattern is formed such that the peripheral edge of the passivation film 6 overlaps the interlayer insulation 5 extending over the scribe area, the sides of the step portion during the photoetching of the passivation film 6 can be formed. The bleeding of the pattern due to etching is also reduced, and the bleeding hardly spreads to the active area A. In addition, in this case, the step of the interlayer insulating film 5 from the surface level of the epitaxial layer 1A corresponding to the scribe region S is about 8000 Å, which corresponds to the thickness of the film 5, compared to the conventional thickness of 14000 Å. This is almost halved compared to . Therefore, when the final patching film 6 is formed by the CVD method, the thickness of the film that is shadowed is reduced, and hot etching to remove the shadowed portion can be performed in a short time, so that the effect of preventing side etching is even greater.
以上述べた如く、本発明によれば、層間絶縁膜
下部のSOG膜のサイドエツチの進行を効果的に
防止することができ、層間絶縁膜のクラツクある
いははがれの発生、さらにSOG膜欠損部分にエ
ツチング液等が残存することによつて生ずる断線
等のさまざまの障害の発生を効果的に防止するこ
とができる。また副次的効果として、フアイナル
パツシベーシヨン膜のホトエツチング時における
サイドエツチによるにじみ不良の発生等も防止す
ることができる。 As described above, according to the present invention, it is possible to effectively prevent the progress of side etching of the SOG film below the interlayer insulating film, prevent cracking or peeling of the interlayer insulating film, and furthermore apply etching solution to the defective portions of the SOG film. It is possible to effectively prevent the occurrence of various failures such as wire breakage caused by remaining wires. As a side effect, it is also possible to prevent bleeding defects due to side etching during photoetching of the final packaging film.
第１図および第２図は従来法による半導体装置
のスクライブ領域断面図、第３図および第４図は
本発明の異なる実施例による半導体装置のスクラ
イブ領域断面図である。
Ａ……アクテイブ領域、Ｂ……スクライブ領
域、１……基板、２……熱酸化膜、３……第１層
配線層、４……SOG膜、５……層間絶縁膜、６
……フアイナルパツシベーシヨン膜。
1 and 2 are cross-sectional views of the scribe area of a semiconductor device according to the conventional method, and FIGS. 3 and 4 are cross-sectional views of the scribe area of a semiconductor device according to different embodiments of the present invention. A... Active area, B... Scribe area, 1... Substrate, 2... Thermal oxide film, 3... First layer wiring layer, 4... SOG film, 5... Interlayer insulating film, 6
... Final protection membrane.
Claims (1)
て、段差を有するように熱酸化SiO2膜をその半
導体基体表面に形成し、その熱酸化SiO2膜上お
よび段差部を覆うように層間絶縁膜としての
SOG膜およびPSG膜を順次形成し、そして上記
スクライブ領域上の上記PSG膜およびSOG膜を
選択的エツチングするにあたり、ホトレジストパ
ターンを、上記熱酸化SiO2膜の段差部を覆いス
クライブ領域上まで残在せしめるようにしたこと
を特徴とする半導体装置の製造方法。1. A thermally oxidized SiO 2 film is formed on the surface of the semiconductor substrate so as to have a step in the scribe region on the surface of the semiconductor substrate, and an interlayer insulating film is formed on the thermally oxidized SiO 2 film and to cover the step.
When sequentially forming an SOG film and a PSG film and selectively etching the PSG film and SOG film on the scribe area, a photoresist pattern is left over the scribe area to cover the stepped portion of the thermally oxidized SiO 2 film. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP709279A JPS5599743A (en) | 1979-01-26 | 1979-01-26 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP709279A JPS5599743A (en) | 1979-01-26 | 1979-01-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5599743A JPS5599743A (en) | 1980-07-30 |
| JPS6222453B2 true JPS6222453B2 (en) | 1987-05-18 |
Family
ID=11656429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP709279A Granted JPS5599743A (en) | 1979-01-26 | 1979-01-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5599743A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5348474A (en) * | 1976-10-15 | 1978-05-01 | Hitachi Ltd | Electronic parts |
-
1979
- 1979-01-26 JP JP709279A patent/JPS5599743A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5599743A (en) | 1980-07-30 |
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