JPS6222461B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to fast switching field effect transistors, and more particularly to junction gate field effect transistors.

Junction gate field effect transistor (hereinafter referred to as
FET) is a multiple carrier element, so
It has excellent high-speed performance, and its application to high-speed logic elements is being considered.

In general, power consumption and
Although there is a propagation delay time product (hereinafter abbreviated as P·tpd product), a waveform shaping effect is generally used as a method of reducing the input/output propagation delay time (hereinafter abbreviated as tpd). The waveform shaping effect requires the addition of an input voltage with an amplitude greater than the pinch-off voltage (hereinafter abbreviated as Vp) of the FET, and therefore, the more effectively this effect is utilized, the greater the voltage gain is required. Voltage gain is determined by the FET's mutual conductance (hereinafter abbreviated as gm) and load resistance, but the value of gm is uniquely determined at the time of element design. Therefore, a large load resistance is required to obtain a large voltage gain, but if its value is too large, it will degrade the output rise or fall time as well as the output capacitance of the FET, resulting in an increase in tpd. As can be seen from the above, there is an optimal load resistance value, but this optimal load resistance value is generally so large that the speed saturation region of the impurity carrier of the FET cannot be used effectively. This will be explained using FIG. 1. In the same figure
The drain current-voltage characteristics and load line of the FET are drawn. Straight line 1 represents the load straight line of the optimum load resistance value when a power supply voltage (hereinafter abbreviated as _VDD ) used in a normal logic circuit is used. Since the load line crosses a part where gm linearity is not good on the FET's current-voltage characteristics,
In the input/output characteristics, the deviation from the ideal state of the polygonal line characteristic becomes large, and this deviation adversely affects the tpd.

One possible way to avoid the above problem is to increase the power supply voltage and draw the load line 2.
This is not preferable because the P・tpd product becomes large, so
This is one of the reasons why they are not able to take full advantage of their inherent high speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed switching field effect transistor that eliminates the above-mentioned problems and has high speed and low power consumption.

According to the present invention, in a dual-gate field effect transistor, a first gate electrode and a second gate electrode are formed from the source electrode side between a pair of ohmic electrodes (a source electrode and a drain electrode) and the ohmic electrode. , a high-speed switching field effect characterized in that the thickness of the semiconductor active layer constituting the gate region where the second gate electrode is provided is made thinner than the thickness of the semiconductor active layer where the first gate electrode is provided. A transistor is obtained.

According to the present invention, the linearity of gm, which has been one of the factors hindering the reduction of tpd, is improved and tpd can be reduced. This will be explained using figures. Figure 2 shows the current-voltage characteristics drawn using the first gate voltage as a parameter under the condition that the second gate of the FET according to the present invention is kept at the same potential as the source, and also shows the load line 1 in Figure 1. There is. In FIG. 2, it can be seen that the nonlinearity of gm seen in FIG. 1, that is, the proportion of the load straight line passing through the ohmic region where gm is poor in current-voltage characteristics, has been improved. Furthermore, the resistance of the drain region can be reduced without impairing the linearity of gm, and as a result, the resistance of the FET in the ohmic region of current-voltage characteristics can be reduced. This means a reduction in the voltage when the FET is on, indicated by V _ON in FIG. 2, resulting in lower power consumption.

Furthermore, by reducing the contact resistance of the source and drain electrodes, the resistance of the FET in the ohmic region of the current-voltage characteristic can be reduced without impairing the linearity of gm _.
As a result, lower power consumption and higher reliability are achieved.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention.

In the figure, after a low impurity concentration semiconductor buffer layer 4 and a semiconductor active layer 5 are epitaxially grown on a semi-insulating substrate 3, the semiconductor active layer is etched away to a thickness corresponding to a required pinch-off voltage. Thereafter, the drain region of the semiconductor active layer is selectively etched again to a calculated value using a commonly used photolithography technique and removed using a calculation method described later. Furthermore, a window was opened using photo-etching technology, and Al was vapor-deposited.
A first gate electrode 6 and a second gate electrode 7 are provided by a lift-off method. AuGe,
Ni, Au, or AuGe, Pt, and Au are continuously deposited, and a source electrode 8 and a drain electrode 9 are provided by a lift-off method. Finally, heat treatment is performed at 420°C to obtain ohmic contact between the source and drain electrodes.

FIG. 2 is a sectional view showing a second embodiment of the invention.

The steps of forming the semi-insulating substrate 3, the low impurity concentration semiconductor buffer layer 4, and the semiconductor operating layer 5 can be carried out in the same manner as in the first embodiment of the invention, and will therefore be omitted.
Furthermore, a method of removing a portion of the semiconductor active layer 5 between the gate electrode and the drain electrode along the gate electrode or drain electrode is also possible by using a selective etching mask formed using photolithography. The semiconductor active layer may be selectively etched away to the desired thickness. The subsequent steps of forming the first gate electrode 6, second gate electrode 7, source electrode 8, and drain electrode 9 are also the same as in the first embodiment of the invention, and will therefore be omitted.

FIG. 3 is a sectional view showing a third embodiment of the present invention.

The steps of forming the semi-insulating substrate 3, the low impurity concentration semiconductor buffer layer 4, and the semiconductor active layer 5, and selectively etching and removing the drain region of the semiconductor active layer to a required thickness are the same as those of the first embodiment of the invention. Since it is the same as , it is omitted.

Thereafter, low resistance layers 10 are provided in the source and drain regions using ion implantation technology. Further, the subsequent steps of forming the first gate electrode 6, second gate electrode 7, source electrode 8, and drain electrode 9 may be performed in the same manner as in the first embodiment of the invention, and will therefore be omitted.

Up to now, the active layer impurity concentration is 1×10 ¹⁷ cm ^-3 , the buffer layer impurity concentration is 5×10 ¹³ cm ^-3 , and the gate length is 1 μ.
m, source-gate distance 2 μm, gate-drain distance 2 μm, gate width 100 μm, conventional structure GaAs shot barrier type FET with Vp 2.0V, V _DD 4V,
Input rise time under the condition of optimum load resistance value 500Ω
At 100ps, a TPD of 30ps was obtained. On the other hand, in the first embodiment of the present invention, the distance between the first gate and the second gate is 3 μm, and the distance between the second gate and drain is 3 μm, which is large, but the effect on the FET characteristics is negligible and the input/output characteristics are As a result of almost eliminating the deviation from linearity, we were able to reduce TPD by 12 ps, and furthermore, we were able to achieve a 31% reduction in power consumption when achieving the above switching speed with a conventionally structured FET.

Furthermore, in the second embodiment of the present invention, the thickness of the semiconductor layer in the drain region is made thicker than in the first embodiment, so that the conduction time can be increased without impairing the high-speed performance of the FET. The voltage applied across the FET can be reduced to 0.4V, compared to FETs with conventional structure.
A 35% reduction in power consumption was achieved.

Furthermore, in the third embodiment of the present invention, the source and drain regions are made of a low resistance layer, and the contact resistance between the source and drain electrodes can be reduced by providing the source and drain electrodes on the low resistance layer. , the operating speed has been improved from 30 ps to 16 ps in terms of propagation delay time compared to FETs with conventional structure, and
A 36% reduction in power consumption was achieved. Furthermore, by providing the low resistance layer, high reliability of the ohmic electrode can be expected. Although not shown, it goes without saying that the same thing may be applied to the source and drain regions in FIG.

As is clear from the above explanation, according to the present invention, by adjusting the thickness of the drain region in the active layer of the FET, the linearity of gm is improved.
Furthermore, it is possible to realize field effect transistors for high-speed logic elements with low power consumption and low propagation delay time.

Taking the case of a GaAs shot barrier gate field effect transistor as an example, a method for calculating the thickness of the drain region of the semiconductor active layer, which is necessary to implement the present invention, will now be described.

First, by applying Schottley's gradient approximation, the current-voltage characteristics in the low electric field region are determined by the following equation.

Here, e is charge, n is active layer impurity concentration, μ is mobility, a is active layer thickness, w is gate width, L ₁
is the length of the depletion layer, V _D1 is the voltage at the drain end of the depletion layer, and Vs is the voltage at the source end of the depletion layer. For simplicity, even if the calculation is performed assuming that L ₁ is the gate length, V _D1 is the drain voltage, and Vs is zero, almost no error will occur in the final result.

Next, the previous equation and i=e・n・μ・a・wEs(1−
p) are simultaneously solved to obtain the current value, and that value is designated as i _DSS . Here, Es is the value of the electric field that gives the carrier saturation velocity, and in the case of n-type GaAs, it is usually 3~
It is about 5KV/cm.

Furthermore, a load straight line of the external load resistance is drawn with V _DD as the starting point, and the current value at the intersection with the current-voltage characteristic is defined as _ID1 . Then, the required thickness of the drain region of the semiconductor operating layer is obtained from I _D1 /I _DSS ×a.

Since it takes time to perform the above calculation method strictly, in reality, the thickness is calculated using an appropriate approximation at any time, and the selective etching of the drain region of the semiconductor active layer is reduced to ensure safety. A practical method is to perform the final adjustment by applying a bias voltage to the second gate later.

[Brief explanation of the drawing]

Figure 1 shows the drain current-voltage characteristics of the FET with a conventional structure, and Figure 2 shows the drain current-voltage characteristics of the FET of the present invention. 1 shows the 500Ω load line when the power supply voltage is 4V, and 2 shows the case when the power supply voltage is 9V. 500Ω load line, V _ON is the load line 1 and the first gate bias voltage
Represents the voltage at the intersection with the drain current-voltage curve during OV. FIG. 3 is a sectional view showing the first embodiment of the invention, FIG. 4 is a sectional view showing the second embodiment of the invention, and FIG. 5 is a sectional view showing the third embodiment of the invention. In the figure, 3 is a semi-insulating substrate, 4 is a low impurity concentration semiconductor buffer layer, 5 is a semiconductor operating layer,
6 represents a first gate electrode, 7 represents a second gate electrode, 8 represents a source electrode, 9 represents a drain electrode, and 10 represents a high impurity concentration low resistance layer.

Claims (1)

[Claims] 1. A dual-gate field effect transistor in which a first gate electrode and a second gate electrode are formed from the source electrode side between a pair of ohmic electrodes (a source electrode and a drain electrode) and the ohmic electrodes. A high-speed switching electric field characterized in that the thickness of the semiconductor active layer constituting the gate region where the second gate electrode is provided is made thinner than the thickness of the semiconductor active layer where the first gate electrode is provided. effect transistor. 2. The high-speed switching electric field according to claim 1, wherein the thickness of the semiconductor active layer provided with the second gate electrode and the drain electrode is made thinner than the thickness of the semiconductor active layer provided with the first gate electrode and the source electrode. effect transistor. 3. The high-speed switching field effect transistor according to claim 1, wherein the thickness of only the semiconductor active layer in the gate region where the second gate electrode is provided is thinner than the thickness of the other semiconductor active layers. 4. Claim 1, in which the source electrode and the drain electrode are provided directly on the semiconductor active layer,
The high-speed switching field effect transistor according to items 2 and 3. 5. A high-speed switching field effect transistor according to claims 1, 2, and 3, wherein a low resistance semiconductor layer is provided in part or all of the semiconductor active layer in the source and drain regions.