JPS6223340B2 - - Google Patents

Description

[Detailed Description of the Invention] (A) Technical Field of the Invention The present invention provides a method for maintaining or adding individual input/output units in a common bus type device using a processor while the device is in operation. This relates to a connection method for individual input/output units that allows for

(B) Prior art and problems Conventionally, in devices using a processor equipped with an individual input/output unit (hereinafter abbreviated as I/O), the I/O is connected to a common bus of the processor, and the I/O When performing maintenance or expansion of a processor, it was customary to temporarily stop the processor and turn off the power.

FIG. 1 shows the configuration of a device to which a conventional processor equipped with I/O is applied. In the same figure,
1 is a processor (PRO), 2 is a common bus, 3 is a main memory, and 4 _-1 , 4 _-2 , . . . are I/Os. As seen in FIG. 1, each I/O 4 _-1 , 4 _-2 , ... is connected to a common bus 2, and data signals, address signals, and control signals are exchanged with the processor 1 via the common bus 2. sending and receiving. Therefore, if I/Os _{4 -1} , 4 _-2 , etc. are inserted or removed while the power is applied and the processor 1 is in an operating state, there is a risk that the electrical shock may adversely affect the operation of the processor. Therefore, when performing maintenance or expansion of I/O as described above, it is necessary to temporarily stop the processor and cut off the power supply.

In this way, with the conventional method, even a failure in one I/O unit requires the equipment to be stopped, which reduces the equipment's operating rate.Also, when changes such as expansions are made frequently, it is difficult to stop the equipment. There was the inconvenience of having to stop the device each time.

(C) Purpose of the Invention The present invention is intended to solve the problems of the prior art, and its purpose is to solve the problems of the prior art. To provide an I/O connection method that can not only prevent a single O failure from affecting the entire device, but also enable I/O exchange without stopping the device in the event of an I/O failure. There is a particular thing.

(D) Structure of the Invention The I/O connection method in the present invention consists of the following three items.

1. By physically separating the common bus of the processor and the I/O bus, various disturbances occurring on the I/O bus are prevented from spreading to the common bus.

2. By logically separating the common bus and the I/O bus, access to the I/O is temporarily prohibited during processor processing, so that the I/O becomes irrelevant to the processor's operation sequence.

3 I/O to bus while power is applied
Take electrical protection measures to prevent various elements from being destroyed even if the unit is inserted or removed.

Three of these items can be achieved by considering I/O unit circuit design, such as protective measures in circuit configuration, component selection, and transient characteristic suppression circuits using coils and capacitors. Since this is not an object of the present invention per se, it will not be described in detail.

(E) Examples of the invention Hereinafter, the present invention will be explained in detail based on examples.

FIG. 2 shows the configuration of an embodiment of the system of the present invention. In the same figure, the same parts as in FIG. 1 are indicated by the same numbers, and 5 is an I/O bus;
6 is an adapter (ADP).

In FIG. 2, each I/O 4 _-1 , 4 _-2 ,... is not directly connected to the common bus 2 of the processor 1;
It is connected to O bus 5. Common bus 2 and I/O
It is separated from the bus 5 and connected via an adapter 6. I/O4 connected to I/O bus 5
_-1 , _4-2 , ... are I/Os designed to allow the unit to be inserted and removed while the power is applied, as mentioned above.
This is a group of O units.

In addition, FIG. 3 shows the common bus 2 in FIG.
The configuration of the I/O bus 5 and adapter 6 is shown in detail. In the same figure, 2A, 2B, 2C
are an address bus, a data bus, and a control line, respectively, and these form a common bus 2. 5
A, 5B, and 5C are an address bus, a data bus, and a control line, respectively, and these are I/O bus 5.
It consists of Also, 6A and 6B are gates, 6C
is a control section, which constitutes the adapter 6.

In FIG. 3, the adapter 6 includes an address bus 2A as a common bus, an address bus 5A as an I/O bus,
The common bus data bus 2B and the I/O bus data bus 5B are separated by a gate 6A, and the I/O bus data bus 5B and the common bus data bus 2B are separated by a gate 6B. ing. These gates 6A, 6B are
Control signals from the common bus on control line 2C (read requests, write requests, etc.) and control signals from the I/O bus on control line 5C (I/O response signals, etc.)
and are turned on and off under the control of the control unit 6C, which relays the signals to the other bus.

FIG. 4 explains the configuration of the adapter related to the operation when reading data from I/O.
In the figure, 11 is a gate G, 12 is an amplifier, 1
3 is an OR gate, 14 is a selector, 15 is a gate G, and 16 is a timing monitoring circuit. Also the fourth
In the figure, the left side of the adapter shows a common bus, and the right side of the adapter shows an I/O bus.

When an I/O address to be read is generated from the processor via the address bus of the common bus and a read request signal is generated via the control line, the adapter sends these signals to the gate 11 and amplifier 12, respectively.
The data is directly relayed to the address bus and control line of the I/O bus via the I/O bus. In addition, when data is received from the I/O via the data bus of the I/O bus, and a response signal is also received via the control line, the adapter sends these via the selector 14 and gate 15, and the OR gate 13 to the respective data buses of the common bus. and is relayed directly to the control line.

The I/O for which the read request occurred was a failure or was not implemented.
If no response signal is sent to the I/O bus,
In the adapter, the timing monitoring circuit 16 monitors the time from the generation of a read request until the response signal is sent out, and if a response signal is not sent out after a certain period of time, the timing monitoring circuit 16 A pseudo response signal is generated and sent to the control line of the common bus via the OR gate 13. Furthermore, the I/O built in the selector 14
A pattern indicating a defect is sent to the data bus of the common bus via the gate 15, and a status signal indicating an I/O defect is sent from the timing monitoring circuit 16 to the control line of the common bus. A processor (not shown) monitors a status signal indicating an I/O failure sent via the common bus, recognizes that the sent data is defective due to this being sent, and discards the data. etc. Perform necessary processing.

Although the case of reading data from the I/O has been described above, similar processing is performed when writing data from the processor to the I/O.

According to the method described in FIGS. 3 and 4, even if there is no I/O that attempts to read or write, the processor can perform predetermined processing without being physically affected. Data processing can be performed according to a routine.

According to the above method, it is possible to perform maintenance while the I/O is active, but it is still not sufficient. For example, I/
If an attempt is made to remove the I/O while an access to O is occurring, disturbance to the bus will inevitably occur. Furthermore, even if it is possible to prevent element destruction due to active insertion/removal of an I/O unit, it is difficult to completely prevent disturbances caused by insertion/removal.

Therefore, in the method of the present invention, it is necessary to artificially
When inserting or removing the O unit, the adapter is provided with a bus isolation switch to temporarily disconnect the I/O bus from the common bus.

FIG. 5 illustrates the configuration of the adapter in relation to its operation when including a bus isolation switch. In the figure, 21 is a switch, 22 and 23 are AND gates, 24 and 25 are OR gates, and 26 is a timing monitoring circuit. Further, in FIG. 5, the left side of the adapter shows a common bus, and the right side of the adapter shows an I/O bus.

In FIG. 5, when the switch 21 is turned on, the I/O signal is input from the common bus via the AND gate 22.
A read request to the O bus is prohibited, and at the same time, a read request signal from the common bus is returned to the common bus as a response signal via an AND gate 23 and an OR gate 24. Also, since the status signal is sent to the common bus via the OR gate 25,
A processor (not shown) can recognize that reading has not been possible, and can perform processing in the case where the I/O unit is faulty or not installed in the same way as in the case of FIG. As in the case of FIG. 4, the timing monitoring circuit 26 sends a pseudo response signal to the common bus via the OR gate 24 when a response signal is not returned from the I/O even after a certain period of time has passed after sending the read request signal. Send out.

In FIG. 5, when switch 21 is turned on,
Access to all I//O connected to the adapter is interrupted, but normally for process I/O, etc., the access frequency is about once every few seconds, and for output units, data Therefore, if the switch-on time is shortened, no operational problems will occur.

(F) Effects of the Invention As explained above, according to the method of the present invention, in a device to which a processor with individual I/O is applied, a single failure of an individual I/O does not affect the entire device. In addition to preventing this, it is also possible to exchange I/O without stopping the device. Furthermore, if a program is created in advance, L/Os can be added without stopping the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a device applying a conventional processor equipped with I/O, FIG. 2 is a block diagram showing the configuration of an embodiment of the connection method of individual input/output units of the present invention, Figure 3 shows the common bus,
Figure 4 is a block diagram showing the detailed configuration of the I/O and adapter. Figure 4 is a block diagram showing the configuration of the adapter related to the operation when reading data from I/O. Figure 5 is a block diagram showing the configuration of the adapter related to the operation when reading data from I/O. FIG. 2 is a block diagram showing the configuration of an adapter related to operation. 1: Processor (PRO), 2: Common bus, 2
A: Address bus, 2B: Data bus, 2C: Control bus, 3: Main memory, _4-1 , _4-2 ,...: Individual input/output unit (I/O), 5: I/O bus,
5A: Address bus, 5B: Data bus, 5C:
Control line, 6: Adapter, 6A, 6B: Gate, 6
C: Control unit, 11: Gate G, 12: Amplifier, 1
3: OR gate, 14: Selector, 15: Gate G, 16: Timing monitoring circuit, 21: Switch, 22, 23: AND gate, 24, 25: OR gate, 26: Timing monitoring circuit.

Claims (1)

[Claims] 1. In a common bus type device using a processor, an individual bus is provided for connecting individual input/output units belonging to the processor, and a gate is provided to connect the individual bus and the common bus;
A control circuit for controlling on/off of the gate is provided, and the control circuit turns on the gate going from the common bus to the individual bus when a response request signal is generated from the common bus side, and turns on the gate going from the common bus to the individual bus when a response signal is generated from the individual bus side. Turn on the gate from the individual bus to the common bus, monitor the time from the generation of the response request signal on the common bus to the generation of the response signal on the individual bus, and output a pseudo response signal to the common bus if there is no response within a predetermined time. At the same time, a status signal and a specific pattern indicating an individual input/output unit abnormality are sent to the common bus side, a pseudo response signal is output to the common bus when the bus separation switch is operated, and a status signal indicating that the individual input/output unit is not operating is sent to the common bus side. A connection method for individual input/output units that is characterized by sending data to