JPS622334B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error recovery method for a logical device in an information processing system.

Conventionally, in multiprocessor systems, 1
If a logical device fails and cannot be recovered, in order to continue the process that was being executed on the failed logical device to another logical device, for example,
As with the data processing device described in the above publication, there is a drawback that a circuit for relief is required in an otherwise normal logic device.

An object of the present invention is to enable a faulty logic device to continue processing that was being executed in a faulty logic device without preparing a circuit for relief in other normal logic devices. The purpose is to provide a recovery method.

The method of the present invention provides an error recovery method for a logical device including a first logical device, a second logical device, and a main storage device commonly used by the two logical devices. The logical device has a storage means for storing a group of information for reading and executing instructions, and a stopping means for stopping execution of the instruction when a retryable error occurs and recovery within the own device is impossible;
and saving means for saving the information group stored in the storage means to the main storage device when the error occurs, and the second logical device saves the information group stored in the storage device to the main storage device, and the second logical device It is provided with an import means for importing the information group saved in the storage device.

Next, the present invention will be explained in detail with reference to the drawings. Referring to the figure, in one embodiment of the present invention, a central processing unit (hereinafter referred to as CPU) 1 that has detected an error
0, CPU20 and CPU10 take over the interrupted process
A programmable register group 130, a save register group 140 for saving information of these register groups 130, a data path 135 used for data transfer between the register group 130 and the save register group 140, a control line 111, and a control line. 112, an arithmetic circuit 110 that executes instructions using the register group 130, an error detection circuit 15 for the CPU 10;
0, a control line 152 and a control line 153 that transmit signals from this circuit 150, a retry control circuit 160 that controls whether or not recovery is possible in the event of an error, this circuit 16
A control line 161 and a control line 162 that transmit signals from 0, a main memory 30 that is shared by the CPU 10 and the CPU 20 and stores interruption information, and data used for data transfer between the main memory 30 and the save register group 140. path 145, an interruption control circuit 120 that controls interruption of processing of the CPU 10, this circuit 1;
The control line 121 transmits signals from the CPU 20 and the data path 245 takes interrupt information from the main memory 30 into the save register group 240 of the CPU 20.

Next, the operation of the present invention will be explained in detail step by step.

First, the operation in the normal state will be explained.
When a process A being executed by the CPU 10 needs to wait for the completion of an input/output operation by a peripheral device (not shown), the process A temporarily abandons the use of the logical device and responds to this abandonment. The CPU 10 saves the save information in the save register group 140 to the main memory 30 and enters an idle state. If there is another process B waiting to be executed, the CPU 10 that has become idle takes the interruption information of process B from the main memory 30 into the save register group 140 and starts executing process B. do. When the input/output operation in process A is completed, process A enters the execution waiting state, and the CPU 10 and CPU
20 is symmetrical and shares the main memory 30, it waits for an opportunity to be executed by the CPU 10 or CPU 20. After that, if the CPU 20 becomes idle first, the CPU 20 takes in the interruption information of the process A from the main memory 30 into the save register group 240, and resumes execution of the process A.

Next, the operation in the event of an error will be explained. now,
An error occurs in the CPU 10 and the error detection circuit 15
When an error is detected by 0, the error detection circuit 1
50 reports the error detection to the retry control circuit 160 and instructs the arithmetic circuit 110 to stop execution. The retry control circuit 160 checks whether the reported error can be retried, and if it is possible to retry, stores the information in the save register group 140 in the programmable register group 130, and then instructs the arithmetic circuit 110 to restart execution. multiply. When the situation does not recover even after a predetermined number of retries, or when retry is not possible, retry control circuit 160 requests interruption control circuit 120 to suspend processing. Upon receiving the interrupt request, the interrupt control circuit 120 saves the information in the save register group 140 to the main memory 30, and
Put the process that was being executed in 0 into a waiting state. At this time, since the arithmetic circuit 110 has not been activated to resume execution, it is unable to accept new processing. Therefore, the processing that was being executed by CPU 10 is different from the normal state, and the processing that was being executed by CPU 20 is
Wait for execution to resume. CPU20
And since the main memory 30 is normal, the CPU 20
When the CPU 20 becomes idle, the CPU 20 transfers data from the main memory 30 to the CPU 1, similar to the operation in the normal state.
The interruption information of the process being executed at 0 is taken into the save register group 240 and the process is taken over.

Since the CPU 10 and the CPU 20 are symmetrical, it is clear that if the CPU 20 fails, the CPU 10 will take over the processing. Furthermore, it is clear that the method of the present invention is applicable even when there are three or more CPUs. Further, this embodiment focuses on processing relief, and the method of the present invention is effective even if a means for notifying the occurrence of a failure is provided for resource management within the system.

The present invention has the advantage that when an unrecoverable error occurs, it is possible to perform recovery processing for a logic device while maintaining processing continuity without the need to provide a special rescue circuit for a normal logic device. There is.

[Brief explanation of the drawing]

The figure shows an embodiment of the present invention. In the figure, 10, 20... CPU, 30...
Main memory, 110, 210...Arithmetic circuit, 120,
220... Interruption control circuit, 130, 230... Program controllable register group, 140, 240...
...Saving register group, 150,250...Error detection circuit, 160,260...Retry control circuit, 1
15,135,145,215,235,245
...Data path, 111, 112, 113, 11
4,121,151,152,153,161,
162, 163, 211, 212, 213, 21
4,221,251,252,253,261,
262, 263...control line.

Claims (1)

[Scope of Claims] 1. An error recovery method for a logical device comprising a first logical device, a second logical device, and a main storage device commonly used by the two logical devices, comprising: The logic device 1 includes a storage means for storing a group of information for reading and executing instructions, a stopping means for stopping the execution of the instruction when a retryable error occurs and recovery is impossible within the own device, and a stop means for stopping the execution of the instruction when a retryable error occurs and recovery is impossible within the own device. and saving means for saving a group of information stored in the storage means to the main storage device by itself when an occurrence occurs, and the second logical device saves the information group stored in the storage device to the main storage device from the first logical device. 1. An error recovery method for a logical device, characterized by comprising a capture means for capturing a group of saved information.