JPS6223363B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic recording device used in an information processing device, and more particularly to an improvement in a read circuit for a high-speed, large-capacity magnetic disk device.

Conventionally, in the readout circuit of this type of magnetic recording device, a capacitor is inserted in series with the signal transmission line in order to remove the DC component of the readout signal. The time constant of the differentiating circuit formed by the CR circuit constituted by the capacitor and the input resistance of the circuit on the output side is set to be sufficiently large with respect to the period of the read signal.
On the other hand, if the read signal is superimposed with a transient response when switching from a write operation to a read operation or a transient response when switching heads, the capacitor is charged and a DC component is generated, which causes the subsequent readout to occur. This will adversely affect the operation of the circuit. That is, since the time constant of the differentiating circuit is set large, the discharging time is long, it takes time to remove the DC component of the signal transmission line, and it takes time for the readout circuit to work effectively.

The present invention improves this by making it possible to maintain a sufficiently large time constant with respect to the period of the readout signal at all times, and when a transient response occurs.
It is an object of the present invention to provide a circuit that can quickly remove DC components and obtain normal operation.

The present invention consists of a capacitor for removing DC components and an input resistor of a circuit connected immediately after the capacitor, which is used only when a transient response occurs such as when switching from a write operation to a read operation or when switching heads. A readout circuit capable of high-speed switching is provided by reducing the time constant and speeding up the removal of DC components.

That is, in a readout circuit equipped with a DC voltage removal circuit in which a capacitor is inserted in series with the readout signal transmission line and the output terminal of the capacitor is connected to the subsequent readout circuit, the voltage between the output terminal of the capacitor and the ground is It is characterized by comprising a circuit that switches the resistance value. The circuit that switches this resistance value is
A control signal covering the timing of switching from write operation to read operation and head switching is applied, and the resistance value switching circuit is configured to change the resistance value in response to the control signal. Thereby, the time constant formed between the capacitor and the capacitor can be changed.

The time constant of the DC voltage removal circuit, which takes into account the transmission characteristics of the read signal, slows down the convergence of the transient response, but when a transient response occurs, it is generally not necessary to guarantee the read signal, so the transmission characteristics must be By ignoring this, the time constant of the differentiating circuit can be made small, and the convergence of the transient response can be made faster.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the main block configuration of an embodiment of the present invention. In the figure, H ₁ , H ₂ , . . . , Hn are write/read heads, and both end lines thereof are connected to head drive circuits PA ₁ , PA ₂ , . . . , PAn, respectively.
The outputs a of the head drive circuits PA ₁ , PA ₂ , ......, PAn are connected in common, and the transistors
Given on the basis of Q ₁ and Q ₂ . resistance
R ₁ and R ₂ are bias resistors inserted between the bases of transistors Q ₁ and Q ₂ and ground. The collectors of transistors _Q1 and _Q2 are connected to the positive power supply voltage +V, and the emitters are connected to the negative power supply voltage -V through resistors _R3 and _R4 . Transistor Q ₁
or the emitter of Q ₂ is capacitor C ₁ respectively
or connected to the input of readout amplifier _A1 through _C2 . Its output signal h is connected to the subsequent circuit.

Signal b is the input signal of amplifier _A1 . The output terminals of the capacitors C ₁ and C ₂ are grounded through resistors R ₅ and R ₆ and connected to the drains of field effect transistors Q ₃ and Q ₄ through resistors R ₇ and R ₈ . The sources of field effect transistors Q ₃ and Q ₄ are grounded. The signals d ₁ , d ₂ , . . . , d _o are selection signals for the head drive circuits PA ₁ , PA ₂ , . . . , PAn, and are supplied from the outside. The signal g is write information and is applied to the converter T from the outside, and its output is connected to the output terminals of the head drive circuits PA ₁ , PA ₂ , . . . , PAn.

Signal c is a read and write control signal given from the outside, and is located between the midpoints of heads H ₁ , H ₂ , ......, Hn, and the head drive circuits PA ₁ , PA ₂ , ......, PAn.
and is supplied to the converter T. The signal e is d ₁ ,
This is a control signal that covers switching of the signals d ₂ , ..., d _o and c, and is supplied to the level converter L from the outside. Output f of level converter L
is connected to the gates of transistors Q ₃ and Q ₄ and turns on transistors Q ₃ and Q ₄ when signal e is valid.

Signal c indicates a write operation at high level and read operation at low level, and signals d ₁ , d ₂ , ......, d _o , e
is valid at high level. Also, the head drive circuit
PA ₁ , PA ₂ , ......, PAn are phase-directional circuits, and when they are selected by the signals d ₁ , d ₂ , ......, d _o , and the signal c is at low level, each head
The read signals of H ₁ , H ₂ , ......, Hn are amplified and output, and when the signal c is at a high level, the write information received at the output terminal is converted into a current and the read signals of the heads H ₁ , Hn are amplified and output.
Flow into H ₂ , ......, Hn. If not selected, the output terminal will be in an open state. The converter T is also driven when the signal c is at a high level, and when the signal c is at a low level, the output is in an open state.

Next, the operation of the above-mentioned circuit will be explained with reference to the time chart shown in FIG. FIGS. 2a to 2h are waveform diagrams of points with corresponding symbols shown in FIG. 1.
Further, in FIG. 2, states (1), (2), and (4) are read operations, and state (3) is a write operation. In state (1), the signal _d2 is at a high level and the head drive circuit _PA2 is driven, and the other head drive circuits PA1 _, PAn, etc. are not driven. In states (2), (3), and (4), the head drive circuit _PA1 is driven and the others are not driven. When the state changes from (1) to (2), the DC level of the output a changes from the bias voltage of the head drive circuit PA ₂ to the bias voltage of the head drive circuit PA ₁ , resulting in a DC step. Here, a control signal e covering the switching timing of the signals d ₁ , d ₂ , d _o and the signal c
However, transistors Q ₃ and Q ₄ are turned on to reduce the time constant of the DC voltage removal circuit for signals c ₁ and c ₂ , thereby quickly converging the transient response appearing in signal b.

The pulse width of the control signal e is determined in consideration of the convergence time of the transient response. Here, if there is no control signal e and the DC step enters the capacitors C ₁ and C ₂ with transistors Q ₃ and Q ₄ in the off state, then
A response as shown by the broken line in FIG. 2 occurs, and it takes time for the output signal h to recover.

In the write operation in the state shown in FIG. 2(3), a write signal having a larger amplitude than the read signal appears in the signal a. Therefore, when switching from state (3) to (4), a transient response occurs as well as when switching from state (1) to (2) described above.
In this case as well, the response converges quickly with the control signal e, and the waveform of the output signal h can quickly return to normal.

In this way, the circuit of the present invention can maintain a sufficiently large time constant with respect to the period of the readout signal at all times, and can quickly remove the DC component during transient response to restore normal operation. Ta. This has the excellent effect of effectively increasing storage capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of an embodiment of the present invention. Figure 2 is a time chart of the waveforms of each part. H ₁ , H ₂ , ......, Hn...Write/read head,
PA ₁ , PA ₂ , ......, PAn...head drive circuit,
A ₁ ... Readout amplifier, T ... Converter, L ... Level converter, R ₁ , R ₂ , R ₃ , R 4 , R ₅ , R ₆ , _{R 7 ,} R ₈ ...
…Resistor, C ₁ , C ₂ … Capacitor, Q ₁ , Q ₂ …
Transistor, Q ₃ , Q ₄ ...FET.

Claims (1)

[Claims] 1. In a readout circuit of a magnetic recording device equipped with a DC voltage removal circuit in which a capacitor is inserted in series with a readout signal transmission line, a circuit that switches the resistance value between the capacitor and ground by a control signal given from the outside is provided. A readout circuit for a magnetic recording device.