JPS6223876B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a continuous recording type voice response device installed in a telephone service system or the like.

In a continuous recording type voice response device in a telephone exchange system, various voices are stored in a disk device, and voice services are provided to subscribers via a buffer memory provided for each subscriber line. Conventionally, in this type of voice response device, only the voice information necessary for the service line is extracted from the voice information continuously output from the voice storage device.
Words (e.g., “Anata”, “No”, “Denwa”,
``Bangou'', ``Ha'', etc.) are written to the buffer memory, but in this case, a buffer amount equivalent to two words is required to support the line. That is, the buffer for the first word is used for reading from the audio storage device, and the buffer for the next word is used for writing the audio after the reading is completed and the buffer memory is switched. It was hot. According to this method, there was an economical problem because a buffer amount equivalent to two words was required to support the line.

SUMMARY OF THE INVENTION An object of the present invention is to provide a voice response device capable of outputting voice with a buffer amount of one speech while being compatible with a line.

The present invention sets the buffer amount corresponding to the line to one word, reads out the information necessary for the line from the voice storage device, temporarily stores it, and writes the buffer amount for one word immediately before the reading of the buffer amount for one word is completed. The reading and writing of one word are completed at the same time.

Hereinafter, a specific example of implementation of the present invention will be described and explained.

FIG. 1 is a circuit block diagram for explaining the principle of the present invention, and FIG. 2 is a time chart of buffer control based on the block diagram of FIG.
In FIG. 1, reference numeral 1 denotes a voice storage device that stores a large amount of voice information.The voice information stored in this voice storage device 1 is selected by a voice selection signal a from a control device 2, and the voice information It is transferred to the switching unit 4 as b. Here, the audio storage device 1 is composed of a disk device as described in the conventional example. This disk device 1 consists of a plurality of tracks, and an index clock is stored at the beginning of each track. In this embodiment, this index clock is actively used for the timing of writing and reading from the buffer memory, which will be described later.

In the switching section 4, the selection signal of the buffer memory 3 is inputted as a signal c from the control circuit 2, and one of the buffer memories 3 provided corresponding to a plurality of lines is selected. Therefore, the control circuit 2 outputs the write signal d and writes the previously read audio information into the buffer memory 3. In parallel, the control device 2 outputs a read signal e, and the buffer memory 3
The audio information f is read out from the converter 5, converted into audio by a converter 5, and output as an audio signal g to the line.

This figure takes advantage of the fact that the time required to write one word into the buffer memory 3 is much faster than the time required to read it from the buffer memory 3.The operation will be explained with reference to the time chart of FIG.

First, the writing line is switched by the control method described above based on the index clock, which is the leading clock output from the audio storage device 1 shown in FIG. In this case, the audio output time is approximately 0.64 (sec) and the index clock time is approximately 20 (msec). That is, as shown in the time chart of FIG. 2, one word must be written every 0.64 (sec) for each line. The write mode is switched by the index clock for each line (0CH, 1CH, 2CH...), and the write mode is switched by the index clock for each line (0CH, 1CH, 2CH...).
“1″” and “2”, “2′”, and “2″”. One word is written in one pulse in the write mode.

Here, the audio output time is determined by the circumstances on the audio output side, and can be thought of as the duration of time that can be heard as audio by the so-called human ears. This is a well-known feature of voice response devices. In this embodiment, the period is set to be twice the period of the index clock of the disk device 1.
Specifically, the cycle was set to 32 times that of the index clock (ratio of 640/20). This double length relationship is determined by the relationship between the rotational speed of the disk device and the period of audio output.

In this embodiment, the writing cycle to the buffer memory is one cycle of the index clock. Moreover, this writing was performed every index clock immediately before the end of the audio output cycle. This allows the index clock to be used as a timing reference, making timing easier.

Also, a read operation is performed in parallel with this, but
The beginning of reading one word is synchronized with the index clock according to the line, and the reading mode shown in the figure is shown, but the beginning of reading one word is delayed by 20 (msec) of the index clock. ing. and,
The written and read contents are "1" and "11", "1'" and "11'", "1" and "11" of the time chart.
”
It corresponds to Now, regarding 0CH, the contents of write mode "1" are read out with a delay of one index clock in read mode. next 0.64
The write mode of (sec) is "2", which overlaps with the read mode "11". In this case, writing of "2" is started while giving priority to reading the contents of read mode "11". In this way, writing and reading for one word is completed. This also applies to other channels.

Note that the read cycle for one sample is 125 μsec.
(8KHz) and write cycle is 3.2μsec
(When using FHD50 mini disk)
The above read and write cycles are fully feasible. Further, the end of reading for one word and the end of writing are approximately the same time, and the write mode has a circuit condition that does not overtake the address to the buffer memory in the read mode.

Next, a specific embodiment of the present invention based on the principle diagram of FIG. 1 will be shown and explained in FIG. 3. FIG. 3 shows the peripheral circuit of the control device in FIG. 1 in more detail, and the same reference numerals as in FIG. 1 indicate the same components. The control device 2 includes a control circuit 6 for the audio storage device 1 and a control circuit 7 for the buffer memory 3.
, a counter 8 and a decoder 9 (switching section 4 in FIG. 1) which are provided between the control circuit 6 and the buffer memory 3 and selectively switch the buffer memory 3, a word address buffer memory 10, and its control circuit 11.
It consists of. Note that register 12 is a bit group (byte) consisting of 8 bits from the audio storage device.
This is for converting the output audio signal into words and outputting them to the buffer memory 3.

According to the block circuit diagram of FIG. 3, first, the control circuit 11 edits the audio and sets a disk address in the word address buffer corresponding to the line. The contents of this buffer memory are switched every 0.64 (sec) as shown in the time chart in FIG. Set to disk address counter.
Furthermore, in the audio storage device 1, audio parameters are output after a certain period of time has elapsed after the index clock is sent. The audio information is serially input in the SP conversion register 12 and is converted into parallel audio information and sent to the buffer memory 3 corresponding to the line.

On the other hand, the buffer memory 3 decodes the contents of the counter 8 that received the index clock, automatically selects the buffer memory 3 corresponding to the assigned line, and opens the input gate for audio information from the register 12. In this case, writing to the line-compatible buffer memory 3 is controlled by the buffer control circuit 7, and in parallel, writing to the buffer memory 3 is controlled by the buffer control circuit 7.
Read from. The timing is generated by the buffer control circuit 7 and also includes write and read priority circuits.

According to the above-described circuit configuration, when the write operation for one word on one line is completed, the next line is selected by the next index clock, and writing is performed in the same control order. In parallel with this, the beginning of one word is read out with a delay of one index clock. By writing the audio information read from the audio storage device 1 as described above into the line-compatible buffer memory, the audio information that conventionally required two words' worth of buffer memory can be replaced with one word's worth of buffer memory. It outputs the following.

As is clear from the above-described embodiments, according to the present invention, the buffer amount corresponding to the line can be reduced to 1/2 that of the conventional one, and an economical voice response device can be obtained.

[Brief explanation of the drawing]

The attached drawings are diagrams for explaining one embodiment of the present invention, in which Fig. 1 is a block diagram explaining the principle of a continuous recording type voice response device, and Fig. 2 explains the operation of Fig. 1. FIG. 3 is a block diagram of a control circuit for a line-compatible buffer memory constructed based on the principle diagram of FIG. 1. DESCRIPTION OF SYMBOLS 1... Audio storage device, 2... Control device, 3... Buffer memory, 4... Switching part, 5... Conversion part, 6... Storage device control circuit, 7... Buffer memory control circuit, 8...
Counter, 9...Decoder, 10...Word address buffer, 11...Control circuit, 12...Register.

Claims (1)

[Scope of Claims] 1. A disk device that stores audio information, a buffer memory installed to correspond to a line, and each index clock from the disk device, switching the audio information from the disk device to correspond to the line. means for temporarily writing into a buffer memory, means for reading the audio information written in each of the buffer memories at a cycle equal to a double length of the index clock, and converting the audio information read from each of the buffer memories into audio. It consists of a line-compatible audio converter that obtains audio signals and outputs audio in a line-compatible manner, and the write cycle to each of the buffer memories is determined by the index clock immediately before the end of the audio information reading cycle of the own buffer memory. Synchronized voice response device.