JPS6224663A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve information holding characteristics by increasing overlapping areas of gate electrodes and upper surfaces of source and drain regions in MISFET's which constitute a flip-flop circuit. CONSTITUTION:N<+> type semiconductor regions 4 constitute switching MISFET's QSW with gate insulation films 5 and gate electrodes 6 and the gate electrodes 6 are formed together with word lines WL. N-type semiconductor regions 7 constitute driving MISFET's QDR of a flip-flop circuit with gate insulation films 8 and gate electrodes 9 and each semiconductor region 7 consists of an N<+> type semiconductor region 7A and an N<++> type semiconductor region 7B which has impurity concentration higher than the region 7A. The N<+> type semiconductor region 7A is provided to make the channel length of the driving MISFET QDR equal to that of the switching MISFET QSW or to those of MISFET's composing peripheral circuits. With this constitution, the overlapping area of the gate electrode 9 and the upper surface of the semiconductor region in the driving MISFET QDR is made to be larger than the area in the switching MISFET QSW.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a 44-body storage device, and in particular,
The present invention relates to a technique that is effective when applied to static RAM (SRAM).

[Background technology] Information in SRAM is retained by MIS that constitutes memory cells.
This is caused by charges accumulated in the parasitic capacitance of the gate electrode of the FET and the parasitic capacitance of the semiconductor region to which this gate electrode is connected.

The inventors of the present invention have discovered the problem that soft errors are more likely to occur as SRAMs become more highly integrated. As integration becomes higher, MISFETs in memory cells are reduced, and parasitic capacitance is also reduced.

However, the charge stored in the parasitic capacitance gradually decreases due to leakage current.

Note that technology related to SRAM is described in, for example, Japanese Patent Laid-Open No. 130461/1983.

[Object of the Invention] An object of the present invention is to provide a technique that can improve the information retention characteristics of a semiconductor memory device.

Another object of the present invention is to provide a technique that can improve information retention characteristics by increasing the amount of charge stored in a flip-flop circuit serving as a memory cell.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief outline of one typical invention disclosed in this application is as follows.

That is, information retention characteristics are improved by increasing the area where the gate electrode of the M I S FET constituting the flip-flop circuit, which is a memory cell, overlaps with the upper surface of the source and drain regions.

Hereinafter, the configuration of the present invention will be explained along with examples.

[Example] FIG. 1 is a plan view of the SRAM memory cell of this example, and FIG. 2 shows the configuration of the memory cell in order to make it easier to see.
A plan view showing the second conductive layer and the third conductive layer removed, FIG. 3 is a sectional view taken along the first ■-■ cutting line,
FIG. 4 shows an equivalent circuit of a memory cell. In addition, Figure 1,
In order to simplify the configuration of the memory cell, FIG. 2 does not illustrate the interlayer isolation film provided between the conductive layers.

1 shown in FIGS. 1 to 3 is a P-type semiconductor substrate, and a field insulating film 2 is provided in a pattern as shown in FIG. 2. Below this field insulating film 2, as shown in FIG. As shown in FIG. 3, a P+ type channel stopper region 3 is provided. 4 is an n1 type semiconductor region, which is used as the switch M T shown in FIG. 4 together with the gate insulating film 5 and the gate electrode 6.
It constitutes S FETQsw. Note that the gate electrode 6 is formed integrally with the word line WL.

Reference numeral 7 denotes an n-type semiconductor region, which together with the gate insulating film 8 and the gate electrode 9 constitutes the MI 5FET Qo R for driving the flip-flop circuit shown in FIG. The semiconductor region 7 is composed of an n+ type semiconductor region 7A and an n" type semiconductor 7B having a higher impurity concentration than the n+ type semiconductor region 7A. The n+ type semiconductor region 7A is mainly provided on the surface of the semiconductor substrate 1 under the gate electrode 9. Yes, the n'' type semiconductor region 7B is the gate electrode 9
It is provided on the surface of the semiconductor substrate 1 on the side of the semiconductor substrate 1.

By providing the n+" type semiconductor region 7B, the parasitic capacitance between the semiconductor region 7 and the semiconductor substrate 1 increases. This is because the parasitic capacitance of the semiconductor region 7 is proportional to the square root of its impurity concentration.

On the other hand, as shown in FIG.
It is much larger than that of TQsw. This is to increase the parasitic capacitance between the gate electrode 9 and the semiconductor substrate 1. Note that the gate electrode 9Φ pattern does not need to be particularly limited as long as the parasitic capacitances of both gate electrodes 9 are similar. The length of the gate electrode 9 of the driving MISFET QDR is
Usually, as shown by the dashed line in Fig. 2,
It is formed to have approximately the same length as the gate electrode 6 of ISFETQsw. This is to make the channel lengths about the same. Preferably, the gate electrode 6 of the switch MI S FET
Make it somewhat smaller. M for driving mutual conductance
This is to make it smaller than I5FETQoR. If the mutual conductance of the switching MISFET QsW is the same as or larger than that of the driving MISFET, the information will be inverted when reading the information. This is because the drive MISFET QoR, which should be in a non-conductive state, becomes conductive.

On the other hand, in order to make the channel length of the drive MISFETQotz comparable to that of the switch MISFETQsw or the MISFET constituting the peripheral circuit (not shown), the n+ type semiconductor region 7A can be provided. be. By providing this semiconductor region 7A,
The weight between the gate electrode 9 of the drive MI 5FETQo R and the top surface of the semiconductor region 7 is the weight of the switch MISFETQs
It is larger than that of w. Further, by providing the semiconductor region 7A under the gate electrode 9, the parasitic capacitance of the gate electrode 9 becomes larger than when the semiconductor region 7A is not provided. If the n+ type semiconductor region 7A is not provided under the gate electrode 9, an inversion layer serving as one electrode of the capacitor must be formed on the surface of the semiconductor substrate l. This inversion layer is formed when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 9. From this, the effective voltage for charging the parasitic capacitance is the value obtained by subtracting the threshold voltage from the voltage Vcc. However, by providing the n+ type semiconductor region 7A, the voltage applied to the gate electrode 9 itself becomes a voltage for charging the parasitic capacitance. Therefore, the parasitic capacitance of gate electrode 9 increases. Note that the parasitic capacitance of the driving MISFET QOR that stores information is the sum of the parasitic capacitance of the gate electrode 9 and the parasitic capacitance of the semiconductor region 7 serving as the drain region. This is because, as shown in FIG. 4, the gate electrode 9 of one driving MISFETQoR is connected to the drain region of the other driving MISFETQoR. Therefore, as described above, by increasing the parasitic capacitance of the gate electrode 9 and the semiconductor region 7, the driving MISF E T Q
o The information retention characteristics of R are significantly improved.

Note that the parasitic capacitance of the gate electrode 6 of the switch MISFET Qsw is made as small as possible in order to speed up writing and reading. For this reason, in this embodiment, the gate electrode 6 of the switch MI 5FET 6 is connected to the drive MI S
It is not made large like the gate electrode 9 of FETQo*. Further, each of the gate electrodes 6.9 is made of phosphorus (P).
, a polycrystalline silicon layer containing n-type impurities such as arsenic (As), but is not limited thereto. For example, molybdenum (Mo), titanium (TB)
It may be formed using a high melting point metal layer such as , tungsten (W) or the like. Alternatively, it may be formed of a silicide layer of these high-melting point metals, or the high-melting point metal layer or silicide layer may be provided on a polycrystalline silicon layer.

The P+ type semiconductor region 10 provided below the semiconductor region 7 is provided to further increase the parasitic capacitance between the semiconductor region 7 and the semiconductor substrate 1.

Note that although the semiconductor region 10 is not shown in FIGS. 1 and 2, it is provided in the same pattern as the semi-quartet region 7.

The parasitic capacitance between the semiconductor region 7 and the semiconductor substrate 1 is formed by using the depletion layer between them as a dielectric. However,
Since the impurity concentration of the semiconductor substrate 1 is much lower than that of the semiconductor region 7, the depletion layer formed between them becomes thick.

However, by providing the P+ type semiconductor region 10, the thickness of the depletion layer becomes thinner, so that the parasitic capacitance of the semiconductor region 7 further increases. Note that the semiconductor region l
O is formed so that the peak value of the impurity concentration is near the interface with the semiconductor region 7. n“ type semiconductor region 7 and P
This is to make the depletion layer between the + type semiconductor regions 10 as thin as possible. on the other hand.

As can be understood from Fig. 1 or 2, the driving MI
The semiconductor region 7 of the 5FETQo R is a switch MI
It is larger than the semiconductor region 4 of S F E T Q s w. Therefore, it is easily affected by unnecessary minority carriers generated by alpha rays etc. that have entered the semiconductor substrate 1. The semiconductor region 10 also has a function of preventing unnecessary minority carriers in the semiconductor substrate l from entering the semiconductor region 7. but.

The switch MISFET Qsw is not easily affected by unnecessary minority carriers because the semiconductor region 4 is small as described above. Therefore, in this embodiment.

The P' type conductor region IO is not provided below the switch MISFET Qsw. This is also effective for not increasing the parasitic capacitance of the switch M r S F E T Q sw. Note that the p1 type half region 10 does not necessarily need to be provided. By not providing the P+ type semiconductor region IO, the junction breakdown voltage between the semiconductor region 7, which becomes the drain region, and the semiconductor substrate 1 is improved. Further, a P+ type semiconductor region 10 is provided only under the semiconductor region 7 which becomes a drain region, and a P+ type semiconductor region 10 is provided below the semiconductor region 7 which becomes a source region and a ground layer.
0 may not be provided. This is because among the parasitic capacitances of the source and drain regions, it is the parasitic capacitance of the drain region that is effective in retaining information. On the other hand, when rewriting information, it is necessary to release the electric charge that becomes the information that was previously held.

However, if the parasitic capacitance of the ground layer is large, the time for releasing charges increases, and therefore the information writing speed decreases. However, by not providing the p+ type semiconductor region 10 under the semiconductor region 7 serving as the ground layer, the time required for discharge of charges is reduced, so that the writing speed can be improved.

Reference numeral 11 denotes a resistance element made of a polycrystalline silicon layer that does not contain impurities such as phosphorus and arsenic, and is the load resistance R shown in FIG. Conductive layers 12 similarly made of polycrystalline silicon are integrally formed at both ends of this resistance element 11. One of the conductive layers 12 is for connecting the resistive element 11 to a Vcc level power supply terminal, and the other conductive layer 12 is for connecting the resistive element 11 and the predetermined semiconductor regions 4 and 7 through the connection hole 13. belongs to. This conductive layer 12 has a sufficiently reduced resistance value by containing n-type impurities such as phosphorus and arsenic. The conductive layer 12 can be formed to have the same width as the resistive element 11, but in this embodiment, as shown in FIG. It has been done. This is to further increase the parasitic capacitance of the gate electrode 9. Reference numeral 14 denotes an insulating film made of a silicon oxide film or the like, and is provided to cover the word line WL and gate electrode Fi9. On this insulating film 14, an insulating film 15 made of phosphosilicate glass (PSG) or the like is provided to cover the conductive layer 12 and the resistive element 11. 16 is a conductive layer made of aluminum, 16A and 16B are used as data lines D L r and D L 2, and 16 C
is used to connect the ground M (semiconductor region 7) to the Vss level power supply terminal. Conductive layers 16A, 16B
is connected to the semiconductor region 4 through the connection hole 17, and the conductive layer 17C is connected to the ground layer (semiconductor region 7) through the connection hole 18. Note that an uppermost protective film may be further provided on the insulating film 15.

Next, a method for manufacturing the SRAM of this embodiment will be explained.

First, using FIGS. 5 and 6, the driving MI
A method of forming the semiconductor region 7 of S F E T Q OR and the semiconductor region 4 of MISFEQsw for switch will be explained. FIG. 5 is a plan view of the memory cell in the manufacturing process, and FIG. 6 is a cross-sectional view taken along the line Vl--Vl in FIG. As shown in the figure, a field insulating film 2 and a channel stopper region 3 are formed using a well-known technique. Next, the semiconductor substrate 1 exposed from the field insulating film 2 is
MISFE for switch by oxidizing the surface of
TQsW gate insulating film 5 and driving MISF
ETQ.

A second gate insulating film 8 is formed. Next, drive MISF
A resist mask 19 for ion implantation, particularly for forming the n+ type semiconductor region 7A for ETQoR, is formed. Note that the width of the resist mask 19 in the region where the gate electrode 9 of the driving MI 5FETQo R is provided is the distance between the semiconductor regions 7A.

That is, the channel length of the driving MISFETQo R is set to a predetermined value.

Next, an n-type impurity 20 such as phosphorus or arsenic is introduced into the surface of the semiconductor substrate 1 by ion implantation.

Note that this n-type impurity 20 may be introduced before forming the field insulating film 2 and the channel stopper region 3. In this case, it is preferable to use arsenic, which has a small diffusion coefficient. This is to suppress the diffusion of n-type impurities as much as possible during the thermal oxidation step when forming the field insulating film 2.

After introducing the n-type impurity 20, an n-type impurity (not shown) such as boron (B) is introduced by ion implantation in order to form a −“ type semiconductor region IO.A mask for ion implantation is as follows. The resist mask 19 used when introducing the n-type impurity can be used.However, ion implantation may be performed without using the resist mask 19.If the mask is not used, the n-type impurity will Because it is also introduced at the bottom of S F E T Q s w.

The P+ type semiconductor region 10 is a driving MISFET.
Q.

MISFET Q s for the switch as well as the lower part of 6
It will also be provided at the bottom of w. Furthermore, as described above, in order to avoid providing the P'' type semiconductor region 10 under the n+ type semiconductor region 7 which becomes the ground layer, a new resist mask is formed separately from the resist mask 19. As described above, the reason why the ion implantation for forming the P+ type semiconductor region 10 is performed after the ion implantation for forming the n" type semiconductor region 7 is to suppress the diffusion of the P+ type semiconductor region 10 as much as possible. be.

After this ion implantation, the resist mask 19 is removed.

Next, using FIG. 7, switch MISFET Q s
A method of forming the gate electrode 6 of the drive MISFET QOR and the gate electrode 9 of the driving MISFET QOR will be described. FIG. 7 is a cross-sectional view of the memory cell during the manufacturing process at the same portion as in FIG. 6.

In order to form the gate electrodes 6 and 9, a polycrystalline silicon layer is formed on the entire surface of the gate insulating film 5.8 etc. by CVD or the like. In order to reduce the resistance value, n-type impurities such as phosphorus and arsenic are introduced into this polycrystalline silicon layer by thermal diffusion or the like. Next, each of the gate electrodes 6.9 is formed by selectively removing the polycrystalline silicon layer. Next, in order to form the semiconductor region 4 of the switch MIS FET Qsw, etc., rl type impurities are introduced into the surface of the semiconductor substrate 1 by ion implantation. Ion implantation mask.

Goo 1 - Use electrodes 6 and 9. By this ion implantation, n-type impurities are introduced again into the portion exposed from the resist mask 19 shown in FIG. Therefore, an n+" type semiconductor region 7B is formed.
Drive MISFETQ.

By forming the gate electrode 9 of No. 9 after forming the gate electrode t@6 of the switch MISFET Qsw and the semiconductor region 4, the ion implantation step for introducing n-type impurities can be performed at one time. At the time of ion implantation, a resist mask may be formed on the upper part of the gate insulating film 8 on the channel region of the driving MISFET QO%l. This resist mask is formed after forming the gate electrode 6, that is, the word line WL.

Also, the gate of MISFETQsw for the switch? l! Pole 6 and gate electrode 9 of driving M r 5FET Qo R
can be formed in the same process, and the semiconductor regions 4 and 7 of both MISFETs can also be formed by self-alignment. You can do it like this: First, gate electrodes 6 and 9 are formed. Next, an n-type impurity with a small diffusion coefficient, that is, arsenic, is introduced by ion implantation. Next, a region where the switch MISFETQsw is provided is covered with a resist mask. Next, drive MISFE
An n-type impurity having a large diffusion coefficient, that is, phosphorus, is introduced into the region where TQoR is provided by ion implantation.

The semiconductor substrate 1 is then annealed to form semiconductor regions 4 and 7. That is, the weight of the gate electrode 9 of the driving MISFET QOR and the semiconductor region 7 is increased by utilizing the difference in diffusion coefficient between phosphorus and arsenic.

Therefore, the width of the gate electrode 9 is determined by the difference in the horizontal extension of the impurity.
It can be made larger than the gate electrode 6 of sw. With such a method, it is difficult to significantly enlarge the gate electrode 9 as shown in FIG. However, n+
The parasitic capacitance can be increased by the "type semiconductor region 7B.

After forming each of the semiconductor regions 4.7, the insulating film 1 is
4, connection hole 13, conductive layer 12. Resistance element 11, insulating film 1
5. The connection holes 17 and 18 and the conductive layer 16 are sequentially formed by a well-known technique.

[Effects] The following effects can be obtained by the new technology disclosed in the present application.

(1) Driving M I that constitutes a flip-flop circuit
By making the gate electrode of the S FET larger than the gate electrodes of the switch MISFET, the overlap between the gate electrode and the top surface of the semiconductor region increases, increasing the parasitic capacitance for retaining information. I can do it.

(2) According to (1) above, information retention characteristics can be improved.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, in the embodiment described above, the SRAM is constructed on a p-type semiconductor substrate, but it may be constructed on an n-type semiconductor substrate. Furthermore, the flip-flop circuit may be configured by complementary MIS FETs. In a flip-flop circuit composed of complementary MISFETs, the parasitic capacitance of the semiconductor region of the p-channel MISFET is added to the parasitic capacitance of the semiconductor region of the 0-channel MISFET, so that information retention characteristics can be further improved. Furthermore, a depletion type MISFET may be used as the load resistor. In this case as well, the parasitic capacitance of the semiconductor region of the deregression type MISFET is added.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a plan view of an SRAM memory cell according to an embodiment of the present invention. FIG. 2 is a second conductive layer and a third conductive layer of the memory cell. A plan view shown with and removed. FIG. 3 is a cross-sectional view taken along the line ■--■ in FIG. 1, and FIG. 4 is an equivalent circuit diagram of the memory cell. FIG. 5 is a plan view of the memory cell in the manufacturing process. 6 is a sectional view taken along the line Vl--Vl in FIG. 5, and FIG. 7 is a sectional view of the memory cell in the 12th manufacturing process. 1... Semiconductor substrate, 2... Field isolation ls1 film,
3... Channel stopper region, 4.7A, 7B, 10
...Semiconductor region, 5,8.14.15...Insulating film,
6.9.12.16.16A, 16B, 16C... conductive layer. 11...Resistance element, 13.17.18...Connection hole, 1
9...Resist mask, 20...Impurity, Qsw, Q
, R-MI 5FET, R-...resistance element, DL+,
DL2...Data line. Figure 1 Figure 2

Claims (1)

[Scope of Claims] 1. A semiconductor memory device in which a memory cell is constituted by a flip-flop circuit having a MISFET and a switch MISFET provided at an input/output terminal of the flip-flop circuit, wherein the MISFET of the flip-flop circuit A semiconductor memory device characterized in that the overlapping portion between the lower surface of the gate electrode and the upper surface of the source and drain regions is larger than the overlapping portion between the lower surface of the gate electrode and the upper surface of the source and drain regions of the switch MISFET. 2. The flip-flop circuit is an n-channel MIS
2. The semiconductor memory device according to claim 1, comprising a FET and a load resistor connected to the FET. 3. The flip-flop circuit is a complementary MISFET
A semiconductor memory device according to claim 1, which is constructed by: 4. The flip-flop circuit is an n-channel MIS
FET and depletion type MISF connected to it
The semiconductor memory device according to claim 1, which comprises an ET.