JPS6224878B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device, and particularly to a multi-bit simultaneous write type storage device.

A conventional storage device of this type, for example, using a 2-bit simultaneous write method, was constructed as shown in FIG. That is, 11 is an address buffer circuit, which is composed of an inverter 1 and NOR circuits 2 and 3, which shapes the waveform of an address selection input signal and outputs complementary logic signals P ₁ and P ₂ . 5 is a memory block, and the first and second sub-blocks 5 ₁ , 5 ₂
First and second write circuits 6 ₁ and 6 ₂ are provided corresponding to the sub-blocks 5 ₁ and 5 ₂ . The write circuits 6 ₁ , 6 ₂ are correspondingly controlled by the logic signals P ₁ , P ₂ and write the data input into the cells in the corresponding sub-block when the logic signal level is, for example, "high". In this case, the logic signals P ₁ and P ₂ are complementary, and only the cells of either sub-block 5 ₁ or 5 ₂ are written.

Above is the address input signal at normal logic level,
That is, this is the operation when driven with an amplitude less than the power supply voltage (Vcc). On the other hand, when the address input signal is made sufficiently higher than Vcc, the high potential detection circuit 4 performs a detection operation, and the signal output P ₀ becomes "low".
become the level. As a result, the output levels of both NOR circuits 2 and 3 of the address buffer circuit 11 become "high", and the write circuits 6 ₁ and 6 ₂ are simultaneously activated. Therefore, subblock 5 ₁ ,
The same data is written in parallel in ₅₂ .

As described above, simultaneous multi-bit writing is particularly effective for memory elements in which writing takes longer than reading, such as ultraviolet erasable read-only memory (EPROM).

However, in the circuit shown in FIG. 1 described above, when reading the written contents of a cell after setting the address input sufficiently higher than Vcc to perform simultaneous writing, the simultaneous writing function of the address buffer circuit 11 is canceled. It is necessary to return to the normal read mode, and the address input waveform must be controlled to three values as shown in FIG. This makes it difficult to design an external circuit for simultaneous writing, and it takes time for the address input waveform to become stable, which ultimately makes it impossible to shorten the write and read times that should be shortened. As described above, since the address waveform described above is used when reading (verifying) the written contents, there is a drawback that the reading time cannot be shortened as a result.

The present invention was made in view of the above circumstances, and
By using signals normally used inside the device to automatically release the circuit function for simultaneous writing when reading after simultaneous writing, the address input waveform can be simplified, and the process can be completed in a short time. This provides a storage device that can be easily read.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

3a, 30 is an address buffer circuit, 31 is a high potential detection circuit; in FIG. 3b, 5 ₁ and ₅₂ are first and second sub-blocks forming a memory block; 33 is a sense amplifier;
34 ₁ and 34 ₂ are write circuits.

The high potential detection circuit 31 includes inverters _I1 to _I3 .
, and a NOR gate formed by an enhancement type E reset transistor T ₀ connected in parallel to the output side of the inverter I ₄ are connected in cascade. For convenience of explanation, the inverter is shown as an E/D type based on an N-channel process, and the threshold voltage of the enhancement type transistors T _E and T _p is 0.6 V, and the threshold voltage of the depletion D type transistor T _D is -3.0. It is V. Further, the voltage of the power supply Vc is 5V, and the reference potential Vs is Ov. Then, the address signal Ain is input to the first stage inverter _I1 , and the reset signal F is introduced as the gate input of the reset transistor _Tp . This reset signal F is normally used inside the storage device, and is at a low level only during writing, and at other times is at a high level and is connected to a reset transistor T.
_p is turned on, and the output signal P ₀ of the high potential detection circuit 31 is turned on.
This is for resetting to a low level. In addition, the first stage inverter _I1 has an address input
Ain is at a sufficiently high potential (for example, 12V) compared to the Vc voltage.
The beta ratio of the D-type transistor T _D and the E-type transistor T _E is set so that the threshold voltage becomes high. Note that the 2nd to 4th stages of inverters I ₂ to I ₄ are for waveform shaping.

On the other hand, in the address buffer circuit 30, inverters I ₆ and I ₇ for waveform shaping are connected in cascade to an inverter I ₅ to which the address input Ain is guided, and buffer gates BF ₁ and BF ₂ are complemented by the inverters I ₆ and I ₇ . It is becoming more and more driven by Furthermore, E-type transistors T ₁ and T ₂ are connected in parallel corresponding to the output sides of the inverters I ₆ and I ₇ , and the output signal P ₀ of the high potential detection circuit 31 is guided to their gates. There is. Note that the inverter I ₆ and the transistor T ₁ form a NOR gate, and the inverter I ₇ and the transistor T ₂ form a NOR gate.

On the other hand, sub-blocks 5 ₁ and 5 ₂ are, for example,
It constitutes an EPROM, and the transistor _TFG group is its memory cell. An E-type transistor whose gate is controlled by the output signal of the buffer gate BF ₁ is connected between the collective connection point A ₁ of the group of column selection transistors Tc ₁ corresponding to the first sub-block 5 ₁ and the sense amplifier 23. T ₃₁ is inserted. Further, between the collective connection point _A2 of the _two groups of column selection transistors Tc corresponding to the second sub-block ₅₂ and the sense amplifier 23, there is an E-type circuit whose gate is controlled by the output signal Ain of the buffer gate _BF2 . Transistor T ₃₂ is inserted.

On the other hand, in the write circuit ₃₄₁ , _NA1 is a NAND gate to which the data input and the output signal of the buffer gate _BF1 are guided, and _I8 is this gate.
The inverter _T33 to which the output of _NA1 is guided is an E-type transistor whose gate is controlled by the output of this inverter _I8 and inserted between the high voltage power supply Vp and the bulk connection point _A1 .

Similarly, the write circuit ₃₄₂ includes a NAND gate _NA2 to which the data input and the output of the buffer gate _BF2 are guided, an inverter _I9 , and a high voltage power supply Vp.
It consists of an E-type transistor T ₃₄ inserted between and the collective connection point A ₂ .

Next, the operation of the above configuration will be explained. First, during normal operation, the address input Ain is at a normal level, and the buffer gates BF _{1 and} BF of the address buffer circuit 30 are activated in accordance with this address input Ain.
A “high” level output can be obtained from either BF ₂ . At this time, in the read mode, one of transistors T ₃₁ and T ₃₂ is turned on, and information read from one of sub-blocks 5 ₁ and 5 ₂ is input to sense amplifier 33 . On the other hand, if it is in the write mode at this time, when the data input is at the "high" level, one of the write circuits 34 ₁ and 34 ₂ writes into one of the sub-blocks 5 ₁ and 5 ₂ . i.e. for example Batsufuagate BF ₁
When the output signal of is at the "high" level, the output of the NAND gate _NA1 becomes "low" in the write circuit ₃₄₁ , and the output of the inverter _I8 is approximately Vpp.
(approximately 21V), and transistor T ₃₃ for writing
Data is written into the memory cell whose address is selected through the transistor selected from the column selection transistor Tc ₁ group.

Note that during the above-mentioned normal operation, the high potential detection circuit 31 does not perform a detection operation because there is no high potential input, and its output signal P ₀ becomes a "low" level and the transistors T ₁ and T of the address buffer circuit 30 ₂ is turned off, the address buffer circuit 30 performs normal operation.

Next, a simultaneous write operation will be explained. At this time, since the address input Ain becomes 12V or more, the output signal _P0 of the high potential detection circuit 31 becomes a "high" level. Therefore, address buffer circuit 3
0 transistors T ₁ and T ₂ are both turned on, and the outputs of inverters I ₆ and I ₇ are both at the "low" level. Therefore, the outputs of the buffer gates BF ₁ and BF ₂ are approximately the absolute value of the threshold voltage of the D-type transistor _TD , that is, 3V, and both are at a "high" logic level. As a result, the write circuits 34 ₁ , 3
4 ₂ data inputs are write circuits 34 ₁ , 34 ₂
are simultaneously written to sub-blocks 5 ₁ and 5 ₂ through.

Thereafter, when reading to verify the written contents of the cell, the signal F becomes "high" level and the high potential detection circuit 31 is automatically reset. Therefore, it is not necessary to return the level of the address input waveform to the normal voltage (12 V or less) during reading after this simultaneous writing, and the address input waveform may be as shown in FIG. 4. This is simpler than the conventionally required address input waveform shown by the solid line in FIG. 2 mentioned above.

In other words, according to the above-mentioned memory device, a signal corresponding to a period outside the write period normally used inside the device is used to automatically reset the high potential detection circuit at the time of reading after simultaneous writing, and the high potential detection circuit is automatically reset for simultaneous writing. The circuit function is controlled to be automatically canceled. Therefore, it is not necessary to return the high potential of the address input waveform to the normal potential during the readout, and the readout can be performed easily and in a short time. Therefore, if the present invention is applied to a storage device that requires a long write time, such as an EPROM, great effects can be achieved.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be applied to other storage devices such as static RAM, C-MOS RAM, and dynamic RAM. This is because in these storage devices, memory blocks are often divided into a plurality of subblocks in order to speed up reading and writing. Particularly in large-capacity storage devices, application of the present invention is very important in order to shorten test time. Further, although the above embodiment describes the case of simultaneous writing of two bits, the present invention can also be applied to simultaneous writing of even more bits. Furthermore, the present invention is applicable not only to N-channel E/D circuits but also to memory devices that implement high-potential detection circuits, address buffer circuits, etc. using P-channel circuits, C-MOS circuits, dynamic circuits, etc. It is.

Further, in the above embodiment, simultaneous writing is controlled by detecting the high potential of the address input Ain by the high potential detection circuit 31, but instead of this, as shown in FIG. and the signal F are connected to a NOR gate 51 (for example, FIG.
(similar to the combination of inverter _I4 and transistor _T0 ), and the output signal _P0 of this NOR gate 51 is guided to the address buffer circuit 30 in the same way as the output of the high potential detection circuit 31 in FIG. You can do it like this. In this case, if the pad 50 is set to a "low" level during simultaneous writing (at this time, the signal F is also set to a "low" level), the output of the NOR gate 51 becomes a "high" level, and the same result as in the previous embodiment is obtained. can get. Once writing is completed in this way, assembly can be performed by fixing the input to pad 50 at a "high" level. In this case as well, there is no need to perform the conventional three-value control on the address input waveform.

As described above, according to the present invention, the circuit function for simultaneous writing is automatically canceled when reading after simultaneous writing, so the address input waveform can be simplified and reading can be performed easily in a short time. Storage devices can be provided.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing a conventional storage device, FIG. 2 is a diagram showing address input waveforms of the device in FIG. 1, and FIGS. 3a and 3b show an embodiment of the storage device according to the present invention. FIG. 4 is a diagram showing address input waveforms of the device shown in FIG. 3, and FIG. 5 is a circuit diagram showing a modification of the high potential detection circuit shown in FIG. 3a. 5 ₁ , 5 ₂ ... Sub block, 30 ... Address buffer circuit, 31 ... High potential detection circuit, 34
₁ , 34 ₂ ...Writing circuit, _T0 ...Reset transistor.

Claims (1)

[Scope of Claims] 1. A memory block divided into two or more sub-blocks, a plurality of write circuits provided corresponding to each of the sub-blocks, and control means for selecting these write circuits individually or simultaneously;
A storage device characterized by comprising: canceling means for automatically canceling the simultaneous selection function of the control means at the time of reading after simultaneous selection of each of the write circuits by the control means. 2. The control means includes a detection means for detecting a signal input when simultaneously writing to each sub-block, and selects each of the write circuits simultaneously or individually according to the address input depending on the presence or absence of a detection output of this detection means. 2. The storage device according to claim 1, wherein said release means is a circuit that resets said detection means by a signal generated outside a write period.