JPS6226052B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to data processing systems, and more particularly to
Relating to a system including a preemption function. In large multiprocessor systems,
Processor performance depends on the system's large main memory
Or there is a cutter between the auxiliary storage device and the central processing unit.
Providing an e-store, i.e., a high-speed buffer storage device.
It has been improved by. Further increases system performance
In order to strengthen
gives the data line requested by the central processing unit.
After the next sequential data line is automatically
Also includes a prefetch function retrieved by the store
It was hot. The disadvantages of the aforementioned systems are that such systems
The next sequential line is immediately prefetched from main memory.
Conditions that change the basic concept of what should be done
This was not taken into account. The above short
To overcome this problem, some systems use main memory
Preempt the next sequential line from to high-speed buffer
and the system console device.
related to the form of the program executed by the use
The current
Contains an algorithm for replacing lines, and
Ta. In particular, this system uses variables in the preemption control algorithm.
Contains operating status registers corresponding to . this
Variables like
It is based on The above configuration means that before a certain request is made, the next
Versatility regarding accessing data lines
, but this preemption request is canceled by the previous request.
A particular byte or feature of a line being matched
The short term “based on arbitrary circumstances regarding a fixed place”
have a place This is an advantage for certain operations.
However, in other cases this may result in a decrease in performance.
In particular, automatic access operations can increase memory congestion.
Ru. Therefore, the main purpose of the present invention is to provide a kind of pre-emption mechanism.
Providing an improved data processing system with
It is in. Another object of the invention is to provide a high speed processing system or multiple
Pre-emption suitable for use in any heavy processing environment
Improved data processing system with
On offer. The above objects and advantages of the present invention have been achieved.
achieved in a new embodiment, the configuration of which is less
both combined into one central processing unit and main memory
data containing a high-speed buffer or cutter device
Contains a processing system. preferred embodiment
In this case, the processing unit is controlled by a microprogram.
Acts below. This processing device
control to establish different action cycles for
Contains logic circuits. Furthermore, the execution of certain types of instructions
Some microinstruction words accessed during read-ahead
is encoded to specify the operations to be performed. similar
, this control logic circuit has a code for this instruction format.
for forming look-ahead commands for the Tsushie device.
Contains equipment. The cutlet device that responds to each look-ahead command
data stored in the cutlet device in advance.
specified by the instruction being executed when
Retrieve one block of data from main memory.
It acts like a sea urchin. In action, certain types of
Microprogram control during execution of program instructions
Either the control logic circuit or the control logic
to the cutlet device at a predetermined point during the execution of
A look-ahead command is generated for this. In this way, a life
normally required at a later point in the execution of the command.
The data that is displayed is used by other operations related to this instruction
While the data is being stored, the files previously retrieved from main storage are
The information can be stored in the Tsusier device. In a preferred embodiment of the invention, a certain type of
type instructions require a significant amount of address preparation.
Multi-word instructions with multiple descriptor addresses
Contains. Configuration and operating method considered to be the characteristics of the present invention
The innovative features of the
For further information, please read the following description regarding the attached drawings.
It will be well understood. However, each attached drawing is an illustrative example.
It is provided solely for the purpose of
It should be understood that this is not intended to be a limitation on the
It is possible. DESCRIPTION OF THE PREFERRED EMBODIMENT overview As can be seen from FIG.
A system with at least one input/output processor
(IOPP) 200 and system interface
equipment (SIU) 100 and high-speed multiplexer
(HSMX)300 and low speed multiplexer
(LSMX) 400, upper processor 700, and
Tsushie memory 750 and local memory module
At least one memory corresponding to Yule 500
- module and remote memory module 8
At least one memory module corresponding to 00
Including tools. Each of these modules has a different
multiple types of interfaces 600 to 603.
System interface 1 via several lines
00 to one of the many ports. In particular,
Output processor 200 and cutlet memory 75
0 and high-speed multiplexer 300, respectively.
Connect G, E, and A to low-speed multiplexer 40.
0, local memory module 500 and main memory
Lee module 800 is connected to port J, respectively.
Connect with LMO and RMO. The upper processor 700
Connect to Katsushi Memory 750. The input/output system in Figure 1 consists of a large number of active modules.
"Passive Module" and "Memory Module"
module”. IOP process
processor 200, upper processor 700, and high-speed multi
Each of the plexers 300 has the ability to issue commands.
Acts as an active module. active module
Normally connected to ports A through H, the upper processor
700 via interfaces 604 and 600
and connect to port E via the cutter device 750.
Ru. Multiple passive modules have three ports J, K
and connected to L. These modules are low
speed multiplexer 400 and system interface
Compatible with Ace device 100, as explained in the text
is given to the lines of interface 601.
A device that has the ability to intercept and execute commands.
Ru. The last group of modules is local memory
-Module and interface 603
Executes two different types of commands given to the line
Configure a main memory module capable of
Ru. The input/output system in Figure 1 is usually a high-level processor.
I/O in response to I/O commands issued by 700
Functions as a force subsystem. Port E and
F is the multiplexer or processor module in Figure 1.
installation to allow connection of any of the modules.
Contains an interface. These interfaces
The phase will be described in more detail below. For purposes of the present invention, the upper processor 700
is structurally known and described in U.S. Pat. No. 3,413,613.
The device may take the form described. desirable
In an embodiment, input/output processor 200
Channel program required to execute output instructions
Start and end the system interface device
Processes interrupt requests received from
Unit record connected to multiplexer 400
Control peripherals directly. The processor 200
data interface 600 and interrupt interface
Connect to port G via Ace 602. For the purpose of this invention, a low speed multiplexer 4
00 may be of known structure, and each
Various installation adapter interface (DAI)
low-speed peripherals through peripheral adapters that connect to
Provides a connection mechanism for side devices. This interface
base and adapter are assigned to the assignee of this invention.
Device configuration described in U.S. Pat. No. 3,742,457
You can also take Card readers are used for low-speed devices.
Includes printer, card punch, and printer.
Ru. As can be seen from Figure 1, the multiplexer 40
0 via programmable interface 601.
and connect to port J. The high speed multiplexer 300 is a channel adder.
Disks connected to each of the ports 303 to 306
Glue of devices and tape devices 309 to 312
Direct control of transfer effects between groups. each chiyane
controller adapters 303 to 306
is a channel adapter interface
(CAI) via the 300-1 interface line.
maximum for each channel port 0 to 3.
Can connect 16 devices. High speed multiplexer 3
00 is the data interface 600 and the
Programmable interface 601 and interrupt in
Connect to port A corresponding to Turf Ace 602.
Ru. For the purposes of this invention, each channel
The controller adapters 302 to 305 are structurally
The above-mentioned U.S. Pat. No. 3,742,457 may be considered to be publicly known.
Use the controller/adapter format described in
Good fit. system interface Processor 70 constructed in accordance with the principles of the present invention
0 and cutlet device 750 in detail.
Before doing so, each of the above-mentioned interfaces 600 to 600
Regarding Figures 5a to 5e regarding 604, the following
Explained below. First, in Figure 5a, the active module and
Between the system interface device 100
A device is an interface for exchanging information.
Various lines that make up the data interface 600
Disclose. This information exchange is called a “dialogue”
A predetermined signal organized through a series of signals called
The logical state of each signal line is controlled according to established rules.
It is done by doing. As can be seen in Figure 5a, this interface
is an active output port request line (AOPR).
and multiple SIU data lines (DTS00 to DTS35,
P0 to P3) and multiple SIU steering data lines
(SDTS0-6, P) and active request acceptance line
(ARA) and Data Read Acceptance Line (ARDA)
and data bus lines from multiple SIUs (DFS00
~35, P0~P3) and multiports from multiple SIUs.
from the SIU
Double precision line (DPFS) and acceptance status line
(AST). This interface
Lines are explained in more detail in the following sections.
Ru. data interface line Symbol Explanation AOPR active output port request line
Extends from module to SIU100
This is a one-way line. this line
When set, this
Module sends commands or data
to request a forwarding path to be sent.
signal. DTS00~35, P0~P3 data path line is 4 bytes
Width unidirectional path (4 to 10 bits)
(byte) for each active module.
and SIU, and each active module
command to SIU100 from
used to transfer data
Ru. SDTS0~6, P vs. SIU steering data line is active
Extends from module to SIU100
Ru. For these lines, the line AOPR is
When set, steering control information
Used to feed SIU100
Ru. The steering control information is marked as follows.
Encoded 7 bits and parity bits
It starts from Tsuto. That is, (a) The state of bit 0 indicates the DTS line.
shows the command format given to (directive
is a programmable interface
command or memory command) (b) Which module are bits 1 to 4?
receives and interprets memory commands.
is encoded to indicate
(The command is sent by the memory module.)
Interpreted and programmable
Interface directives are input/output
All modules except Sesa 200
). (c) The state of bit 5 is the command information.
1 or 2 words are the active modifiers of the requester.
Yule and requestee receiving module
should be transferred between files.
(1 word is single precision transfer, 2 words is
(instructs double-precision transfer). (d) The state of bit 6 is
module and the receiving module of the requested party
Indicates the direction of transfer between channels. (e) Bit P is included in SIU100.
requestor inspected by the device being
formed by the active module of
parity bit. MITS0~3,P 4 SIU multiplex port identifiers
The line is from the active module to SIU10
Extends to 0. These lines are active
Which subchannel within the module
Or the port is set to line AOPR.
encoded to indicate whether the
be done. Is the ARA active request acceptance line SIU100?
and extends to each active module. child
line is connected to the receiving module of the requested party.
is required for the active module.
data interface
Active module removed from circuit
to indicate that you have accepted the request.
It is being tested. The ARDA data read acceptance line is
Extends to the dynamic module. this line
is set by SIU100
So, is this the requested module?
You must accept the requested data before
Display the information. DFS00~35, P0~P3 Data lines from SIU are
On another set of data path circuits,
Extends from SIU to each active module
4 bytes with a unidirectional path
width (four 10-bit bytes)
Ru. The line in these sets is SIU1
00 is used to read the data
the specified one of the active module.
tell to. MIFS0~3,P 4 multiplex port identifier lines
Plus odd parity line is SIU10
0 to each active module
Ru. These lines are active modules.
Which port or subchannel of the file
is the previously read operation from SIU100.
indicates whether the data of the work should be accepted.
It is encoded as The double precision line from the DPFS SIU is
Extends to active module. This time
The state of the line is 1 of the read data.
or two words are active modules
The transfer contents (read instructions) are
(instruction) is completed. AST acceptance status lines are available from SIU100 to each active
Extends to module. mutual line
The state of this line without ARDA
is for this active module,
status information given to the DFS line.
Signal that something should be accepted. The programmable interface shown in Figure 5b
Ace 601 lines are one active module
Transfer command information from the specified module.
conduct. This transfer is a series of calls called dialogues.
according to predetermined rules organized through the signals of
to control the logical content of the state of each signal line.
It is done by folding. This programmable interface
Ace commands programmable interface
Acceptance Circuit (APC) and programs from multiple SIUs
System-enabled interface data line (PDFS00
~35, P0~P3) and programmable interface
Ace available line (PIR) and data transfer request
Read line (RDTR) and multiple SIU programs
Programmable Interface Data Line (PDTS00
~35, P0~P3) and acceptance data read line
Contains (RDAA). This interface
The lines will be explained in more detail below. programmable interface line Symbol Explanation APC Programmable Interface Finger
Order acceptance lines receive each from SIU100
Extends to the opposite module. This time
When the line is set, the command information is
SIU has established this interface.
This module given to the PDFS line
model to be accepted by the model.
Signal to Juul. PDFS00~35, P0~P3 Programmable from SIU
function interface data line
From SIU100 to each module
A 4-byte wide unidirectional path that extends
(four 10-bit bytes)
Ru. These lines are designated by the SIU.
program for the received receiving module.
Provides RAM-enabled interface information.
I can do it. Using PIR programmable interface
Possible lines are from each module to SIU
extend. This line is set
Then, the module contributes to the line PDFS.
ready to accept the directives to be given.
Show that something is true. PDTS00~35, P0~P3 vs. SIU programmable
The interface data line
Extends from module to SIU100
A 4-byte wide unidirectional path (4
(one 10-bit byte). child
These lines are programmable interfaces.
To transfer face information to SIU
used for. The RDTR data transfer request read line is
connected to the RAM-enabled interface.
from each module to SIU100
extend. This line is set
the previously requested read data.
data is transferred to one module.
module for line PDTS.
show that it was given by
Ru. RDAA acceptance data read line is from SIU
Extends to each module. this line
is set, the line is PDTS
that the data given has been accepted.
, and this module is
information can be removed from the line
This is displayed for the module.
Ru. Yet another interface is the input/output processor.
Interrupt processing in Figure 5c with interrupt handling by 200
It is an interface. That is, this interface
Ace is interrupt information by some active module.
for processing, along with forwarding to SIU100.
For input/output processor 200 by SIU 100
Enables transfer of interrupt information. Other interfaces
Similar to Ace, this interrupt request forwarding is
Organized through a series of signals called "earlogs"
The logic of each signal line according to predetermined rules
This is done by controlling the target state. This interface is the interrupt request line.
(IR) and multiple interrupt data lines (IDA00~
11, P0~P1) and connected to ports A~L
Multiple interrupt multiple port identification for modules
Contains child lines (IMID00-03). Port G
For modules connected to
The interrupt interface of
line (LZP) and higher level interrupt present line
(HLIP), Interrupt Data Request Line (IDR),
Release line (RLS) and multiple active interrupt levels
AIL lines (AIL0-2) are included. Figure 5c?
As you can see, the interrupt interface port
G and H include interrupt multiple port identifier lines
do not have. About this interrupt interface line
is further explained below. interrupt interface line Symbol Explanation The IR interrupt request line is connected to each module.
Extends to SIU100. this line
When set, it requires service.
Show the SIU what you are looking for
do. IDA0~3, P0 This data interrupt line is active IDA4~11, extended from P1 module to SIU100
Exists. These lines require an interruption.
request is accepted by the input/output processor.
transferred to this processor when
code to include control information that should be
be converted into These bits are listed below.
It is encoded as follows. That is, (a) The state of bit 0 is
which processor (i.e., processor number)
) should handle this interrupt request.
SIU100. (b) Bits 1-3 are SIU100.
Priority or level of interrupt requests for
coded to display the bell number.
ing. (c) Bit P0 corresponds to bits 0 to 3.
It is a parity bit. (d) Bits 4-8 handle interrupts.
To check the appropriate procedures for
Formed by input/output processor 200
I'll give you part of the address that should be sent.
(i.e. interrupt control
block number ICBN). (e) Bit P1 becomes bits 4 to 11.
It is a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit of a bit. IMID00~03 This interrupt multiple port identifier line
is 100 SIU from each active module
Extends until. These lines are active
Which specific subchannel of the module?
has requested interrupt service.
It is encoded for identification. LZP Is this level zero existence line SIU100?
Extends from input/output processor 200
Ru. Once this line is set up,
The highest priority (level 0 interrupt) is
SIU100 changes to processor 200
indicates that it is directed towards
Ru. Interrupt-present lines higher than HLIP are
Extends from SIU to I/O processor
Ru. Once this line is set up,
Hands executed by processor 200
a higher level than a process
An interrupt request with priority
Show that. IDR This interrupt data line is used by input/output
Extends from SA200 to SIU100
Ru. Once this line is set up,
Interrupt data is generated by SIU100
sent to the processor on the line DFS.
Show what should be done. RLS This release line is input/output processor 2
It extends from 00 to SIU100. child
Once the line is set up, the
The server 200 has completed execution of the current step.
Display what has been done. AIL0~2 Is this active interrupt level line SIU?
Extends from input/output processor 200
Ru. These lines are connected to the processor 20
Interrupt record for procedures executed by 0
coded to display the bell number.
ing. Used by some of the modules in Figure 1.
The next set of interrupt lines that are
Corresponds to the Molly interface line. this
Local memory interface 603
Between the memory 500 and each module of this system
exchange of information. This exchange operation is
Organized through a series of signals called "earlogs"
Interconnect each signal according to predetermined rules.
By controlling the logical state of the face line
It will be done. This local memory interface
connects multiple memory-to-memory data lines (DTM00~
35, P0 to P3) and multiple memory-to-memory request identifiers
Lines (RITM0-7, P0-P1) and multiple paired notes
Lee designated lines (SLTM0-3, P) and PI command receiving
Acceptable line (APC) and ZAC directive accepted line (AZC)
, data transfer request read line (RDTR), and
data line from memory (DFM00~35,
P0 to P3) and request identifiers from multiple memories
From the line (RIFM0~7, P0~P1) and memory
double precision line (DPFM) and QUAD line, and acceptance
Data read line (RDAA) and system clock
Contains the Tsuku line (SYS-CLK). Memory and programmable interface
The commands are based on the same physical data on the interface.
transferred from the line. This interface is
Contains one set of lines for handling interrupt requests.
First, the SIU100 connects to the local memory.
Each connected module directly attracts memory interrupts.
I can't wake it up. This local memory input
The Turf Ace line is explained in more detail below.
I will clarify. Local memory interface line Symbol Explanation DTM00~35, P0~P3 This data route line is 4
Byte-width unidirectional paths (36
Information circuit and 4 odd parity circuits
line) and local from SIU100
Extends up to 500 memories. These etc.
Line can be memory or programmable
Local memo of function interface command
to transfer to Lee 500
used. RITM0~3, P0 vs. memory request RITM4~7, P1 data identifier line is SIU100
Extends from 500 to local memory
Configuring 4 lines in 2 groups
Ru. These lines initiated the command
Local memory that identifies the module
encoded to convey information to
the requested data in the correct module.
used to return against Yule
Ru. SLTM0~3, P The memory specified line is SIU
Extended from 100 to local memory 500
with two port number selection lines
and memory read/write lines
, double-precision line to memory, and
Includes retail line. These lines
The information signal obtained is coded as shown below.
be converted into That is, (a) Bits 0-1 indicate the connected
Which port or subchannel within the module
Jannel for this module
Receives sent memory commands
I'll tell you how to interpret this.
Port number selection bit encoded in
It's Tsuto. (b) Bit 2 is a new directive.
Sent to memory by SIU100
Local memory 500 by SIU when
received from active modules sent to
Memory-related information included in the steering control information
– read/write bit. child
The state of the bit indicates the direction of data transfer.
Display. (c) Bit 3 indicates the data to be transferred.
encoded to specify the amount of data.
double-precision bit vs. memory
Ru. This bit is also a new directive.
is sent to the memory module
local memory by SIU100
– functions sent to the module.
Steering provided by dynamic modules
Included in control information. AZC ZAC command acceptance line is from SIU100
Extends to the main memory module
Ru. Once this line is set up,
Local memory module 500
On the other hand, SIU100 is applied to other lines.
ZAC command and control information available
signal acceptance. This i
Setting up the interface line
are mutually PI command interface times.
Exclusive to line acceptance lines. APC programmable interface and
Program as described in connection
Possible interface command acceptance line
is the local memory module from SIU100.
Extends to 500 yen. This time
Once the line is set, the line DTM
The command information given to the local memory
- Accepted by Module 500
Display what should be done. PIZ/ZIR This programmable interface
Usable line/ZAC interface
Ace usable line is local module
Extends from LE 500 to SIU 100
Ru. Once set up, each line
The memory module 500 is
programmable interface
(PI)/memory (ZAC) command is received.
SIU confirms that it is possible to accept
Signal 100. The RDTR data transfer request read line is local
Molly Modille 500 to SIU
Extends to 100. This line is
If the
The requested read type before
The data in the module that requests the data
Necessary control information to be sent to Yule
Show what you get with the information. DFM00~35, P0~P3 Data times from memory
The line is local memory module 5
4 bars extending from 00 to SIU100
It is a unidirectional bus with a width of 1.5 cm. child
These lines are read type data
active module via SIU100.
used to return to the RIFM0~3, P0 2 groups of notes RIFM4~7, P1 Rixter identifier times from Lee
The line is local memory module 50
Extends from 0 to SIU100. this
etc. lines are from module 500.
Conversely, it is read by the requesting module.
encoded to direct the data
It can be done. Double precision times from DPFM and QIAD memory
lines and QUAD lines are local memory
-Module 500 to SIU10
Extends to 0. These lines are
output data transfer request time interval.
SIU for the requesting module
100 to be transferred via
encoded to display the number of
Ru. These lines are encoded as follows
be done. That is, QUAD DPFM 0 0 1 word, single precision 0 1 2 words, double precision 1 x 4 words (Anything is fine) The DSD read data/status identifier line is
From memory module 500
Extends to SIU. The state of this line
is when line RDTR is set,
Information given to line DFM is read
SIU100 for data or status information
signal. This line is set
1 word or 2 words
(QUAD=0) status information is being transferred
. this line
is reset to binary zero,
Up to 4 words of data are being transferred.
This word signals that there is
The number is the sign of the line QUAD and DPFM
Specified by Related to RDAA programmable terminals
Accepted readout as described
The data line is localized from SIU100.
Extends to memory module.
Once set, this line
memory module
- The data given on the face is
acceptance and that this local
Molly Mojiur has provided this data.
etc. that can be removed from the line
signal to the memory module.
do. SYS-CLK This system clock is
Each module of this system from 100
The line extends all the way to the station. this line
is included in the input/output processor 200.
connected to a common clock source.
Is it an expert system clock source?
Function of each memory module
Sync. Between the cutlet device 750 and the central processing unit 700
The last used as an internal interface between
The interface line of the set is shown in Figure 5e.
Corresponds to the cutlet/CPU interface line.
Ru. This interface 604 is connected to the processor 7
00 and the cutlet device 750.
exchange control signals. This exchange action is
Controlling the logical state of an interface line
This is done by Katsushie/CPU interface
The base is connected to multiple processor-to-processor data lines (ZDI0
~35, P0~P3) and multiple ZAC and write data
data lines (ZADO0~23, RADO24~35, P0~
P3) and the processor request signal line (DREQ-
CAC) and multiple cutlet command lines (DMEM0~
3) and the hold cutlet line (HOLD-C-CU)
, central line (CANCEL-C), and flash
line (CAC-FLUSH) and read request line
(RD-EVEN) and read command buffer line
(RD-IBUF) and read data buffer line
(DRDB) and the initial setting pointer line (INIT-
IBUF), multiple command lines (ZIBO-35), and
address pointer line (ASFA-M32-
33), control line (DSZ), and readout I-button
A data line (RD-IBUF/ZDI) and multiple
Zone bit line (DZD00-33) and bypass
communication line (BYP-CAC) and write communication.
number line (WRT-SGN) and command line (WRT-SGN) and command line (WRT-SGN)
(IBUF-EMPTY) and the number of times the instruction buffer can be used.
line (IBUF-RDY) and command buffer complete line
(IBUF-FULL) and CP stop line (CP-
STOP) and CP control line (DATA-RECOV)
Contains. Instructions, Katsushie directives, and data are
are sent to the cutlet device 750 via each of the lines.
It can be done. Furthermore, the operation of processor 700 is not explained in the text.
Used by some of these lines as specified
Enabled or disabled. CP/Katsushi
Further details regarding the E-Interface line are provided in the main text.
Explain in detail. CP/Katsushie Interface Line Symbol Explanation DREQ-CAC This line is from processor 700
It extends to the cutlet device 750.
DREQ-CAC set to binary 1
When the ZAC command is
Transferred to 50. writing
In case of ZAC directive, write data
The word is 1 or 1 after the ZAC command.
Transferred in 2 cycles, the data
The code has been modified from processor 700.
Through Katsushie 750 without
Sent to SIU100. DMEM0, 1, 2, 3, these lines are
Extended from Sa700 to Katsushie750
do. These lines are Katsushi 7
50 will display the commands to be executed.
It is encoded. Encoding content
is as follows. That is, DMEM=0100 0-3-address
Circulation command (ADD-WRAP)
The dress circulation command consists of two cycles.
executed. Start of the first cycle
Sometimes the data and command information is
750. next black
The processor 700
It is turned off. second rhinoceros
In the computer, the processor is ON.
state and at the end of this cycle
The data given to this processor is
Available for processor 700
state. DMEM=0100 0-3-load life
Command retrieval 1 (LD-
IBUF−IF1) This load instruction is
A fire command is executed in one cycle.
It can be done. At the beginning of this cycle, add
Response and command information is on Katsushie 750
be transferred. end of this cycle
the block specified by the address.
If tsuku is specified before the command
At the instruction buffer address
written and addressed to this
Words are programmed via ZDI lines 0-35.
The data is transferred to the processor 700. DMEM=0101 0-3-load life
Command retrieval 2 (LD-
IBUF−IF2) This load command is
Hua directive in one cycle
executed. beginning of this cycle
The address and command information is
750. this cycle
at the end of the said address.
The block to be executed is before the instruction buffer.
The instruction buffer address specified in
written to the DMEM=0110−Lord Quats
This road quad is one sample.
Executed in cycle. IF2 and
Similar, but the data is
Go to another part of. DMEM=0111 0-3-read ahead
(PR-RD) This read command is the minimum
execute in a variable number of cycles, which is 1 at
be done. At the beginning of the first cycle, the address
The command information and command information are
will be forwarded to. This first cycle
, the specified address is
Block ad on Tsushie 750
When there is a response, the read-ahead operation stops.
However, no other actions are taken. If a
The block specified by the dress is cut off.
If it is not in E750, the first cycle
At the end of the file, this request is sent to main memory.
be transferred. the requested block is
When read from main memory, the data
The data is stored in the cutter 750. DMEM=1000 0-3-single read
command (RD-SNG) single read finger
An instruction is executed in one cycle.
At the beginning of this cycle, the address
and command information is given to Katsushi 750.
data at the end of this cycle.
processor is available for use with processor 700.
Ru. DMEM=1001 0-3-readout
Rear (RD-CLR) read clear finger
The command is a variable number of cycles with a minimum of 9
executed. Beginning of the first cycle
The address and command information should be
transferred to a storage device, and this processor
It will be in the OFF state. second cycle
During the
When the card is held in the cutlet, this
The word is taken from Katsushi 750
be done. the requested word is in main memory
The cutlet 750 is read out from the device.
When transferred to
become a state. DMEM=1010 0-3-2 times parsimonious number
Read command (RD-DBL-φ) (line
DSZ is a binary number zero) This double odd number readout
The command is executed in two cycles.
will be carried out. At the beginning of the first cycle
The address and command information is
It is transferred to the server 750. First service
At the end of the cycle, the odd address
Word can be used on processor 700
becomes. At the end of the second cycle
means that even-addressed words are processed
It becomes available for use. DMEM=1010 0-3-2 times even number
Read command (RD-DBL-E) (line
DSZ is binary number 1) Read this twice even number
The command is executed in two cycles.
will be carried out. At the beginning of the first cycle
The address and command information is
It is transferred to the server 750. First service
At the end of the cycle, the even address
Word can be used on processor 700
becomes. Odd at the end of the second cycle
Words of several addresses are processed by processor 70.
It becomes available for use at 0. DMEM=1011 0-3-Remote reading
Remote reading command (RD-RMT)
The command is a variable number of cycles with a minimum of 10.
executed in number of files. first cycle
At the beginning of the
The information is transferred to the cutlet 750.
At the end of the first cycle, the request is
transferred to the storage device and processed by the processor 70
0 is in the OFF state. requested
word pairs are retrieved from memory.
After that, the processor 700 is turned on.
data is available to this processor.
Becomes Noh. DMEM=1100 0-3-single write
Single write command (WRT-SNG)
Commands are executed in two cycles
be done. At the beginning of the first cycle
The address and command information is
It is transferred to the server 750. second sa
At the beginning of the cycle, the data is
750. second rhinoceros
During the kuru, if addressed
Blocks containing words are cutlet 7
50, the data is
It is written to the cutlet 750. Second
At the end of the cycle, write requests and
and data are transferred to main storage.
Ru. DMEM=1110 0-3-2 times writing
Double write command (WRT-DBL)
The command is executed in three cycles
Ru. At the beginning of the first cycle, the ad
Response and command information is available at Katsushi 75
Transferred to 0. Second (third) service
At the beginning of the cycle, the even (odd)
Ta word transferred to Katsushie 750
be done. During the third cycle, if
Contains the addressed word pair
The block is memorized in Katsushi 750.
If so, the data will be written to Katsushie.
be included. End of the third cycle
Write requests and both data
code is passed to main storage
It turns out. DMEM=1111 0-3-Remote writing
Remote writing command (WRT-RMT)
Commands are executed in three cycles
be done. At the beginning of the first cycle,
The address and command information are
750. first cycle
At the end of the process, the request is transferred to main storage.
sent. In the next two cycles
and the two data words are cut.
Transferred to Cie 750, this cutlet
Shie further transfers this to main memory
do. HOLD-C-CU Is this line processor 700?
It extends from Katsushie 750. binary
When set to the number 1, this control signal
The number is requested by Katsushi 750 or provided as data.
Should be in HOLD state for data transfer.
to instruct people. CANCEL-C This line is from processor 700
Extends to Katsushi 750. binary number
When set to 1, this control signal
Would you like to be made into Katsushi 750?
The request will also be terminated. CAC-FLUSH This line is from processor 700
Extends to Katsushi 750. binary number
When set to 1, this line
Start flashing Tushie 750.
Ru. RD-EVEN This line is connected from processor 700 to
It extends to Tsushie 750. cutlet
makes a double word request to the SIU.
, even words are special registers.
Stored at. RD-EVEN
When the line is set to binary 1,
The contents of this register are input to the ZD1 line.
will be exported. ZADO, 0-23 One of these 40 RADO, 24-35 tropic lines are processor Extends from P0 to P3 700 to Katsushie 750
do. These lines are subject to the ZAC directive.
and write data word.
used to transfer to E750.
Ru. RD-IBUF This line is connected from processor 700 to
It extends to Tsushie 750. binary number 1
When set to
According to the state of the line DRDB as follows:
instruction buffer to process the instructions of
increment the out pointer
Ru. DZD0~3 These 4 lines are processor 700
It extends from Katsushie 750. child
These lines are used because of the double write command.
The odd word zone bit is
send BYP-CAC This line is connected from processor 700 to
It extends to Tsushie 750. binary number 1
When set to
Type instruction for cutlet 750
data word from main memory to
make demands. WRT-SGN This line is connected from Katsushie 750.
Extends to Rosesa 700. this is,
During the write command, Katsushi 750
NAC directive and SIU100 data
to confirm that the transfer of the data word has been completed.
used to signal processor 700.
used. ASFA32~33 These two lines are processor 700
It extends from Katsushie 750. child
These lines are INIT
Hardware control via IBUF line
When initialized under control, the processor
I buffer to be read to 700
the next word of the block stored in
is encoded to specify
Ru. INIT−IBUF This initial setting command buffer command
is executed in one cycle. child
At the end of the cycle, the pointer's buffer is
The buffer is reset to zero and the buffer is reset to zero.
A out pointer loads its initial value.
is coded. DSZ1 This line is cut from processor 700.
Extends up to 750. of this line
The state is that a double read command is executed.
The time word is sent to processor 700.
The order in which the
Specify. DRDB100 This line connects processor 700 to
It extends to Tsushie 750. this is,
Top of read address of I buffer
Used as a bit. RD-IBUF/ZDI Is this line a processor 700?
It extends from Katsushie 750. this
I use Katsushie 750 and connect ZIB line.
Give the above data to the ZDI line
Ru. ZDI0~35 One of these 40 P₀,P₁,P₂,P₃ Is the tropic line Katsushie 750?
It extends from the processor 700 to the processor 700. this
etc. from Katsushi 750 to Processor 7
Give data to 00. ZIB0~35 One of these 40 pieces P₀,P₁,P₂,P₃ Is the tropic line Katsushie 750?
It extends from the processor 700 to the processor 700. this
etc., can be downloaded from the cutlet command buffer.
A command is given to the processor 700. IBUF-EMPTY Is this line Katsushie 750?
It extends from the processor 700 to the processor 700. binary
When set to number 1, this line becomes
At this point, the command is
Show that you don't have it. IBUF-RDY This line is connected to the cutlet 750.
Extends to Rosesa 700. binary number 1
When set to
Bathua has at least one command.
Show what to do. IBUF-FULL This line is from Katsushie 750
It extends to the processor 700. This time
The line is a line with 4 or more orders.
or with at least one command.
Has an outstanding instruction fetch request line
Show that. CP STOP This line is connected from Katsushie 750.
Extends to Rosesa 700. binary number 1
When forced to
Special information detected in device 750
As a result of the conditions, cutlet device 7
While 50 resolves this special condition,
The processor 700 waits for the operation or
Signals that a stop is required. DATA-RECOV Is this line Katsushie 750?
It extends from the processor 700 to the processor 700. this
responds to the detection of cutlet error conditions.
In response, following the termination of processor 700,
to restrove the processor's registers.
used to block. 5a to 5e show processor 700 and
In addition to connecting to cutlet device 750, SIU100
For the different modules of the system in Figure 1,
Although the various lines to be connected are shown, there are also other conditions,
e.g. to signal certain error conditions and operating conditions.
As you can see, other lines are also included.
cormorant. Further details on the various modules shown in Figure 1
See US Pat. No. 4,000,487. Then
About Rosesa 700 and cutlet device 750
A more detailed description will be provided. FIG. 2 General description of processor 700 In FIG. 2, the upper processor 700 executes
Control device 701, control device 704, and execution device
714, character device 720, and auxiliary arithmetic control device
(AACU) 722 and a multiplication/division unit 728.
These devices are interconnected as shown.
I understand that. Furthermore, the control device 704 is configured as shown in the figure.
Has a large number of interconnections to the cutlet device 750.
do. The execution control device 701 is an execution control store address.
response preparation/branching device 701-1 and execution control stream
701-2. Store 701-2 and
Device 701-1 connects buses 701-3 and 7 as shown.
They are interconnected via 01-6. The control device 704 includes a control logic device 704-1;
Control store 704-2 and address preparation device 70
4-3 and data and address output circuit 704
-4 and XAQ register section 704-5
and which are interconnected as shown in the figure.
Ru. As you can see from Figure 2, the SIU interface
600 is a large number of inputs to the cutlet device 750
provide a line. Lines of this interface
was explained in detail earlier. However, Katsushi
Regarding the operation of the device 750,
In particular, the following is encoded: Immediately
Chi, 1 MITS0 to 3 for reading are marked as below.
coded. Bit 0-1 = 00 Bits 2-3 = Read ZAC Buffer Add
For non-responsive write operations, bits 0-3 = odd.
Several word zone. 2 MIFS lines are encoded as follows.
That is, bit 0=0 Bit 1 = 0 Even word pair (word 0,
1) Bit 1 = 1 Odd word pair (word 2,
3) Bits 2-3 = ZAC x for memory
Hua Address Interface line DFS00~35, P0~P3
, these lines do not capture read data.
It is transmitted to the Tsushier device 750. Line DTS00~
35, P0 to P3 from Katsushie 750 to SIU100
Used to transfer data. The controller 704 performs address preparation operations and instruction fetch operations.
eject/execute operations, and each operation cycle and (or
) required for sequential control over machine states
control. This control is performed by block 704-1.
For each part of the logic circuit and control device 704
Generated by execution controller 701. XAQ register section 704-5
Standard register, accumulator register, commercial register
Many program-visible registers such as
Contains. See Figure 3 for this section.
will be explained in more detail. Instruction counter and
and other program bits such as address registers.
The register is address preparation device 704-3.
contained inside. As can be seen from Figure 2, section 704-5
is sent from device 704-3 via line RIC00-17.
Receives a signal indicating the contents of the command counter. Also, the line
ZRESA00−35 is performed for various operators.
An output signal is sent from the execution device 714 in response to the calculated result.
give a number. Also, section 704-5 is the line
Output from the auxiliary calculation/control unit via RAAU0~8.
Receives force signal. Section 704-5 is address preparation device 7
In the same section as one input for 04-3
give a signal indicating the contents of one of the included registers
Ru. Address preparation device 704-3 stores this information.
Execution device 7 via line ZDO0~35
Send to 14th. Similarly, in section 704-5
The contents of some of the registers included are
Transfer to execution device 714 via ZEB00~35
I can do it. Finally, select these registers.
The contents of the contents are from section 704-5 to the line.
It is sent to the multiplication/division unit 728 via ZAQ00-35.
I can do it. This includes address preparation device 704-3.
Generates an address from the contents of various registers and connects it to the line.
ASFA00~35 allows it to be distributed to other devices.
The resulting logical effective address and (or absolute address)
Give a dress. Address preparation device 704-3
is connected to the execution device 714 via lines ZRESB00 to 35.
The result of the operation performed on a pair of operators by
Receive. Device 704-3 connects lines RBASA and
Control logic unit 701 to 1 via RBASB0 to 1
A signal indicating the contents of the pair's base pointer register.
Receive. The output from the multiplier/divider 728 is the address
is provided to reference device 704-3. Finally, the second
The contents of the instruction register (RSIR) are line RSIR00 to 35.
provided as input to device 704-13 via
available. The data and address output circuit 704-4 is
Cutlet device via line RADO/ZADO00~35
Katsushie memory address given to 750
generates a signal. These address signals are
The switches built into the various circuits of Tsuku704-4
Input lines ZDI00~ that form the set selected by
35, one of ASFA00~35 and ZRESB00~35
corresponds to the given signal. Also, word address
The signal is provided via lines 32-33. These etc.
The circuit is explained in more detail in the main text.
Ru. The control logic device 704-1 is a cutter device 75.
interface with each device contained within 0
update in the main tree, providing a data path with
Lines ZIB00~35 are cut off as detailed in
An instruction buffer built into the driver 750
provide an interface. Line ZDI00−35 is
From Tsushie 750 to control logic device 704-1
Used to transfer data signals. other signals
Other than Katsushi-CP interface 604
Provided via data and control lines.
These lines are shown separately in CP
Including STOP line. As can be seen from FIG. 2, control logic unit 704-
1 gives many groups of output signals. These etc.
The output signal of, for example, its content is the line RBIR18~
27 to control store 704-2 and
The basic instruction register (RBIR) given by
Contains the contents of certain registers. control logic
The station 704-1 is controlled via lines CCSDO13 to 21.
A certain control signal read from store 704-2
Receive. Control logic 704-1 also processes certain instructions.
loaded in parallel with the basic instruction register at the beginning of
Contains the secondary instruction register (RSIR). aforementioned
The contents of the secondary instruction registers RSIR00 to 35 are as follows.
As input to address preparation device 704-3
Given. Furthermore, one of the contents of the secondary instruction register
The section is auxiliary via lines RSIR1-9 and 24-35.
Provided as an input to the arithmetic and control unit 722
Ru. control store 704-2 as described in the text.
performs the initial decoding of the program instruction OP code.
Therefore, each possible instruction OP code
It has many storage locations (1024 locations) with
It is composed of As mentioned above, the signals given to lines RBIR18-27
The code is given as input to control store 704-2.
available. These signals have 1024 possible storage locations.
Select one. The contents of the selected storage location are
As shown in Figure 2, lines CCSDO13 to 31 and
Given to CCSDO00−12. Line CCSDO00−
12 is implemented as described in the text.
used to address row controller 701.
corresponds to the address signal that is input. For the remaining sections of processor 700,
A brief explanation follows. The execution unit 714 executes instructions.
In this case, the same device 714 performs a row from each input.
Perform operations and/or sequences for selected operators.
Perform soft operations. The result of such an operation is
is given to the output side. The execution device 714
control logic 704-1 as a source of
Data input buses corresponding to lines RDI00-35
Receive data. Built into section 704-5
Contents of the accumulator register and quotient register
is executed by the execution device via lines ZEB00~35 as described above
714. Address preparation device 704-
3 to the input bus line ZDO00~35.
The number is the line ZRESA00-35 and
Execution device as output signal for ZRESB00~35
714 through a built-in switch.
Ru. Furthermore, the execution device 714 connects lines ZRSPA00 to
Auxiliary computing/control unit 722 provided via 06
receives a set of scratchpad address signals from
take. Furthermore, the same device 722 is connected to the line ZRSC00~05
Shift information is provided to device 714 via. Character device 720 translates data fields.
and character type commands that require operations such as editing.
Used to execute commands. explain in text
As such, these types of instructions are part of the extended instruction set.
(EIS) instruction. Character device 720 executes
Such instructions to do are move, scan, compare type
Contains instructions for The signal indicating the operator is a line
Given through ZREA00~35. one word
Regarding the type of character position and number of bits in
Information is sent to the character device 72 via input lines ZPB00~07.
given to 0. Information indicating the result of a certain data operation is
It is provided to device 722 via ZOC00-08.
Such information includes exponential data and hexadecimal data.
Including data. The character device 720 has lines RCHU00 to 35.
Output operator data and control information through the device
722 and device 728. The auxiliary calculation/control unit 722 performs floating point calculations.
calculations on control information such as exponents used in
calculate the length and pointer of the operator, and
Generate mount information. The result of such an operation
As mentioned above, the line ZRSPA00~06 and the line
Provided to the execution device 714 via ZRSC00~06
Ru. Character input such as 9-bit characters and 6-bit characters
Decimal data converted from hexadecimal data, quotient
Information and information signals corresponding to code information, etc.
Section 704-5 via lines RAAU00-08
given to. As can be seen in FIG.
receive power. Character pointer information is from line ASFA33
Given through 36. EIS digit shift information and
Alphanumeric field length information is for lines RSIR24-35
to device 722 via. of a specific command
Other signals related to retrieval are via lines RSIR01~19.
It is given as follows. Exponent for floating point data
The signal is applied to the device 722 via lines ZOC00 to 08.
floating point finger from device 704-1.
Number data is provided via lines RDI00-08.
Shift for a certain instruction (e.g. binary shift instruction)
Count information signals are sent via lines RDI11 to 17.
provided to said device. Give to line RCHU00~35
For input signals that are
Give a signal corresponding to the length of the command field and
18-23 give address change signals to device 722;
Ru. The last device is a multiplication/division device 728, which handles multiplication/division instructions.
Perform fast execution. This device is of a known structure.
It may be assumed that the invention is assigned to the same assignee as the invention.
Multiplier type described in U.S. Pat. No. 4,041,292
It's good to stay calm. As can be seen from FIG.
8 is the multiplier, dividend and
and divisor input signals. register section
Multiplicand input signal from 704-5 is line ZAQ00
~35 given through. carried out by device 728
The calculation result is the output for line ZMD00~35.
given as a signal. As mentioned above, the cutter device 750
Data and
Transfers control signals to SIU100 and receives them
Ru. The cutlet device 750 has an interface 6
Data and control signals are routed through 04 lines.
The data is transferred to the processor 700 and received. last
Then, the cutlet device 750 connects the line RADO/
circuits via ZADO00~35 and lines ASFA32~33.
receives address and data signals from line 704-4.
take. Detailed description of processor 700 Each sector including processor 700 shown in FIG.
With regard to Figures 3a to 3i, the following
Discussed in further detail below. In Figures 3a and 3b, this process
The controller has two control stores: (1) controller 704;
The control store of the control unit that forms part of the
(CCS) 704-200 and (2) execution control device 70
Execution control store (ECS) 701 built in 1
-2 is included. Understand how control store devices work
Therefore, the three-stage pipeline of the processor 700
It would be useful to briefly discuss this. this thing
to complete the given program instructions
requires at least three processor cycles;
and issue a new command at the beginning of each cycle.
It means that you can. In this way, many instructions can be
is also in a certain stage of processing. This three-stage pipeline
Configuration includes instruction interpretation, CP code decoding and add-on
The instruction cycle (I) in which response preparation is performed, and the
The device 750 is accessed
A cycle (C) and an execution cycle where instructions are executed.
Contains cycle (E). Regarding control, I cycle
of commands given via lines RBIR18-27.
The place in control store 704-2 is created using the OP code.
access the location. During the C cycle, the control string
The content accessed from A704-2 is
Given to CCSDO00~12 and further execution control store
701-2 to access one of its storage locations.
used. During the C cycle, the execution of this instruction
The microinstructions of the microprogram used are
144-bit output from execution control store 701-2
It is read out to register 701-4. MEMDO00~
The signals displayed as 143 correspond to each function of the processor 700.
distributed to devices. During the E cycle, the processor
Performs operations specified by microinstructions. In particular, in FIG. 2, control store 704-2 is
The OP code signal given to line RBIR18-27
controller store addressed by
(CCS) 704-200 included. As mentioned above,
The CCS704-200 operates during I-cycle operations.
The contents of are read into the output register 704-202.
It has 1024 memory locations. Figure 6a shows the control
Format of words stored in stores 704-200
It shows. In Figure 6a, each controller control store
A word has five fields. first fi
field is a 13-bit field, line RBIR18
For instructions with an OP code given to ~27
Contains the ESC start address location. next file
The field is a 3-bit field (CCSφ).
Control operations. Bit interpretation of this field
is its destination, and this is decoded by a particular circuit.
or decrypted under microprogram control
Depends on the crab. The next field is a 4-bit field.
Perform certain register control operations in the field. The next field is a 6-bit sequence control field.
Yield, hard with cutlet operation type
A series of operations to be performed under the control of the software logic circuit.
It is encoded to specify the operation. In this example,
field is 75₈is encoded in Last
The field is a 6-bit indicator field.
This is not relevant to the understanding of the present invention. As can be seen in Figure 3a, the controller control store
The signal corresponding to the CCSA field of is route 704
-204 to the execution start circuit 701-7.
given as input. CCSR field
The corresponding signals are sent to the execution device via paths 704-206.
is provided as an input to position 714. Furthermore,
The signal is added via another path 704-208.
given as input to the response preparation device 704-3.
It will be done. The signal indicating the sequence control field is
Sequence control logic circuits via lines 704-210.
given as input to path 704-100.
Ru. As explained in the text, these circuits
decoded using the ance control field, and
To condition 0 and perform the specified operation
generate a signal. As previously mentioned, the execution address generation circuit 70
1-1 is a field from control store 704-2
Receive CCSA and corresponding input address. 3rd b
As can be seen from the figure, these circuits have an output of 4
Connect to the 1st position of position switch 701-12ZECSA.
input address register 701-10
include. The output of this switch is the control store 701-
Acts as an address source for 2. vinegar
The first position of Itsuchi 701-12 is MICA Regis
Connected to receive address from data controller 701-14.
be done. The contents of register 701-14 are
is updated at the end of the cycle and its contents are updated during that cycle.
in the ECS control store
Indicate the location. The second control is the ZCSBRA branch address select.
Address generated from Kuta switch 701-18
Select. The third position is REXA register 70
By CCS control store loaded in 1-10
In each given microprogram, the first
Select the address of the microinstruction. CCS output
is not obtained at the end of the microprogram, the
The predetermined address (octal address 14) is automatically
selected. The first position of branch switch 701-18 is
read from register 701-2 to register 701-4.
Furthermore, the amount sent to the return control register 701-20
Receives a signal corresponding to the branch address. switch 7
The 2nd, 3rd and 4th positions of 01-18 are the RSCR record.
Register 701-20, MIC register 701-15
signals from and a number of vector branch registers 7
Receive the contents of 01-36. MIC register 701
-15 is the master following the microinstruction word being executed.
Memorizes the address that specifies the macro instruction word.
Ru. This address is determined by the increment circuit 701-12.
from switch 701-12 incremented by one.
Corresponds to the address. The vector branch register is a 4-bit vector.
Branch register 0 (RVB0) and 2-bit vector
branch register 1 (RVB1) and a 2-bit vector
Contains Tor branch register 2 (RVB2). These
The registers are input multiplexers for many groups.
selector circuits 701-32 and 701-3
A large number of different images given as input to 4.
Stored in indicator flip-flops and registers
The address value obtained from the signal
loaded during the cruise. Circuit 701-32 and
The output of 701-34 is a two-position selector circuit 70.
1-30. These etc.
The circuit is further stored in register 701-36.
Generate output signals ZVBR0, ZVBR1 and ZVBR2
Ru. The switch 701-36 is used for various hardware
indicator signal, via the INDGRP field.
Inspection of state flip-flop signals selected by
gives an address based on . The decision to branch is made by Mike.
INDMSKU and INDMSKL files in the instruction word
Selected indicator set using field
determined by masking (ANDING) the data.
determined. If the vector branch is chosen
For example, INDMSKU is treated as 4 zero bits.
8-bit “OR” is TYPG and GO micro
relative to the state specified by the instruction field.
compared. This hardware signal contains a large number of
selector circuit 701-28 (one of them
(only shown) and the output of said circuit is
Yet another 5-position multiplexer/selector circuit
701-26. Ma
The output of the multiplexer circuit 701-26 is an
“AND” the data signal with the mask signal and use the result.
Provide a comparator circuit that produces the result signals MSKCBR0-7.
Ru. Signals MSKCBR0-7 are given to another comparator circuit.
The circuit uses this as a conditional branch test signal.
TYPGGO “AND” and branch decision flip flow
Set or reset the switch 701-22 and
A flip-flop has a state that indicates whether a branch occurs or not.
generates a signal RBDG0 indicating whether the output signal
RBDG0 is the first two of switch 701-12
is given as a control input for the position of . branch
Test conditions are not met (i.e. signal RBDG0=
0), incremented from MICA register 701-14.
address is selected. If there are any as stated in the text, the formation
followed by the state of the indicator for that cycle.
It is impossible to test. For this reason
Therefore, remembering registers for indicators in group 2.
Therefore, history registers HR0 to HR7 (not shown) are set.
I'm being kicked. Such memorized indicators
The state of the data is selected and other indicators (i.e.
mask field) condition as well as
Ru. Additionally, device 701-1 has a number of indicator times.
including paths, some of which are controlled by certain types of commands.
When the string being processed is delayed, the processor 700
used to control the action of some part of
These indicator circuits are block 701-4.
2 and in the microinstruction word of Figure 6a.
field (i.e. IND6 field)
It is set and reset by . ECS output register
This field read from star 701-4.
The bit is decoded by decoder 701-40.
Provided to RMI register 701-38. Various programs
processor device (e.g. 714, 720, 722
based on the state of status indicator signals received from
and the appropriate one of the auxiliary flip-flops is binary.
It is switched to the state of number 1. These flips
The output of the flop is a 4-position switch 701-44.
switch 701 for inspection through different positions of
-Given to 26 GP3 positions. The same output is ZDO
for storage via switch 704-340
given to the second position of ZIR switch 701-43.
It can be done. For example, indicator status signals may
It includes the output of the adder circuit (AL, AXP).
Ru. These signals are FE11, FE12, FE13,
Polymers labeled FE1E, FE2E, FE2 and FE3
Set each of the many termination flags and flip-flops.
to tsut. FE1E and FE2E flip-flops
is set during any FPOA cycle of any instruction.
will be played. These flip-flops also have
The output from the AL or AXP adder circuit of
When setting FE11, FE12, FE13 flip-flops
make it tsut. Setting of these indicators
and resetting, please refer to the explanation of the action.
This will be explained in more detail below. However, the main text
Termination flags and flip-flops for cases in
The program is set and reset according to the following formula:
be done. Set: FE1E=FPOA+IND6FLD field Reset: FE1E=IND6FLD field Set: FE2E=FPOA+IND6FLD field Reset: FE2E=IND6FLD field Set: FE11=IND6FLD field ・FE1E (ALES+AXPES+DESC1 ・AP0−4=0)+IND6FLD Field・FE1E・DESC1・ (AP0−5=0+APZN+ALZN) +IND6FLD field Reset: FE11=FPOA+IND6FLD field Set: FE12=IND6FLD Field FE1E・(ALES+AXPES+FE13) Reset: FE12=FPOA+IND6FLD field Set: FE13=IND6FLD field ・FE1E・ALES＋IND6FLD Fee
Ludo Reset: FE13=EPOA+IND6FLD field Set: FE2=IND6FLD Field FE2E・ALES＋IND6FLD Field・FE2E・DESC2・
(APO-4 =0+AP0-5=0+APZN+
ALZN) + (IND6FLD field) FE2E ・DESC2＋IND6FLD Reset: FE2=FPOA+IND6FLD file
de Set: FE3=IND6FLD Field/DESC3 ・(AP0-4=0+AP0-5=0+
APZN +ALZN)+IND6FLD Field・DESC3＋IND6FLD Reset: FE3=FPOA+IND6FLD file
de However, IND6FLD displays a specific code.
That is, ALES=AL=0 or -; AXPES=AXP=0 or -; APZN=AP0−70; and ALZN=AL0−110 Normally ZCSBRA switch 701-18 is a branch
Decision flip-flop RBD
Enabled when set to binary 1.
Become. The first location is RSCR register 701-2
13 from the current microinstruction given via 0
Select the bit branch address. This branch ad
directly at any of the ECS control store locations.
Allows direct addressing. The second position is
Current input via MIC register 701-15
The six lower addresses from the row microinstruction.
bits and via RSCR registers 701-20.
Branch address from the current microinstruction given
Select the concatenation of the 7 most significant bits of the others
specified by the contents of MIC register 701-15.
within a 64-word page (current location + 1)
Allow branching. The third location is the RVB0 vector branch register
The four lower bits of
from the branch field of the current microinstruction
6 bits and the address stored in the MIC register.
Select the concatenation of the three most significant bits of the others
16 branching methods are possible. The fourth position is
4 bits from vector branch register RVB0 and the current
line microinstruction branch address field.
The four most significant bits are stored in the MIC register.
The three upper bits and the two lower bits of the current address
Select zero concatenation. Therefore, the destination of each adjacency pair is
16 ways with 3 control memory locations between destination addresses
branching becomes possible. The fifth position is vector branch register RVB1
These two bits and the current microinstruction branch
6 bits of address and high order from MIC register
Select the concatenation of the two lower zeros with the 3 bits of
Ru. For this reason, there are three
Branching with 4 possible destinations by controlling storage location of
becomes possible. The sixth position is vector branch register RVB2
These two bits and the branch address of the current microinstruction.
6 bits of the address and the upper 3 bits from the MIC register.
Select the concatenation of two low order zeros with bits. child
This creates three constraints between the destination addresses of each adjacent pair.
It is possible to branch in four ways depending on the location. The output of switch 701-12 is shown in Figure 6b.
reading from a microinstruction word that has the format
The specific in control store 701-2 that causes the
Address a location. In the figure, this
Microinstruction words are used in various ways within processor 700.
Many different functional devices used to control
is determined to be encoded to contain a field that
Ru. Only these fields are relevant to this example.
This is explained in the text. Bits 0-1 Reserved for future use. Bit 2 EUFMT How does the EU operate?
stipulates. EUFMT-0 is like the first microinstruction
Specify the expression, EUFMT=1 is another microinstruction
Specify the format. Bit 3-5 TRL TR lower write control Control book for EU temporary storage registers TR0 to TR3
included. OXX No change 100 write TR0 101 Write TR1 100 write TR2 111 Write TR3 Bit 6-8 TRH TR upper write control Control book for EU temporary storage registers TR4 to TR7
included OXX No change 100 write TR4 101 Write TR5 110 Write TR6 111 Write TR7 Bit 9-12 ZOPA ZOPA switch control ZOPA switch output selection (0) 0000 TR0 (1) 0001 TR1 (2) 0010 TR2 (3) 0011 TR3 (4) 0100 TR4 (5) 0101 TR5 (6) 0110 TR6 (7) 0111 TR7 (8‐11) 10XX RDI (12) 1100 ZEB (13) 1101 ZEB (14) 1110 ZEB (15) 1111 0 (Use prohibited) Bit 13-16 ZOPB ZOPB switch control ZOPB switch output selection Bit 17-18 ZRESA ZRESA switch system
God ZRESA switch output selection 00 ALU 01 Shifter 10 Scratch pad/RDI switch 11 ZDO Bits 19-20 ZRESB ZRESB switch control ZRESB switch output selection 00 ALU 01 Shifter 10 Scratch pad/RDI switch 11 ZDO Bit 21 RSPB Scratchpad Butt
A strobe control Strobe with ZRESB data of RSPB 0 No strobe 1 RSPB strobe Bit 22 RSP Scratch Pad Write Control 0 read scratchpad 1 Write scratchpad Bit 23 ZSPDI Scratch Pad/RDI Scratchpad
Itsuchi control Scratch pad/RDI switch output selection 0 Scratch pad output 1 RDI Bits 24-25 ZSHFOP shifter operator
switch control Selecting left operator for shifter 00 ZOPA output 01 EIS output 10 0 11 Bit 0 of the right operator for the shifter
Therefore selection of 0 or -1 Bits 24-27 ALU ALU function control on the two inputs (A and B) to the ALU.
Selection of a given operation Bits 24-29 N/A Bits 26-31 RFU For future use
reservation Bits 30-31 ZALU ALU switch control ZALU switch output selection Bits 32-33 NXTD Next Descriptor Control Strobe the RBASB and RDESC registers 00 RBASB←00 RDESC←00 01 RBASB←01 RDESC←01 10 RBASB←Alt RDESC←10 11 No strobe (omitted) Bits 32-35 in CCM CONTF field
Control constant field matched by Bits 34-35 IBPIPE IBUF
control Selection of reading IBUF or pipeline operations 00 No operation 01 IBUF/ZDI read (Alt) 10 Type 1 Restart Release or 11 Type 4 restart standby Bit 36-37 FMTD Selection and loading of various CU registers
MEMARD file for small-scale CU control
An indication of the interpretation given to the code. 00 No operation 01 RADO←ASFA 10 RADO←ZRESB 11 RADO←ASFA Bit 38-40 MEMADR cutlet control Selection of cutlet operation. complete control over this
Interpretation is a function of FMTD control FMTD control 000 No operation 001 Single read 010 Road Quad 011 Read ahead 100 single write 101 Double write 110 Single read translation (=11 for FMTD)
fruit) 111 for single write word (FMTD) = 11
only) Bit 41 ZONE Zone control Table of zone applicability for small-scale CU control
Show 0 No zone 1 zone available Bits 42-44 TYPA Type A flag Type A overlaid file in use
field display 000 Type A=0 field 100 Type A = 4 fields Bits 44-46 PIPE Pipeline control Selecting the type of restart to be initiated 000 No operation 001 Type 1 restart and release 010 Type 2 restart 011 Type 3 restart 100 Type 4 restart 101 Type 5 release 110 Type 6 restart Bits 44-47 AUXREG Auxiliary register book
control The device selected by the AUXIN control field
an auxiliary register strobed by the
Selection of the combination (0) 0000 No strobe (1) 0001 RRDXA (2) 0010 R29 (3) 0011 R29, RRDXA FRL, RID (4) 0100 RRDXB (5) 0101 RTYP (6) 0110 RBASA (7) 0111 RBASA, RTYP (8) 1000 RBASB (9) 1001 RDESC (10) RBASA, R29, RRDXA Bit 45-46 TYPB Type B flag Type B overlaid fees in use
display 00 Type B=O field 11 Type B = 3 fields Bit 47 RSC RSC strobe control RSC register strobe (shift counter)
) Bit 47 RSPA RSPA strobe control RSPA register strobe Bit 47-48 N/A Bit 47RAAU RAAU strobe control RAAU register strobe Bit 48-49 ZLX ZLX switch control ZLX switch output selection Bits 48-49 ZSPA ZSPA switch control ZSPA switch output selection Bits 48-50 AUXIN Auxiliary register input
of data strobed into the control auxiliary register.
choice Bit 49 ZADSP ZADPS switch control ZADSP switch output selection Bits 50-52 ZSC ZSC switch control ZSC switch output selection Bit 50-52 ZRSPA ZRSPA switch system
God ZRSPA switch output selection Bits 50-52 ZAAU ZAAU switch control Bit 51 RSIR RSIR register strobe RSIR record as a function of the AUXIN field.
jista's strobe Bit 53 RDW R1DW, R2DW register
Trove R1DW as a function of RDESC register
is the strobe of R2DW register Bits 53-54 ZLNA ZLNA switch control ZLNA switch output selection Bits 54-57 CONTF Various flip-flops
Tsupu control Set by control constant field (CCM)
or 4 groups of control flips reset
One choice on the flop. These flip-flops
Blocks 704-104 and 704
-110 flip-flops included. Bits 55-56 ZLNB ZLNB switch control ZLNB switch output selection Bit 55-56 ZSPA₍₂₎Type A = (2)
ZSPA switch, RSPA register control ZSPA switch output selection and RSPA register
star strobe Bits 57-58 ZPC ZPC switch control ZPC switch output selection Bit 59-62 ZXP ZXP switch, RXP
register bank control ZXP switch output and this is written
RXP register selection Bit 59-63 ZLN₍₁₎(Type A=1)
ZLN switch, RLN register bank control ZLN
switch output and the RLN register to which it is written.
Selection of register Bits 59-60 ZPA ZPA switch control ZPA switch output selection 00=RP0 11=RP3 Bits 61-62 ZPB ZPB switch control ZPB switch output selection 00=RP0 11=RP3 Bits 63-64 ZXPL (Type A=0)
ZXPL switch control ZXPL switch output selection 00=RXPA 11=RXPD Bit63 ZLN₍₂₎(Type A = 2) ZLN
Itchi, RLN register bank control ZLN switch output and this is written
RLN register selection Bits 63-66 RDIN RDI In Control The data strobed into the RDI register and
and instruction word change control field (MF₁−
M.F.₃, TAG). RDI strobe
can also be controlled by the MISCREG field. Bit64 ZXPL₍₁₎(Type A=1) ZXPL
switch control ZXPL switch output selection Bit 64-68 ZRPAC (Type A=2)
ZRPA switch, ZRPC switch, RPO-3re
register bank control ZRPC and ZRPA switch output and ZRPA
Selection of RPO-3 register to which output is written Bit 65-66 ZXPR (Type A=0)
ZXPR switch control ZXPR switch output selection Bit 65-66 ZXP₍₁₎(Type A=1)
ZXP switch, RXP register bank control ZXP switch output and this is written
RXP register selection Bits 67-68 ZPD (Type A=0) ZPD
switch control ZPD switch output selection bit67 ZRPAC_(Four)(Type A=4)
ZRPA switch, ZRPC switch, RPO-3re
register bank control CP4 selection from ZRPA switch, and
RP1 register strobe Bit 67 TYPD Type D flag Field overlaid with type D
Type D flag to display bit68 ZRPB_(Four)(Type A=4) ZRPB
Switch, RP4-7 register bank control Selecting 0 from ZRPB switch and RP4 level
jista's strobe Bit 68-71 MEM Katsushi Memory
control Selection of cutlet operation regarding SZ control (0) 0000 No operation (15) 1111 Remote writing Bits 68-70 IBUF IBUF read control Selection of IBUF data destination when reading IBUF Bits 69-73 AXP (Type A=0)
ZXPA switch, ZXPB switch, AXP addition
device, ZAXP switch, RE register control ZXPA and ZXPB switch output, etc.
The AXP adder function provided to the switch,
ZAXP switch output selection. Also, RE register
strobe Bit 69-73 ZRPB (Type A=1)
ZRPB switch, RP4-7 register bank system
God ZRPB switch output and this is written
RP-47 register selection Bit 69-71 ZRPAC-3 (Type A=
3) ZRPA switch, ZRPC switch, RPO
-3 register bank control ZRPC and ZRPA switch output and ZRPA
Selection of RPO-3 register to which output is written Bit 72-74 ZRPB₍₃₎(Type A=3)
ZRPB switch, RP4-7 register bank system
God ZRPB switch output and this is written
RP4-7 register selection Bit 72-73 SZ Size/Zone/Cut
sie control Katsushie operations regarding MEM control fields
control of production Bit 74-78 ZRPB₍₀₎(Type A=0)
ZRPB switch, RP4-7 register bank system
God ZRP switch output and this is written
RP4-7 register selection Bit 74-78 AL (Type A=1)
ZALA switch, ZALB switch, AL adder system
God ZALA and ZALB switches, etc.
AL adder function given to Bit 74 TYPE Type E flag Type E overlaid field
Type E flag to display Bit 75-77 ZXP₍₃₎(Type A=3)
ZXP switch, RXP register bank control ZXP switch output and this is written
RXP register selection Bits 75-78 MISCREG Miscellaneous registers
control Various registers (e.g. RBIR, RDI,
Selection of various operations in RLEN, RSPP) Bits 75-78 ZDO ZDO switch control ZDO switch output selection Bit 78 ZIZN ZIZN switch control ZIZN switch output selection Bit 79-83 AP ZAPA switch, ZAPB
Switch, AP adder control ZAPA and ZAPB switch outputs and
Selection of AP adder functions provided to Bit 79-81 ZLN₍₃₎(Type A=3)
ZIN switch, RLN register bank control ZLN switch output and this is written
RLN register selection Bit 79-83 ZLN_(Four)(Type A=4)
ZLN switch, RLN register bank control ZLN output and the RLN register this is written to
Select star Bit 80-81 RAAU RAAU/RE Regis
ta strobe Several switches and additions of device 722
The RAAU and RE registers are
Selecting data to be trobed Bit 82-83 AP₍₃₎(Type A=3)
ZAPA switch, ZAPB switch, AP adder system
God ZAPA and ZAPB switch output and this
AP adder function selection given to etc. Bit 84 ZRSC (Type A = 0) ZRSC
Itsuchi control ZRSC switch output selection Bit 85-86 N/A Bit 86 RLEN (Type A = 3) RLEN
Trobe control RLEN strobe or hardware or
Controlled by the MISCREG field. Bit 87 FMT style flag Style type selection Bit 88-89 TYPF Displaying the types of fields that are overlaid 00 = Scratchpad address 01 = Character device control 10=multiplication/division control 11=N/A Bit 90 RFU Reserved for future use Bits 90-93 CHROP Character device OP code The main operations performed by character devices and
Choice of interpretation given to CHSUBOP field (0) 0000 No operation (1) 0001 Load data (2) 0010 MOP execution (3) 0011 Single comparison (4) 0100 Double comparison (5) 0101 Load register (6) 0100 CN update (7) 0111 Not specified (8) 1000 RCH operation A set (9) 1001 RTF1 set (10) 1010 Set RTF2 (11) 1011 Set RTF3 (12) 1100 Set RCN1 (13) 1101 Set RCN2 (14) 1110 Set edit flag (15) 1111 CH device clear Bit 90 RCH RCH register strobe OP1 RCH register strobe Bit 90 RFU Reserved for future use Bit 91-97 SPA Scratch Pad A
dress Used for addressing EU scratch pads
Retaining addresses Bit 91-93 N/A Bits 94-97 CHSUBOP Character device sub
OP code Select detailed features of character device, otherwise
This device contains constants. Interpretation of this field
is a function of CHROP control as shown below. CHROP=0000 No operation CHSUBOD_0-3 XXXX No interpretation CHROP=0001 Load data operation CHSUBOP_0-1(Sub operation) 00 OP1 load by CN1andTF1 01 Loading OP1 reservation state by CN1andTF1 10 OP2 load with CN2 and TF2 and check character 11 Loading codes CHSUBOP_2-3(filling control) 1X Filler characters loaded into ZCU Filler character loaded into X1 ZCV CHROP=0010 MOP execution operation CHSUBOP_0-1(Sub operation) 00 MOP set by CN2 01 MOP execution 10 Not specified 11 Not specified CHSUBOP_2-3 XX No interpretation CHROP=0101 Load register operation CHSUBOP_0-1(RCH output selection) CHSUBOP_2-3(ZOC switch output selection) CHROP=1011 RTF3 set operation CHSUBOP_0-1(The data to be checked for 00
(Select data, display 9-bit characters) CHSUBOP_2-3(constant field) CHROP=1110 Edit flag set operation CHSUBOP_0-3(The constant is the flag to be set.
(select tsugu) 1XXX ES set (termination suppression) X1XX SN set (code) XX1X Z set (zero) XXX1 BZ set (blank when zero) Bits 94-97 RFU Reserved for future use.
about Bit 97-97 N/A Bit98 TYPG Type G flag Displaying types of overlaid fields 0 = BRADRU field 1=IND6 field Bit 99 GO Conditional branch check status Bits 99-106 BRADRU Upper address
branch of Bit99-106 IND6FLD indicator
control Indicator selection Bits 99-106 Bit 99 = 0 is an indicator
Specify data change command Bit 99=1 is set/reset indicator
Specify the digit command (by X bit 0 or 1).
(set or reset respectively)

【table】 Bits 107-112 BRADRL Lower address
branch Under ECS address used for branching
Preservation of place part Bit 113 EXIT Exit switch control selection Exit selection indicates the end of the microprogram Bit 114-116 ZCSBRA ZCSBRA switch
Tsuchi control In the control store branch address switch
Definition of selected position Bit 117-118 N/A Bits 119-123 INDGRP Conditional branch
indicator group control The first 2 bits (119-120) are "group"
microprogram indicator selection,
The last 3 bits (121-123) are for each “group”
Select “Set” for the indicator in Bit 124 TYPH Type H field 0=INDMSKU 1 = VCTR field Bits 125-128 INDMSKU Conditional Minute
Branch indicator top mask Indicator in type H=0 field
Retention of upper 4 bits of data mask Bits 125-129 VCTR Vector selection Stroke to RVB0, RVB1 and RVB2 respectively.
Selection of branch vector to be saved, most significant bit
(125) is two groups 1 or 2, 2 or 4,
and which of 4 or 5 are registers respectively
strobed by RVB0, RVB1, and RVB2
Decide what to do. The remaining 3 bits are within each group.
Select the vector of . Bits 129-132 INDMSKL Conditional Minute
branch indicator lower mask Retaining lower bits of indicator mask Bit 133-135 N/A Bits 136-139 CNSTU upper constant Retention of upper 4 bits of constant field Bits 140-143 CNSTL lower constant Retention of lower 4 bits of constant field Control logic unit 704-1 As mentioned above, the output of this device is block 7.
04-102 multiple I-cycle control state fritz
Sequence decoding logic provided to the flop
704-100. These flips
The flop is a micro
Instruction (MEM address field in Figure 6b)
MEMADR and corresponding DEMRO38-40)
In response to a signal from path 704-100, the program
Various required information needed to execute a ram instruction
Generate I-cycle control state. Block 704
-102 is also a register allocated to processor 700.
Gate circuit that generates the star hold signal [HOLDE00]
has. As can be seen from Figure 3c, the I-cycle control state
The flip-flop is rotated from the cutter device 750.
Control input via control line including line CPSTOP00
Receive a signal. line as described in the text.
The state of CPSTOP00 indicates that this line is strong against binary zeros.
When controlled, I cycle control state flip-flop
pending signals or other storage registers.
The processor is in a state where the enable signal is also forced to zero.
Determine whether the operation continues. signal
The hold signals corresponding to [HOLDI00 and [HOLDE00] are
The state of processor 700 is suspended or frozen.
use Control store address increment does not occur
Therefore, the ECS control store uses the same microinstruction
Read the code. Signals [HOLDI and [HOLDE] are below.
The following logical formula, [HOLDI=CACHEHOLD+
HOLDREL is set according to this logical expression
In the case, the state of signal CACHEHOLD is
Corresponding to the state of CPSTOP, the signal HOLDREL is
By generating a microprogram release signal
It is a binary 1 until it is switched to a binary 0,
Therefore, [HOLDE=[HOLDI]. Lines used in explaining the operation of the present invention
circuit in response to signals applied to CCSDO20-25
Hardware generated by 704-100
The sequence is as follows.CCS-S code sequence 111101 = EDIT This sequence is followed by EPOP3
FPOA−FPOP1−FPOP2.
Required registers for processing edit operators
Setting up tables, tables, etc.
Following the application, the hardware control
The master signals the path and enters state FPOP3.
Expansion to microprogram control
Jiru. Hardwires used to explain the operation of the present invention
control states and
The operations to be performed are as follows.Control state/cycle explanation FPOA FPOA Preparation Operator Address
The state is for all commands
It is in the start control state.
1 address for FPOA
is calculated and the OP code is
Via CCS Control Store
Translated and works no more
control. FPOP FPOP prepare operator pointer
processes the instruction descriptor
Control state used for
It is. FESC FESC extension is an I-Process
for the pipeline
This is a variable delay state.
Ru. During FESC state, ESC
Control store is processor 70
Has full control over 0
and I-process pipe
When restarting the line
Determine the point. As can be seen from Figure 3c, the I-cycle control state
The signals corresponding to the blocks 704-104 are
Multiple control flip-flops and block 704
-106 decoding circuit and blocks 704-108
and a large number of control logic circuits of block 704-11.
0 multiple control flag indicator flits
Provided as input to the flop. or,
Various indicators of blocks 704-110
The flip-flop is connected to the execution controller 701-4.
Microinstruction input signals via lines MEMDO54-57
I know that I will receive the number. As can be seen from Figure 3d, the hardware control theory
The signals formed by the logic circuits 704-108 are
as a function of the devices whose operation is being controlled.
become one of three groups. That is, this group
A loop is an instruction buffer control, hardware control,
and hardware memory control. In each case, each signal group
are ORed together with the equivalent signal formed by the
It is then decoded. Other sources are ECS output
Register 701-4 to RCSR register 704-1
12 for the microinstruction of FIG.
respond. One field (large CU) is like one
Corresponding to bits 32-83 of the expression, another field
(Short CU) corresponds to bits 32-41. this
The fields such as
Decoded into the set of bits shown and decoded as shown.
coder 704-116, 704-124, 704
-126 and 704-128.
Further decoding operations are performed by blocks 704-118,
704-135 and 704-120 circuits
It is done by folding. The result of decoding these fields is
The results are distributed within processor 700 or
RMEM registers 704-130, RSZ flip
Flop 704-132, FREQDIR flip
LOP 704-136 and FREQCAC free
The data is stored in flipflops 704-134. Large and short CU fields, and block
From the I-cycle status circuit of TS 704-112.
Further decoding of the signal is performed by decoders 704-106 and
704-107. decoder 70
4-106 is the low day of different registers
processing, and various multiplayer functions within the processor 700.
Enabling the bar/selector switch
Generate control signals for Decoder 704-1
07 is a pair of basic pointer B flip-flops.
To set and reset 704-144
acts to form a signal. In addition to these signals
blocks 704-140 and 70 using a combination of
4-142 descriptor number flip-flop set
and reset. As can be seen from Figure 3c, decoder 704-1
16 is the decoder circuit of block 704-117.
Receives the control signal [EXH000] formed by child
These circuits are RDESC registers 704-140.
signals and the termination fritz of block 701-1.
Receives the signal from the flop. These signal conditions
Depending on the state, this circuit converts the signal [EXH000 into a binary number]
Force to zero and cutoff as soon as the end condition occurs
Prohibits generation of memory commands. Signal [EXH000
is formed according to the following logical formula. That is, [EXH000=DESC0・FE11+DESC1・FE2+DESC2・FE3 Flipflop FNUM is usually a microinstruction
Set in response to word's CCS-OP field
be done. When set to binary 1, this
Indicates that the descriptor inside is of numeric type. FINH-ADR flip-flop is ready for address
The operation of device 704-3 is prohibited. Set to binary 1
address cycle (FPOA/
EPOP) is a temporarily valid address register.
It consists of the addition of REA-T+zero content. cash register
Star REA-T prior to FPOA/FPOP cycle
is being loaded at the address. FABS fritz
The pflop allows the generation of absolute addresses.
When set to binary 1, it is a 24-bit absolute address.
response is used. Block 704-110
Regarding lag or indicator flip-flops.
Then, the flip-flop FID is set to binary 1.
indirect address between one instruction.
Descriptors whose changes are loaded into the RSIR register.
and give an indication of what is required. When set to binary 1, the FRL flip-flop
lops whose lengths are loaded into various instruction registers.
specified in the register associated with the instruction being executed.
indicate. Three flip-flops FINDA,
FINDB and FINDC are memory type instructions
gives the display used in the process. fritz
The flop FINDA handles indirect address changes or records.
One descriptor specifies the length indicated in the register.
Set to binary 1 when requested. Fritzpf
Loop FINDB indicates that this descriptor contains a 9-bit character.
When not included, it is set to binary 1. Fritzpf
Loop FINDC is used when the descriptor contains 6-bit characters.
Set to binary 1. As can be seen in Figure 3c, block 704-1
Output from 10 control flag flip-flops
Power is branch indicator circuit of block 701-1
given as input to . Processor 700, cutlet device 750, etc.
section 704 as well as the operation section 704.
The required timing signals are centrally located.
It can be seen that the given clock circuit is given by
Will. For example, in the preferred embodiment of FIG.
In this case, the clock circuit is connected to the input/output processor 200.
Built-in. This type of clock circuit is structurally
crystal controlled oscillators and
It has a counter circuit. A clock circuit like this
The timing or clock signal from
is arranged in each part of the system in Figure 1 for synchronized operation.
divided. Register section 704-150 As can be seen in Figure 3c, control logic 704
-1 is also register section 704-150
including. This section contains the basic instruction register.
(RBIR) 704-152 and secondary instruction register
(SBIR) 704-154 and block 704-3
04 address register RAR0 to RAR7 1
The base pointer A register used to select one
Zista (RBASA) 704-156 and Sexy
Index register (not shown) included in input 704-5.
) selection and ZDO multiplexer switch
Used for selecting output from 704-340.
The read index register A704-158 and the
Type of data character indicated by the value of the predicate
(e.g. 9 bits, 6 bits, 4 bits)
descriptor type register (RTYP) 704-1
Contains 60. Section 704-150 is
Furthermore, the 1-bit instruction of block 704-162/
Contains EIS descriptor register R29. RBAS-A cash register
This bit regarding the contents of star 704-158
State is used to specify the specific address used for address preparation.
Select address register. Block 704-
162 register R29 is set to binary zero
This is the address of block 704-304.
None of the registers are used during address preparation.
to show that End of section 704-150
The registers of blocks 704-164 are
input register (RDI) and execution unit 714
A read index that points to the register used by
Contains register B. As can be seen from Figure 3, the RBIR register 704
-152 indicates the displayed source (i.e. switch
Receives signals from ZIB-B704-172 and lines ZDI0 to 35).
Two position switch 740-1 connected to take
70. RSIR register 70
4-154 also has ZDI line and switch 70
Receives signal from 4-172. RBASA register
704-156 is another block 704-174
Transmission from ZDI lines 0 to 2 outside the ZBASA switch
Receive the issue. RRDXA and RTYP registers
are switches 704-176 and 704 as shown.
-178 and receives a signal from line ZDI. Switches 704-172 are cutlets respectively.
Switch ZIB from device 750 and execution device 714
and a two-position switch that receives input from ZRESB.
It is. Switch 704-174 is a 3-input switch
2 inputs from the execution device 714 and a cutter
Receives the output of the ZIB switch of device 750. Switch 704-176 is a 4-input switch,
Two of the inputs from the execution device 714 and the cutlet
One input is received from device 750. ZRDXA
The first position of switch 704-176 is ZRDXM
Select the output of switch 704-185. this
One location of the switch is RBIR register 704.
-152 bit positions 5 to 8, 14 to 17, and
and 32 to 35, and ZIDD switch 704-180
and 2-position ZMF switch 740-176.
Bit position of RSIR register 704-154
Give the tag field values from positions 32-35.
Ru. The second position of switch 704-185 is
ECS output register 704-1 (CCM field
32-34) give constant values from the output. line
Signals from ZIDD27~35 are block 704-11
0 control flag flip-flop
given as input. switch 704-178
input from control store 704-2 and
input from the execution device 750 and the input from the execution device 714.
Receives input. Data input registers 704-164 are ZIDD
Receives a series of input signals from the switch 704-180
The switch has an RDI register 70 on its output side.
Another switch 704 that loads directly into 4-164
-ZDIA switch 704 giving one input of 182
-181 is connected in series. ZDIA Sui
The switch 704-181 is a 3-input switch 704-1.
Another input is given to 83, but the 3-input switch
Itchi is cutlet device 750 and execution device 71
4 and receives other input. ZIDD switch 704-180 is an RBIR register
register 704-152 and RSIR register 704-1
54 and 2 position ZMF switch 740-187
Receives input from. ZDIA switch 704-18
1 is the ZIDD switch 704-80 and execution unit.
Signal from the output side of the ZRESB switch in position 714
In addition to the signals from ZDI lines 0 to 35, and
A certain constant value that occurs at the first switch position from the force side
Receive. Switch 704-182 is ZDIA switch
Receives signals from Tutsi output and ZDI lines 0-35
Ru. RRDXB registers 704-189 are 3-position
Loaded by switch 704-188. this
The switch is included in the execution device via the first position.
The signal from the RREG register and the second location
and the constant value from control store 701-2 and the third
Receives signal from ZIDD switch via location of
Ru. Sections 704-150 also include a two-position switch.
Tsuchi704-185 and its output is AACU72
2 used by EU714 Scratch Patches
Address for access to memory
Scratchpad pointer register that forms
704-186. first switch
Position gives one constant value and is hardware controlled
(FPOA・29) Selected below. second sweet
The location is the contents of RBASA registers 704-156.
is given as output. This position is hardware controlled.
control and microprogram control (i.e.
FPOA/R29 or MISCREG field)
is selected. Address preparation device 704-3 Address preparation device 704-3 has a number of registers.
and an adder. register is one instruction
Block 704- used to store descriptor values of
300 multiple base registers (i.e. TBASEO
TBASEB) and a pair of temporarily valid addresses.
address registers (TEA0, TEA1) and instruction
Block 704 used to address the
A pair of instruction counters built into -302
(ICBA, ICBB) and used during address preparation operations.
Eight addresses in blocks 704-304
contains the access registers (RAR0 to RAR7).
Ru. Device 704-3 also has an instruction counter 704-3.
Contains 10. The adder includes switches 704-311 and 704-
314 to update instruction counters 704-310.
adders 404-312 used to update;
A pair of adders 404-320 and 704-322
Contains. Adders 704-322 block
Usually stored in one of the registers 704-302
used to form effective address values.
This effective address has its output in block 704.
−327 through a large number of AND gates.
ZY switch 704-326, block 704
-304 selected temporary address registers;
or another switch 704-328.
Selected one of the blocks 304-302
Temporal address registers TEA0 and TEA1, or
is the index address signal ZXO from device 704-5
Generated from numerous sources including -20. Furthermore,
The adder 704-322 is connected to the cashier instruction buffer.
Used to update the contents of the instruction counter.
Ru. As can be seen in Figure 3d, adder 704-32
The output from 2 is also applied to adders 704-320.
given as input. Adder 704-320
are temporary base registers TBASE0 to TBASEB
Adder 70 adds the base value stored in any one of
Combined with address signal ACSOS0-19 from 4-322
used for matching. The resulting bits
is connected to the line ASFA0 via the adder 704-321.
Another addition that differentiates the logical address given to ~36
Provided as input to calculator circuitry 704-320.
available. This adder is connected to block 704-30.
With shift input from 0 and 704-320
Add operator inputs. This valid address is
When the stem is operated in paginated mode
Used to obtain absolute addresses. This operation
is not related to the present invention and will not be discussed further in the text.
Not mentioned. Further information regarding such address generation
See U.S. Patent No. 3,976,978 for more information.
I want to be illuminated. Temporary Base Registers of Blocks 704-300
is loaded via switch 704-332.
Ru. This switch receives input from the execution device 714,
Receive output from blocks 704-300. execution
Device 714 switches yet another input to switch 704-3.
34 to the registers of blocks 704-302.
and the address of block 704-304.
It is also given to the response register. output multiplexer
(ZDO) switch 704-340 is the line
The contents are sent to the execution device 714 via ZDO0~35.
address preparation device 704-3 and
Enables selection of various registers in device 704-3
do. Also, ZDO switch 704-340 is
Registers and control flip-flops in location 704-1
Put the contents of each tup in the fourth position (ZDO-A).
read out via the The fifth position is block 70
The status of various displays in the control store circuit of 1-1 is detected.
be selected for inspection. XAQ register section 704-5, and
Data address output section 704-4 3rd
Figures e and 3f Section 704-5 is an accumulator RA
registers 704-50 and quotient QA register 704
-52 and used by control logic unit 704-1.
Transient indicator (RTX) register 704-54
Contains. program visible RA,
The contents of RQ and RTX registers are ZXA2 switch 7
04-56, ZXOB switch 704-57,
Device 704- via ZX switch 704-58
3. From here, the contents of this register are
Executed via ZDO switch in device 704-3
Transferring to the device 714 or the cutlet device 750
I can do it. The selection of the output from the aforementioned switch is determined by bit 5.
5 to 77 (ZX field) plus RRDXA cash register
star 704-158 and block 704-104
FNUM flip-flop and RTYP register 7
Controlled by the contents of 04-160. ZXA2
The switch 704-56 is for changing the address.
RA and RQ registers 704-50, 704-5
The upper or lower 18 bits of 2 are read.
Select from ZXA2 switch and ZXOB switch
The output signals are RAAU, RTX and
and RIC register signals to the ZX switch.
It will be done. The ZX switch uses the first position as an output.
RA/RQ register for 9-bit character string
bits of the star and the 6-bit statement via the second position.
RA/RQ bit for character string and third
to a 4-bit character string via position
RA/RQ bits and word type changes
Select the RA/RQ bit. RAAU register, RIC register and RTX register
Position 5, to select the contents of the register respectively.
6 and 7 are used. Another ZXB2 switch 7
04-59 is programmed via line ZEB0~35
Equipped for reading from RAM visible registers.
A second path is provided to the location 714. device 72
A similar route for 8 is via lines ZAQ0-35
Given. Section 704-4 is attached to cutlet 750.
registers used to transfer orders and data.
It includes a star and a switch. Such a turn
The feeding operation usually consists of at least two cycles, i.e.
is for sending addresses, others are for sending data.
Requires cycles. Bit 5 of the command word
8 is obtained from the output side of the 4-position switch 704-40.
It will be done. The switch is connected to the first position via the first position.
RZN register via constant value of 1 and 2nd position
704-42 and the second via the third position.
and the third constant value via the fourth position.
Receive. Bits 1-4 of the command are in block 704-1.
OR gate circuit with bits 5 to 8 depending on various circuits
704-44. This OR gate 70
4-44 is also the RADO register 704-48.
Receives bits 1 to 8 of ZADO switch 704-46.
take. RADO registers 704-48 contain addresses and
ZADOB switch
line through the first location of Tutsi 704-48
Address preparation device 704-3 via ASFA0~35
Logical (virtual) address from ZRESB0~
Data out signal from EU417 via 35
Receive. Each position of switch ZADOB704-48
is the FMTD field for small CU styles
or RADO for large CU formats.
Under the control of the field. As can be seen from the figure, ZZN1 to 8 bits or
ZADO bits 1 to 8 are control signals [RADO~
RADO/ZADO line as a function of ZADO state
given as the output for . Bit 0 and
9 is always a binary 1, but bits 10-35 are
given by RADO registers 704-46.
Ru. Execution device 714 - Figure 3g Device 714 has an address as its primary device.
Specifiable temporary register bank 714-1
0 and 714-12 and arithmetic logic units
(ALU) 714-20 and shifter 714-24
and Scratchpad Memory 714-30.
Contains. Additionally, device 714 may be configured to
position data selector switch 714-15,7
14-17, 714-22, 714-28, 71
4-34, 714-36, 714-38,
Provides flexibility in choosing operators and output results.
provide In action, the operator is a ZOPA spacer as shown.
Itsuchi 714-15 and ZOPB Switch 714
-17 of the register in bank 714-12.
One or other inputs like ZEB0~35 or RDI0~35
Selected from line. ALU714-20 and
Shifter 714-24 is associated with the selected operator.
The result is sent to the output bus line ZRESA0.
Sweets to be given to ~35 and ZRESB0~35
Chi 714-24, 714-36 and 714-3
8. Similarly, scratch patch
selected through the contents of
The contents of the scratchpad location are sweets
Chi 714-34, 714-36 and 714-3
8 can be read out. This selected output result or other data
After temporary register bank 714-12 and
and 714-10 or scratching the execution device 714.
Processor 7 including padded memory 714-30
Loaded into other registers in 00. More specifically, the source of the operator is
ZOPA and ZOPB switch 714-15 and
Identical to the counterpart of 714-17. ZOPA
Switch position against Itsuchi and ZOPB switch
The location selection is made using bits 9-1 of the microinstruction word.
2 and bits 13-16.
ALU 714-20 is the microinstruction in Figure 6a.
selected under the control of bits 24-28 of the word.
Logical decimal or binary operations on operator data
make a work Shifter 714-24 is a microprogram
Aligning, shifting or rotating binary data under control
In the combined logic network used to perform
be. ZSHFOP and ZEIS switch 714-2
The input data signal from 8,714-22 is a single
are also concatenated to form a double word input.
You can think of it as Shifter 714-24
is the 36 bits shifted according to the shift count
gives the output of ZSHFOP switch 714-
28 is controlled by bits 24-25 of the microinstruction.
The shift count is controlled by the auxiliary calculation control unit 7.
The microphone of FIG. 6a is suitably selected via 22.
Sequence control constant field of instruction word
(bits 138-143). Book
For purposes of the invention, ALU714-20 and 7
14-24 may be considered to be structurally known. The scratchpad memory 714-30 is
As well as various constants and descriptor values,
Work to store various required data
give a range. For example, octal positions 10-15 are
Record the edit instruction table values required to perform the edit operation.
used for remembering. Scratchpad Memo
Writing to Lee 714-30 is done using ZRESB Suites.
input data provided via the chip 714-38.
RSPB buffer register 714-32
Including the first loading. During the next cycle,
The contents of the register 714-32 are stored in the AACU device 722.
The signal given to ZPSPA0 to 6 lines by
will be written to the specified location. Write to My
Bit 22 of the black instruction word (RSP field)
occurs when is forced to be a binary 1. Regarding other switches, as mentioned above, the device 71
The result caused by 4 is the control of the microprogram.
ZALU switch 714-26 and BSPDI switch below
Tsuchi 714-34 and ZRESA switch 714-
36 and is given via the ZRESB switch.
ZALU and ZSPDI switches are the final level selections.
The first
Make a level selection. Both switches ZRESA
and ZRESB switch have the same input source
Therefore, they give the same output data. ZALU
Switch data selection is bits 30 to 31
(ZALU field), but ZSPDI
Data selection is bit 23 (ZSPDI field)
is under the control of. ZRESA and ZRESB data
The selection is made in bits 17-- of the microinstruction in Figure 6a.
18 and bits 19-20 respectively.
It is in. Banks 714-12 and 714-10 cash registers
Each star has bits 3 to 5 (TRL file
) and 6 to 8 (TRH field)
Addressed vertically. within each field.
The first bit is one of the four registers that points to the address.
The other two bits specify whether
Select the register to be addressed. most
, the switch 714-40 in position 4 is the RREG register.
It is used to load a constant value or
is the bit position of signal RBIR register 704-152
This corresponds to positions 24-26. Character device 720 - Figure 3h The device 702 has four registers 7 forming a bank.
20-10 and a number of registers 720-22,7
20-24, 720-28, 720-30, 72
0-42,720-46,720-54,720
-63,720-64,720-68 and 72
0-70, conversion logic circuit 720-27, addition
The circuit networks 720-32, 720-34 and the comparator
circuitry 720-72 and multiple decoders/decoders.
Tector circuit network 720-36, 720-38, 72
0-44,720-48,720-50,720
-56,720-58 and 720-74 (many
multiple position selector switch 720-26,7
20-40, 720-62, 720-12 to 7
20-20 interconnected)
There is. Control and selection of such switches,
and strobing of various registers.
Numerous flip-flops included in the 720-80
circuit and a pair of zero detector circuits 720-8
2,720-84. The RCH bank of register 720-10 is
Receive from EU714 via ZRESA lines 0-35
Operator buffer register for storing information
used as. The first register (OP1) is
Operator or device 72 specified by descriptor 1
8 or for storage of data sent to device 722
used for. The second register (OP2) is a descriptor
used for storing the operator specified by 2.
It can be done. The third and fourth registers (TABLE
ENTRY1, TABLE ENTRY2) from EU714
For storing edit insert table entry values to get
used for. RCN1 register 720-28 is the ZCU switch
of the selection of characters to be selected by 720-12.
Actual character position for descriptor 1 used for
Holds location data. RCN2 register 720-3
0 is a signal indicating the character position data of descriptor 2.
Hold. These contents are for Switch 720-1
Used for selecting characters from 4. ZCU and ZCV switch 720-16 and
720-80 ZCU and ZCV flip-flops
under the control of the group. RCN1 and RCN2 registers
720-28 is generated by decoder 720-56.
CN1 of block 720-80 in response to the input signal.
and loaded under the control of the CN2 flip-flop.
It can be done. This is the RTF1 and RTF2 register 72
According to the contents of 0-42, 720-46, also blog
Initiation generated by the conversion logic circuit of block 720-27
Character type defined by character position signal (4,
(6 or 9 bit characters).
The circuits of block 720-27 operate on one input statement.
through the switch 720-26 corresponding to the character position value.
to change the signal ZCN0~2 given to the output character position.
exchange. No conversion is required for 9-bit characters.
(ie, input character position = output character position). The 2-bit RTF1 register 720-42 is written
Holds character type information for child 1, 2 bits
RTF2 register 720-46 for descriptor 2
Contains character type information. 1 bit RTF3
Register 720-52 contains the character data for descriptor 3.
Retain type information. Is descriptor 3 a 9-bit character?
Detector 720-50 registers RTF3.
Set the star to binary 1. in all other cases
, the RTF3 register is set to binary zero.
As you can see from the drawing, these registers are
720-40. 5-bit ROMP registers 720-70 are edited.
Stores "micro-operation" values necessary to process instructions
However, the 4-bit RIF register 720-63 is
The information field (IF) value for an instruction like
Remember. 9-bit RCD register 720-6
4 is a comparison instruction for storing the first operator value.
used during operations. 5-bit RTE8 register
Detector 720-68 responds to the load command.
in response to the load signals formed by the controllers 720-74.
and the 8th edit insert table entry value.
Store the 5 most significant bits. REF1LL Regis
The data center 720-22 connects the device via lines ZIDD0 to ZIDD8.
To store the signal received from 704-150
used. RAD registers 720-24
Receives from device 704-3 via lines ASFA34-36
Stores character position bits. Indicator fritz for blocks 720-80
The flop is stored in RMOP registers 720-70.
Stores the operation result specified by the content. This i
The indicator is a 2-bit MOP indicator A.
(MOPIA) and 3-bit MOP indicator B
(MOPIB) and a 1-bit END indicator.
I'm reading. This MOPIA indicator is as follows.
It is decoded easily. That is, 00 MOP execution operation 01 LOAD MOP operation 10 MOPIB tests 11 N/A This MOPIB indicator is similar to the MOPIA indicator.
Another situation arises when the data has the value '10'. child
These are decoded as follows. 000 Length 1 indicator for underflow
state (AXP adder output equals 0)
L1UDF is set when L1 is finished.
) and CN1 overflow
Low indicator (CN1OVF) status
test the 001 Length 3 indicator for underflow
state (if the output of the AL adder is equal to 0)
L3UDF is set when L3 is finished, and
) and CN3 overflow
– indicator (CN3OVF) status
(Set when the output of the AP adder is equal to 0)
test). 010 LIUDF, CN1OVF, L3UDF and
Testing the status of the CN3OVF indicator 011 Decrement the value of length 2 by 1 and
between the L3UDF and CN3OVF indicators
Testing the status of the data and the second cycle
Underflow indicator with length 2 between
(L2UDF) and CN2OVF indicators
Testing the status of the data 100 During the first cycle L3UDF, CN3OVF,
Status of L1UDF and CN1OVF indicators
test of condition. RAAU rate during the second cycle
transfer of the contents of the register to EU714;
Decrease the value of length 3 by 1 and increase the value of CN3 by 1
minutes, L3UDF during the third cycle and
CN3OVF indicator condition test 101 Loading table entry values 110 Changing table values 111 N/A The END indicator is specified by the MOP value.
is set to indicate that the operation is complete.
ing. Auxiliary calculation/control unit (AACU) 722-3i
figure AACU722 is used as a pointer addition circuit network.
Three parallel adder networks 722- shown in the text
2,722-6 and 722-8 and exponent addition times
and a length addition network.
Pointer addition circuitry 722-2 has two banks.
The four registers (RPO-RP3 and RP4~
RP7) Includes 720-20 and 720-22.
Ru. Each bank is used for selecting the data to be written.
its own multi-position switch 722-23;
722-24 and for selecting the data to be read.
1-to-4 position output switch (i.e., switch 72
2-27, 722-28, and 722-29,
722-30). Furthermore, bank 722-
20, its output is ZRPA switch 722-23
A second input is sent to select another input data.
power switch 722-32. ZRPC switch 722-32 and ZRPA switch
register bank 722-23 and register bank 722-2.
0 is bits 64-6 depending on the microinstruction style.
8 (ZRPAC field), bits 69 to 71
(ZRPAC-3 field) or bit 67
(ZRPAC-4 field)
controlled at times. ZRPA switch 722-23
ZRPC switch 722- through the first position
one of the outputs from 32 to the statement via the second position.
Address change/loading for character device 720
Character Offset for Address Register Instructions
The value for the loading of the
Select a character pointer for a 9-bit character via
You can choose. ZPA switch 722-27 and ZPB switch
722-28 are bits 59-60 respectively
(ZPA) and bits 61-62 (ZPB) control
RP0 to RP3 register bank 722-20 below
Select the data. ZRPB switch 722-2
4 and register bank 722-22 are micro
Instruction style type, bits 74-78 (ZRPB-
0), bits 69 to 73 (ZRPB), bits 72 to
74 (ZRPB-3) or bit 68 (ZRBP-
4) simultaneously by one control field depending on
controlled. ZRPB switch 722-4 is the first
adder output switch 722-36 through the position of
output from the character device 720 via the second location
Information field, 9-bit statement via third position
One word or character pointer value for the character, the fourth or
and the statement for 9-bit characters through the fifth position.
character pointer value can be selected. ZPC switch 722-29 and ZPD switch
722-30 are bits 57 to 58, respectively.
(ZPC field) and bits 67-68
RP4~RP7 register under control of (ZPD field)
select data from the data bank. From Figure 3
As you can see, switches 722-27 to 722-
The output from 30 is the A and B operator switch 72.
2-25, 722-26. These
The output of the switch is sent to the pointer adder 722-34.
Given. ZAPA switch 722-25, ZAPB switch
722-26, and adder 722-34.
One control file depending on the format of the macro command
bits 79-84 (AP field) or bits
Same as 82-83 (AP-3 field)
controlled at times. As you can see from the drawing, ZAPA and
and ZAPB switch 722-25, 722-26
is output from ZPA, ZPB, ZPC or ZPD switch.
force, or a constant value provided to adder 722-34
Select. ZLX speed operated under microprogram control
Itsuchi 722-36, ZXC Switch 722-3
8, RSC registers 722-40, and ZRSC registers
Itchi 722-42 performs shift count
and is configured to provide a device shifter. or
ZSC switch 722-38 supports ZRPC and
ZRPA switch 722-32 and 722-23
to the RP0-RP3 register bank via
is RP4~ via ZRPB switch 722-24
Data via RP7 switch bank 722-23.
can be used to load data. ZXL switch position selection is bit 48-49
(ZLX field). ZSC
Switch 722-38 is bit 50-52
ZLX switch 72 under the control of (ZSC field)
Used to select one of 2-38 outputs.
RSC register 722-40 has bit 47
ZLX switch 72 under control of (RSC field)
The rightmost 6 bits from the output side of 2-38 are
is coded. 2 position ZRSC switch 722-4
2 determines which of the two sources corresponds to the execution unit 714.
to give the shift count. Bi
84 (ZRSC field) is the shift cowl
Bits 138-143 as a component source
(CNSTU/L field) or RSC register 7
Select one from 22-40. The last group shown in block 722-2
The circuit consists of ZAAU switch 722-44 and switch
connected to receive the output of the Tuchi 722-44.
RAAU registers 722-46.
ZAAU switch 722-44 is register 722-44
used to transfer data to 46. this
, the data is passed through section 704-5.
Transferred to execution device 714 on ZEB lines 0 to 35
Ru. The input of ZAAU switch 722-44 is bit 5.
Selected by 0-52 (ZAAU field)
Ru. The first position is the character via line ZOC0-8.
Provides a 9-bit character output from device 720. No.
The second and third positions are blocks 722-6 and 722.
-Display output from length adder and exponent adder of 8
used to. RAAU register 722
-46 is bit 47 (RAAU field)
In response, load from ZAAU switch 722-44
be done. As can be seen from FIG. 3i, the exponent adder network 72
2-6 are four registers (RXPA) forming one bank.
-RXPD). This bank 722-6
0 is multiplex for selection of data to be written
position switch 722-62 and the data to be read.
1 to 4 position output switch for selecting the
722-64 and 722-66)
do. ZXP switch 722-62 and RXPA-
RXPD register bank 722-60 contains bits
59-62 (ZXP field), bit 65-6
6 (ZXP-1 field) or bits 75 to 7
7 (ZXP-3 field). The first position of ZXP switch 722-62 is index
The result of the operation is loaded into register bank 722-60.
used to code. The second position is the length
to store the result from adder 722-8 of
used. The next or third position is character device 7.
Used for storage of index values received from 20
Ru. Finally, the fourth position is RPIR line 24-3
To memorize the digit movement information of the numbers received from 5.
used. ZXPX switch 722-64 and ZXPR switch
722-66 are bits 63-64, respectively.
(ZXPL field) or bit 64 (ZXPL-1
bits 65-66 (ZXPR field) and bits 65-66 (ZXPR field)
register bank 722- under the control of
Select data from 60. switch 722-6
The outputs from 4 and 722-66 are respectively A
Operator switch 722-68 and B operator switch
Given as input to Tutsi 722-70
Ru. These switches are output ZAXP switch 7
22-74, which generates the exponential output value given to
A pair of 12-bit adders in locks 722-72
Given the selected inputs for (AXP and AXM)
I can do it. 1 control field AXP (bit 69
~73) is ZXPA switch 722-68,
ZXPB switch 722-70, adder and
ZAXP switch 722-74 operation and RE
Controls the loading of registers 722-76. One adder AXM is generated by an AXP adder.
If the signed sign is negative (i.e., AXP code
The indicator controls the selection of the ZAXP switch.
RE register 72 to give the absolute value when
2-76. ZXPA switch 722-68 is in the first position.
The contents of RE registers 722-76 are
or via the second position ZXPL switch 722-
64 can be selected. ZXPB
Switches 722-70 are configured via a first position.
Give the numeric value to RDI lines 0-7 via the second location.
The resulting binary floating point exponent signal is placed in the third position.
Digits of numbers given to RPIR lines 24-35 via
Move value to ZLNA switch 7 via the fourth position.
Outputs can be selected from 22-84. Operator length data similar to network 722-6
Third summing circuitry 722-8 for data management
is one bank of four registers (RLN1
~RLN4). bank 722-80
is the multiplicity for selection of data to be written
position switch 722-82 and the data to be read.
A pair of 4-position output switches (immediately
722-84 and 722-86)
do. ZLN switch 722-82 and RLN1~
RLN4 register bank 722-80
Bits 59 to 63 (ZLN-1
field), bit 63 (ZLN-2 field)
), bits 79 to 81 (ZLN-3 field),
Or bits 79-83 (ZLZ-4 field)
More controlled. ZLN switch 722-82
and output the output of the length adder as the output of the second digit.
ZAXP switch 722-74 output via
from RSER lines 24-35 via the third location.
Gives the length field value. Furthermore, this switch
is the length of the digits from the RSIR line via the fourth position.
field value through the RDI line through the fifth location
Shift count value from 11 to 17, 6th position
input to register bank 722-80 through
Give the length value from RCH line 24-35 as force
Ru. ZLNA switch and ZLNB switch 722-
84 and 722-86 respectively
Itchi 722-88 and B operator switch 72
Bits 53-54 as input for 2-90
(ZLNA field) and bits 55-56
register bank under control of (ZLNB field)
722-80. The output of these switches is 12 bits long.
(AL) Provided as input to adder 722-92.
available. ZALA switch 722-88, ZALB
switch 722-90 and AL adder 722
-92 are all bits 74 to 78 (AL file
control). ZALA switch 722-
88 through the first position as one operator
Set the output of the ZLNA switch via the second position.
ZPC Switzer through the 3rd position, number field
output of the digit length frame via the fourth position
Select yield. ZALB switch 722-90 is one operator.
the constant field through the first position, and the constant field through the second position.
ZLNB switch 722-86 output via position
, the output of the ZXPL switch through the third position
from RDI lines 11 to 17 via the fourth location.
The soft count value is sent to the ZPC screen via the fifth position.
The output of the switch is sent to the ZPA switch via the 6th position.
ZPC switch 7 through the seventh position.
22-29 bit positions 6 and 7 can be selected.
can. Device 722 has one scratch on device 714.
of another group to give a padded address.
Contains circuits. These circuits include ZSPA switches.
Tsuchi 722-100, RSPA register 722-1
02, and ZRSPA switch 722-104
each of which contains bits 48-49 respectively.
(ZSPA field), bit 47 (RSPA field)
bits 50-52 (ZRSPA feed)
control). ZSPA switch 722
-100 is passed through the first position as one output.
Compatible with clutch pad address field
bits 91-97 are also ported via the second location.
Selecting the output of inter adder 722-34
I can do it. ZRSPA switch 722-104 has one output and
register 722-102 through the first location.
Scratch the contents of the
address field through the third position.
and the descriptor values given from RSIR lines 32 to 35,
RSPR of device 704-150 via fourth location
Values from registers can be selected. Change
, device 722 registers RSIR register 704-15.
Low with the signal corresponding to bit positions 21 to 23 of 4.
A pair of registers 722-106 and 722
-108 included. One register is the 6th
Microinstruction word, FPOP flipflop, in figure b
Load when bit 53 of the lop is a binary 1.
be done. These registers are the RDESC registers.
Loading according to the status of 704-140
(00 or 10=R1DW, 011=
R2DW). Various control frames used by AACU722
The yield signal is input to register 722-1.
Various microinstruction words loaded into 12
obtained from decoder 722-110 that receives the bits.
It can be done. Cutlet device 705-Figure 4 overview The cutlet device 750 has five main sections:
i.e. command buffer section 750-1, control
Section 750-3, cutlet register section
section 750-5, cutlet storage section 750-
7, and instruction buffer section 750-9
It is divided into. Directive Batsuhua Section 750-1 Directive buffer section 750-1 is a 4-way
Write command buffer 750-100 and 4 words
It has a code read command buffer 750-102.
These are counters 750-140 and 750-1.
Addressed via 06. Write ZAC
Batsuhua 750-100 has one ZAC writing finger
Provides memory for commands and reads ZAC buffer
750-102 supports up to four read ZAC commands.
provide memories to Processor 700 sends commands to interface 6
Selector switch via 05 RADO/ZADO line
750-110 to the first location. P
The Rosesa 700 sends cutlet command information to the DMEM.
and selector switch 750- via the DSZ line.
112 to the first location. The state of these lines
status is held or stored in registers 750-114.
Ru. As can be seen from Figure 4, this information is also
written to 750-100 and 750-102
It can be done. In addition to the cutlet command signal, the processor 700
Set up the DREQCA line. processor 700
may perform other types of operations on cutlet device 750.
When you want to perform the
HOLD-C-CU, CANCEL-C,
CACFLUSH, BYPASS−CAC, READ IBUF,
READ EVEN). The status of other control lines can be determined using their outputs.
ZAC Batsuhua 750-100 and 750-102
decoder 750-116 that enables the
It is decrypted by Further, the processor 700
For certain types of write commands via lines DZD0-3
Transfer the zone bit signal for the These
The signal is sent to the RDZD register via switch 750-134.
The data is loaded into registers 750-132. Is this here?
This content is sent via switch 750-136.
A set of bytes is given to the CBYSEL line. Change
, the signal on the DZO line is switched to switch 750-13.
9 to the MITS line. other zones
The signal (bits 5-8) is the RC address register.
750-140, then switch 7
Another set of bytes CBYSEL via 50-142
given to selective lines. Multiple busy bit registers 750-12
RZAC buffer 75 using 0,750-122
Which locations in 0-102 are available
Determine. The state of these registers is
Priority deco to select available bus locations
The data is decoded via the coder circuitry 750-130.
The values formed are stored in registers 750-106.
For read ZAC buffer 750-102
used as the write address. Katsushi Kaname
The request is to retrieve the auxiliary store (MEN memory).
(The cutlet's mistake is the state of the signal BSPD.)
), the appropriate busy bit, or both.
SIU response that will generate one busy bit
(ARDA signal). this
The busy bit indicates the signal for one of the BSY lines.
A decoder (Fig.
(not shown) to a pair of lines SETBOTHBSY and
Set by signal given to SETONBSY
be done. For example, readout single finger (not bypassed)
) yields two SIUARDA responses, each of which
A response containing a pair of words. In this way, both
The in-use bit of the other is set. Single read bar
In the case of the IPAS Directive, only one SIU ARDA response
An answer arises. Therefore, only one bit in use is set.
be tested. Resetting this bit in use
sends the signal from SIU100 via RMIFS line.
via RSPB registers 750-124 that receive
Occurs in response to an ARDA line. More specifically, register 750-12
The contents of 0 and 750-122 are as follows:
When the base number is 1 (i.e., it corresponds to this block)
ongoing bits are not set), as described above.
Set according to the number of ARDA responses. decoder times
Paths 750-130 decode the status of the busy bits.
and read counter registers 750-106.
Next blank space in ZAC buffer 750-102
Set the appropriate address value to indicate the location. The same address signal PRACW0~1 can also be read
switch 750-139 in case of command.
given to the position. From here, this signal is 4 bits.
loaded into MITS registers 750-138 of
and is given to the MITS line. Main storage device 800
is the required pair of data words of a block.
At the same time as the transmission, the encoded signal is transmitted via the MIFS line.
and returns it to the cutlet device 750.
These signals are then sent to the 4-bit RMIFS register.
750-125 and then the control state
RSPB register when signal HCHCFD is binary 1
750-124. value received
is in registers 750-120 and 750-122.
Resetting the memorized display of appropriate in-use bits
cause ing. RMIF bit signals 2 and 3 are generated from appropriate commands.
Read RZAC buffer 750-1 for reading
Used for 02 address command. Furthermore, in the main text
As explained, the out pointer circuit
The signal from (COUT, not shown) is the readout ZAC buffer.
Accessing commands stored in Tsuhua 750-102
used for Registers 750-124 and 75
The in-use bit display stored in 0-126 is:
For the exclusive OR circuit of blocks 750-132
given as input. These circuits are
Produces an output signal that indicates the number of bits in use that have been read.
Use it to accomplish your goals. The output of these is still 4th place
Different positions of selector switch 750-133
given at the location. RMIFS bit signals 2 and 3
to select an appropriate location in response to
Therefore, the switch 750-133 outputs the signal
SECRCV occurs, and when this condition occurs, the cutlet device
750 receives one block of second pair of words.
Decide on the amount. SECRCV signal is block 75
Given as input for 0-3. Writing ZAC buffer 750-100 and reading
The output of the output ZAC buffer 750-102 is 2
Position switch 750-150, 750-152,
750-154, 750-156 and 750-
given to each of the 158 groups. ZAC
The output of the power switch 750-150 is
SIU via Chi 750-170 and 750-172
Loaded into output registers 750-174.
The output from ZAC switch 750-152 is
Via Itsuchi 750-177 and 750-178
Load a pair of data registers 750-180
be done. Output of switch 750-154 and 750-158
Power is given to another switch 750-160 and the
It is stored in the remaining register 750-162. sweets
The output of switch 750-156 is output from switch 750-1.
Decoder 750-16 with 60 DMEM outputs
given to 6. Other output from this switch is
A decoder 750-168 is provided. In addition,
The output of switch 750-158 is decoder 750-
164. Decoders 750-166 are DMEM0 to 3 lines
The cutlet received from the processor 700 via
Directive and buffer 750-100 and 750-1
Decodes the command read from 02 and stores it in Katsushie memory.
Command to device 750-7 and registry 750-5
Generate a signal to transfer. That is, Katsushi
What information can be obtained using the E-decoder 750-166?
is transferred from the process 700 to the cutlet storage device 750-
7. Decoder 750-1
68 decodes the state of the BYPCAC and DSZ1 signals.
Ru. The source of these signals is the processor 700
or is found to be compatible with switch 750-154.
There will be. Decoder 750-164 is buffer 750-1
Decode commands read from 00 and 750-102
and MEM memory (auxiliary storage) via SIU100.
Generates a signal to transfer commands to the controller.
That is, using the S decoders 750-164 to
SIU from Tsuhua 750-100 and 750-102
Controls sending of information to 100. Furthermore, the ZPSW switch 750-178
via switch 750-172 through the location of
To transfer to SIU100 on DTS line
ZAC from processor 700 on RADO/ZADO line
Select command or RDO, RDI data register
The cutlet storage device 7 via the star 750-180
Write main memory data to 50-7. ZPSW750
-178 second position is ZALT switch 750-
177 data output to DTS line (ZAC data)
or RDO, RDI register 750-1
80 to the Katsushi storage device 750-7.
to write main memory data from the DFS line, or
sends the ZAC command to the processor 700 via the ZDI line.
Forward. Using ZACSW2 switch 750-170
ZAC command (1st position) or from ZAC buffer
Transfer data to SIU10 via DTS line (second location)
Transfer to 0. Control section 750-3 This section handles various commands.
During the required operating cycle of the cutlet device 75
A number of constraints generate signals for ordering the zeros.
Contains a state flip-flop. Furthermore, books
The section provides the required restraint for the required operating cycle.
Contains the necessary logic circuitry to generate control signals.
For purposes of the present invention, these circuits are
It may be configured in any way. Therefore, the description in the main text
For the purpose of simplifying the
Control state flip-flop and
Only a simple explanation and logical formula about the control logic circuit.
show. The control state flip-flop performs the following data transfers:
A set of timing sequences that control the transmission sequence.
Generate cans. That is, (1) From processor to cutlet and SIU (cutlet and
and operations on SIU) (2) From processor to SIU (to SIU of write data)
transfer) (3) From ZACBUF to Katsushie (for Katsushie)
operation) (4) From ZACBUF to SIU (operation on SIU) (5) From the processor to ZACBUF (stored in buffer)
written data) (6) From SIU to Katsushie Processor (2 words)
transfer) (7) From SIU to cutlet to processor (1 word
transfer) This transfer operation uses the flip-flop shown below.
Ru. control state flip-flop QATB flip-flops are available starting from SIU100.
Transfer information to Tsushie 750 and processor 750
The first set in the first sequence allows
1 flip-flop. The QATB flip-flop is based on the following logical formula,
According to ARDA/DPFS, the set value is set per cycle.
be tested. THCFD flip-flops start from SIU100
The furling cycle that received the information
OATB to processor 700 via ZDI line.
Next frame set in the first sequence to be sent
It's a lip flop. THCFD Flip Flots
The loop is divided into one cycle according to the following logical formula.
is set. That is, SET: OETF=ARDA・ The UGCOGTH flip-flop is set
Then, setting/resetting the F/F bit
setting, ongoing bit setting, RR bit
setting, register section address
Writing MSA to and to Katsushie memory
Allows writing of data for a single write command of
Make it. This is set and set according to the logical formula below.
will be reset. That is, SET:・SET−COGTH RESET: (): −1・−
HOLD−CAC・CACBYS1＋NO−
HOLD−CAC UGSOGTH flip-flop to SIU
This is the first set in the CPU sequence. Se
the first data word is the DTS line.
can be placed in This is 1 according to the logical formula below.
Set for cycles. That is, SET:・DWRT However, DWRT=CWRT・SNG+CWRT・DBL+
CWRT・RMT. The CAOPR flip-flop is
Set in response to a read. This is below
is set for one cycle according to the logical formula
Ru. That is, SET: SSET−IN・CLD−IBUF(CBYP−CAC
+) +CPR-RD・-
CAC・+(CRD−SNG+CRD−
DBL)・(CBYP−CAC+)+
CRD−CLR+CRD−RMT+CWRT−
SNG+CWRT−DBL+CWRT−
RMT. CPR-FF flip-flop is a cutter device
responds to the DREQ-CAC signal from processor 700
used to determine when to previous cycle
During the cycle, this flip-flop is set to binary 1.
When the cutting machine is set to PREREAD, INST-
F1, INST−F2, LDQUAD, RD−SINGLE or
Requests will not be met except for RD-DBL type directives.
I don't answer. This is set according to the logical formula below.
and reset. That is, SET: (CINST-F1+CINST-F2+CLD・
QUAD+CRD・DBL+CRD・SNG)・
(CBYP・CAC+)+CPR−RD・
−・． RESET:=-. RBPSD flip-flop is HOLD−ON−
Processor 70 in case of MISS or BYD-CAC conditions
Used to turn 0 off. day
When the data is returned from SIU100, this flip-flop
The loops are reset except for the INST-F1 cycle.
It can be done. In case of IF-1, 4 words are received from SIU
This flip-flop is reset after
Ru. This is set and reset according to the logical formula below.
is set. That is, SET: SSET−IN・−・CRP−RMT
+CRD−CLR+(CINST−F1+CRD
−SNG+CRD−DBL)・(CBYP−
CAC+BPSD) RESET: () = THCFD・SEC−RCV・
CINST−F1＋DATA−RECOV・
−1−. control logic signal 1 The CPSTOP signal turns off the processor 700.
This is the signal used to CRSTOP=FBPSD=REQ CAC・[RDTYP・
RZAC−ALL−BSY+PRFF・(PR−
RD+INST−F2+LDQUAD+RD−
SNG+RD-DBL)+CAC-BSY1+
CAOPR＋UGCOCTH〕＋RBPSD＋
DBL・FF+PENBIT・FF+(RD−
IBUF/ZDI・CAC−BSY−1)+(RD
−IBUF/ZDI・LD−QUAD・FF)+
(UGCOGTH・RD−DBL・CAC−
BSY1). 2 The CAC-BSY1 signal is being used by the cutlet device.
Display the time when . CAC−BSY1=OATB+THCFD. 3 [SF/E-WRT signal has fill/blank bit
Write enable signal for setting and resetting.
be. [SF/E-WRT=・1・
(UGCOGTH)・・−
DBL・BYP−CAC・−・
(−2++)・−
CAC・DLY−BPSD. 4 [SPEN1-WRT signal is the continuous operation bit]
This is a writable signal for setting the
Ru. [SPEN1−WRT=−1・(UGCOGTH)・
(INST−F2+LD−QUAD+PR−RD
−SNG・−＋RD・DBL・
−). 5 [SPEN2-WRT signal is
Continues when all data is received from main memory
Writeable signal to reset bits in
This is the number. [SPEN2−WRT=THCFD・SEC−RCV・(INST
−F2+LD−QUAD+PR−RD+RD−
SNG+RD-DBL・-). 6 The RZAC-ALL-BSY signal indicates the status of the bit in use.
While using the RZAC buffer established according to the
Display the status of. RZAC−ALL−BSY=(RBB−00+RBB−01)・
(RBB−10+RBB−11)・(RBB−20+
RBB−21)・(RBB−30+RBB−31). 7 [SRMIFS signals are mainly data or status information]
Multiple port identifier bits when received from a storage device.
This is a write strobe signal that memorizes the
Ru. These bits are available in any RZAC buffer.
ZAC word associated with the data received by the location
(i.e., how much does this data contain?
Which of the several possible outstanding reads requires
). [SRMIFS=ARDA+AST 8 ALTSW0-DT signal enters from main memory
Store data in RDO and RDI registers
Ru. ALTSW0−DT=CAC−BSY1. 9 ALTSW2-DT signal is from ZAC buffer.
Transfer data to RDO and RD1 registers
Ru. ALTSW2−DT=DS−ALT+0− However, DS−ALT=DS−11+DS−12+DS−
13. 10 Signals OPSW0−DT to OPSW2−DT are
data from the processor to the processor 700 via the ZDI line.
ZDI switch to transfer the data word
Control. OPSW0−DT=RD−IBUF/ZDL OPSW1−DT=RD−IBUF/IBUF/ZDI(REQ
−CAC+UGCOGTH)・WDSEL0. OPSW2−DT=RD−IBUF/ZDI+WDSEL1・
(RD-SNG+INST-F1)+REQ-
CAC・・INST−F1+
REQ−CAC・・RDSNG
+REQ−CAC・・DBL−
FF 11 Signals ZACSW1−LC1 and ZACSW2−LC2
is for all Katsushi memory chips.
Switch 750-
702. This source receives directives
When using processor 700, ZAC buffer and
CADR address register. ZACSW1−LC1=1−4・−
−1・UGCOGTH. ZACSW2−LC2=CAC−BSY1+UGCOGTH. 12 Signal DATA-RECOV connects processor 700 to
Stop conditions (e.g. register restrobing)
recover from. DATA−RECOV=THCFD・(CINST−F1+
CRD+SNG)・(−1・
0＋THCFD・CRD−DBL・
(−1・WDSEL0＋FMIFG−
1.WDSEL0+FMIFS −1・WDSEL0+CBYP−CAC)+
THCFD・CRD−RMT. 13 The RD-BSY signal is the flip-flop signal in a certain state.
Establishes when the tip is reset. RD−BSY=RBB−00+RBB−01−RBB−10+
RBB−11+RBB−20+RBB−21+
RBB−30+RBB−31. 14 The SSET−IN signal is a flip-flop
Used to set the SSET−IN=・−・
−
FF・UGCOTH・・−
BSY1・〔−・−・
CINST−F2・CLD−QUAD・CRO−
SNG・CRD−DBL〕・[−・
RZAC−ALL−BSY〕・DREQ−CAC 15 SEC−RCV=−2・−3・[RBB
−00RBB−01〕+−2・
RMIFS-3・[RBB-10RBB-11]
+RMIFS-2・-3・[RBB
−20RBB−21〕+RMIFS−2・
RMIFS-3・[RBB-30RBB-31] 16 BPSD signal indicates cutlet hit condition.
Ru. However, SP-i-00-14 is not registered in the address register.
(stored address bits),
F/Ei is filled/blank bit “i” and also PENi
corresponds to the ongoing bit 'i'. In each of the above formulas, the symbol ・ is an AND operation
, the symbol + indicates OR operation, and the symbol + indicates exclusive OR
It will be seen that the operation is illustrated. Cutsiere register section 750-5 This section includes a four-level control register 75.
0-500 and 4 level set association address registration
Contains books 750-502. Register
) 750-502 contains 128 columns.
Each column has four levels of length 15 bits.
This allows each block to be divided into four blocks.
Provide space for columns. control directory
750-500 contains 128 10-bit locations.
each of which records a 10-bit word of control information.
I remember. The control information for each block is as shown in the diagram.
Like two round robin (RR) bits and
4 fill/blank (F/E) bits and 4 operations
Contains bits in progress. The F/E bit is
whether the value has significant digits (i.e., is valid).
indicate. For the cutlet hits that should occur,
The F/E bit must be set to binary 1.
stomach. A binary zero indicates the presence of an empty block. lounge
Robin bits indicate which block was replaced last.
Gives a count indicating how many times it was done. This count
is the F/E bit by counters 750-512.
The next to be incremented by 1 and replaced under the control of
Used to identify blocks. It can be seen from Figure 3
This operation is similar to round robin bits and
and a pair of F/E bits 750-
Occurs when read into 504 and 750-506
Ru. F/E bits are also round robin bits.
to registers 750-510 that control the incremental operation of
Read. That is, the round robin bit is
Which filling block has all F/E bits set?
should be used for new data.
Used after confirmation. the resulting value
(ADDRR0~1) is for switch 750-518.
given as input. All F/E bits
is reset by an initialization signal. F/E
Bits are set via registers 750-516.
can do. Processor 700 is in state
Issue a read request that is a miss during UGCOGTH
, the value “1000” is loaded into registers 750-516.
is coded. This value is the control directory 750-5
Written to 00. In the next request, the value
"1100" until all F/E bits are set
Loaded into registers 750-516, etc. The ongoing operation bit indicates that a particular operation is still pending.
used to indicate a certain time. For example,
Once set, the
indicates that all read data has not been received.
indicate. Therefore, during a read operation, the address
The directory signals a hit and sets the continuing bit.
When the cutlet device 750
Stop operation of 0. Therefore, for main memory
No new requests will be made. To set and reset the ongoing operation bit.
The network consists of a 4-bit buffer register 75.
0-520 and block decoding registers 750-5.
24, including decoders 750-512. Regis
During a write operation cycle, the data processors 750-520
signals via address registers 750-522.
Addressed and read by PRZACW0~1
During the cycle, signals MIFS2~3 are used to add
Response is specified. Block decoding register 750-
524 outputs each of the output signals BKDCOD0 to 3 as follows.
Force to binary 1 under the condition. That is, (1) if
If at least one F/E bit is zero, this bit
When t is set to binary 1, the corresponding continuation
The middle bits are set via decoders 750-512.
will be played. All F/E bits are set
and the following values for the round robin count:
is encoded and this within the set of four ongoing bits
The bit position is set to a binary 1. cutlet
750 receives all information from SIU 100 (i.e. 4W).
The ongoing bit is decoded only when a code (code) is received.
750-512. cash register
The contents of stars 750-520 should be reset.
Display the position of the ongoing bit. control direct
Ongoing bit read from rear 750-500
The decoder 750 performs updates as necessary.
-514 is given as input. This ongoing bit can be set and set under the following conditions:
will be reset. That is, SET:INSTF2(BYPCAC+CACMISS)+
LDQUAD (BYPCAC+
CACHEMISS) + PREREAD
(・CACMISS)＋
READSINGLE/CACMISS+
READDBL・・CACMISS RESET:INSTF2+LDQUAD+PREREAD+
RDSNG+RDDBL・． The actual control signals are as listed earlier in the text.
It's easy. As mentioned above, the address directory 750-
502 is 120 4 words each 15 bits long
Including groups. Each 15-bit word is
4 word block in memory section 750-7
Corresponds to the lock address. ZAC directive handles
writing to the cutlet device 750 or
Whenever a read from the ZAC buffer is involved,
Blocks included in 750-110 or 750-102
15 bits of the lock address are “set”
Comparison with address contents of directory 750-502
is compared to determine the existence of a hit or miss condition. Special
Directory 750-502 is a hit or miss.
Bit 0 of ZAC address for detection of power condition
The combination is performed for ~14. These bits
is a 2-position input ZACSW switch 750-53
ZAC11~18, 20~26 lines selected through 0
or ZADO/RADO 10 to 24 lines.
corresponds to the input address signal. The address of the set directory is the 3-position input switch.
Katsushi given through Tsuchi 750-702
Specified by address (CADDL0~6)
Ru. Therefore, it is read out and the four comparator times
Group of roads 750-536 to 750-542
4 blots given as input for each of
It becomes possible to inquire about the address of the client. comparator
Each circuit has its block address as ZAC address.
Compare with dress bits 0-14. circuit 750
Results caused by -536 to 750-542
is the F/E bit from registers 750-506.
of the first group with the corresponding input of the signal.
AND gate 750-544 to 750-550
is applied to the corresponding input side of . second group
AND gates 750-552 to 750-55
8 is AND gate 750-544 to 750-5
Which block is selected for the output from 50?
A signal given through a register indicating whether
Combined with ZEXTBK0~3. AND gates 750-552 to 750-55
8 is a cutlet device 750-700 and a blower
One group of directories for 750-560
1 group given as input to medium detection circuit
output block selection signal (i.e., the signal
CBSEL0-3). Block 750-56
0 circuits block the signal indicating the ongoing operation bit.
1 group logically combined with lock selection signal
and the AND gates 750-562, resulting in
is “ORed” by OR gates 750-564
Gives a directory hit signal on line BPSD.
The circuitry of blocks 750-560 is
Bits 0-14 match the contents of the directory
and the corresponding F/E bit is a binary 1, and the
line when the corresponding ongoing bit is a binary zero.
Control BPSD to binary 1. There is an error condition
Assume that Katsushie memory section 750-7 Section 750-7 has 4 blocks of 128 pairs.
2048 (2K) 40-bit words organized into
Includes two storage devices 750-700 with locations of
I'm here. This device is constructed using a known bipolar chip.
Consists of tupu. Katsushi storage device 750-
700 is given through switches 750-702.
7-bit address CADDL0~6
addressed. This address is in the holding register.
data 750-704. For this reason, 4W
4 blocks of the code are 1 to 4 position selection of 1 group
given as input to a switch (not shown).
It can be done. An appropriate block (level) is the line CBSEL0
Depending on the state of the block selection signal given to ~3
Determined by via switch 750-708
The signals given to lines CBYSEL0-7 are
make an appropriate selection of the bytes of the code and odd words.
cormorant. Byte selection between words 0, 2 and 0, 3
are independent and proceed as follows. CBYSEL0 (byte 0 selection) for words 0 and 2 : : CBYSEL3 (byte 3 selection) for words 0 and 2 CBYSEL4 (byte 0 selection) for words 1 and 3 : : CBYSEL7 (byte 3 selection) for words 1 and 3 Line CWSEX0 via decoders 750-706
The signal given through ~3 is for displaying the word
used for. This allows devices 750-700
Select a suitable bit of a group of memory chips consisting of
Secure the contents of the specified position. The words of the selected block are divided into many pairs.
OR (NAND) gates 750-712 to 750
-716 is given as input. OR game
Word output from the 2-position switch 750-
902 via the second location of the command buffer 750-
900 as an input and to the processor 700
Output ZDI switch 750-720 for transmission of
given to the first four positions. This switch's fifth
The location indicates the word contents of registers 750-180.
Processor 7 via ZBP switch 750-902
Give to 00. Finally, ZDI switch 750-7
The sixth position of 20 is commanded via ZIB lines 0-39.
outputs of command buffers 750-900. As can be seen, during the write operation cycle,
The word contents from registers 750-180 are
It is given as one input for 750-700. Command Batsuhua Section 750-9 This section is for Switch 750-902.
Data input from registers 750-180 via
Includes 16 word instruction buffers 750-700 to receive.
I'm reading. As mentioned above, the cutlet storage device 750
-700 output is also switch 750-902
to buffers 750-900.
Control provided via switches 750-904
signals and address signals to decoders 750-90
6 and read address counter 7
50-908 and write address counter 750
- Used to set the 910 to the appropriate state.
Ru. The address output of these counters is
via 750-912 and 750-914
Provided to Tsuhua 750-900 for reading and
Provide a suitable address during a write operation cycle
used for. Description of action 1 to 10, the operation of the present invention is illustrated.
for processing an editing command having the format of Figure 8a.
This will be explained as follows. This editing command is the 8th
It is assumed that the code is encoded as shown in Figure b. This instruction is called the Extended Instruction Set (EIS).
Handling bytes, characters, and bit strings
included in the instruction repertoire with the ability to
Ru. This instruction has a multiple word instruction format. No.
Word 1 is the basic word containing the operation code.
an instruction word, followed by the first, second, and
There are 3 descriptors. Bit 0
~17 contains additional information regarding the operation. Special
This bit is the operator (operand) disk.
Specifies the address changes to be made for the printer.
Two 7-bit change files encoded to
Contains de. Here, this field is zero.
Let's assume that. Bits 18-27 are used to specify editing operations.
contains the encoded OP code value, but bit 28 is
Interrupt service bit assumed to have value 0
It is. Bits 29-35 are descriptor
to specify the address change to be performed for 1.
Another 7-bit change field encoded with
Compatible. This field contains all zeros.
Assume that. The second word is 18 bits for descriptor 1.
The 3-bit CN1 file contains the address of the
The word specifies the original character number in the word being matched.
The 2-bit TA field is
Specifies what types of alphanumeric characters are in the data.
The 6-bit N1 field is
A data string containing a number of characters or bits, i.e.
to specify the number of characters, or bits, in the register.
is encoded as Maximum allowed length is 63.
The TA field is encoded as follows. code data type 00 9 bits 01 6 bits 10 4 bit The CN field for 9-bit characters is as follows:
It is encoded as follows. code word count 000 0 〓 〓 〓 〓 110 3 The third and fourth largest words are data respectively.
Contains similar information for scripters 2 and 3.
I'm here. Editing instructions implement editing functions in a valid manner.
Requires micro operations (MOP)
Ru. Sequence of microsteps to be executed
The second operand data is contained in the storage device.
Matched by scripter word. micro
Some operators accept a string of characters to be manipulated.
Requires a special character to insert into the ring
Ru. These special characters can be scratched by device 714.
Edit insert table stored in padded memory
included in. This table has up to 8 9 bits
character, and the processor 7
00 initializes a table containing the following values:
That is, TABLE ENTRY 12345678 Microoperation operand day
Cryptor (OP2) is executed during the edit command
9-bit character specifying micro-operation
Indicates the string. each 9-bit character
specifies the micro-operation to be performed.
5-bit MOP field encoded to
and the number of source digits being manipulated, or
Editing used according to the sign of the MOP field
Any specific entry number in the insert table
A 4-bit IF encoded to specify which
It has a format that includes fields. micro operator
- The length of the receiving string is usually shortened.
(L3) is terminated. The other fields of the EDIT command are shown in Figure 8.
It is encoded as follows. More about this command
To learn more, visit Honeywell Information
System Inc. has a document “Series 60 (Level 66)/
6000 Macro Assembly Program (GMAP)”
(Copyright 1977, Order No. DD08B, Rev.0)
I want to be In this example, the instruction in Figure 8b is
750-700.
Also, specified by descriptors 1, 2, and 3
The operand data is recorded in the cutlet device 750.
It is assumed that it is not stored and exists in the main storage device 800.
do. In Figure 10, the editing (MVE) instruction
The first cycle of processing
Corresponds to the end cycle [this must be the END cycle]
You will understand that. This cycle follows the logic below
According to the formula [END control signal is controlled to binary 1]
It is ensured by That is, [END=FESC100・DPIPE1−4+…… The state flip-flop FESC is
of the microprogram, such as during the execution of a gram instruction.
It is a binary 1 when operating under control. signal
DPIPE1-4 seem to have new processor registers.
Instruction-loaded (i.e., type 1) pipeline
Bits 38-40 specify restart of the
When encoded, it becomes a binary 1. This kind of mutual trust
Since the numbers FESC100 and DPUPE1~4 are binary 1,
Therefore, [END cycle is in block 704-102]
It enters through various circuits. [During the END cycle, the microprogram
Processor 700 under control executes the first word of the edit command.
from the buffer 750-900.
Blocks 704-150 via ZIB lines 0-39
RBIR, RSIR, RBASA, RRDXA and R29
Transfer to register. In this example, register
RBASA, RRDXA and R29 are set to zero
(i.e. bits 0-2, 32-35,
and the field corresponding to 29 is zero). If the previous instruction was not a transfer instruction, the
The processor 700 executes the next word (data) of the edit command.
Buffer 75 for reading from Cryptor 1)
0-900 read counter 750-910 to 1
In order to increment the line [RDIBUF/ZIB]
give. At the same time, the content on the ZIB line
The switch 704-172, 704-170
and decoder 704-1 via 704-173.
Signals generated by 06 [SRBIR and
[In response to SRSIR, registers RBIR and RSIR
loaded into. Switch ZBASA, 704-1
75, 704-176 and 704-177
and responds to the signals [SRBASA and [SRRDXA].
Bits 0-2 are RBASA register 704-1.
44, bits 32-35 are RRDXA
Loaded into registers 704-158. bit
29 is a signal via switch 704-183.
[Loaded into R29 register in response to SR29. If the previous order was not a transfer order or an EIS order
Assuming that the contents of instruction counters 704-310
is ZIC-N switch 704-314 position 3 (immediately
001) to the adder 704-312.
is incremented by 1. Next, block 704-102 in FIG.
Responds to FPOA state flip-flop switching.
Answer and enter cycle FPOA. This FPOA fritz
The flop is configured in hardware according to the following logical formula:
Set to binary 1 under control. That is, SET=[・(DIBFRDY・・
[...DPIPE1~
4) i.e. pending conditions on the pipeline (i.e.
If there is no signal HOLDI00=1), [END cycle]
Following this, the FPOA cycle is entered and the instruction buffer is
750-900 are not blank (i.e.
DIBFEMTY00=1) at least one processor 7
Transferable instructions for 00 (i.e.
DIBFRDY100=1), and the previous instruction is a store
Compare instruction (i.e. STRCPR00=1) or execution 1
It is not a repeat instruction (i.e. DXEDRPT00=1)
IP line has been restarted (i.e. DPIPE1~4=
1). At this time, the RBIR registers 704-152 are
Instruction OP code field and disk
Address change field for ports 1, 2, and 3
Memorize MF1, MF2, MF3. of this cycle
Between, flag flip-flop FID and FRL
is generated by the circuits of blocks 704-124.
signal [ZIDD switch 70 in response to ZIDD]
RBIR register 7 given via 4-180
Corresponds to bits 30 and 31 of 04-152
Set by a signal. Also, R29 and
RRDXA registers 704-162 and 704-15
8 is provided via ZIDD switch 704-180.
Bits of RBIR register 704-152 obtained
29 and bits 32-35 and corresponding signals
is set. Similarly, the FPOA state flip-flop
As a result, the RDESC1 flag is set to binary 1.
The lipflop is reset to binary zero. So
The values loaded into these registers are shown in Figure 8b.
As you can see, it is zero. Under hardware control, the value '00' is the RDESC record.
registers 704-170. In other words, the cash register
Star 704-140 RDESCO flip float
The program is set and reset according to the following formula:
be done. That is, SET: RDESCO=Each level of LARGECU field
JISTA + SMALLCU field
FMTD＋DESC1・(DNUM3EDIT)・
FPOP. RESET: RDESCO=FPOA+LARGECU fee
field + SMALLCU field. In this case, the RDESCO flip-flop
is the FPOA state fritz of block 704-102.
As a result of the flop becoming a binary 1, it returns to a binary 0.
is set. The RDESC1 flip-flop follows the following logical formula:
set and reset. That is, SET: RDESC1=LAGRECU field+
SMALLCU field + DESCO・
FPOP・ RESET:FPOA+(DESC1・
(DNUM3EDIT)・FPOP＋LARGECU
Field + SMALLCU field Furthermore, the commands given to lines ZIB0 to 39 are
The contents of the next word (descriptor 1) are the control
In response to the signal [SRSIR, the RSIR register 704-
154. Block 704-106
The signals generated by the circuits [SRBASA and
[In response to SRTYP, bits 0-2 are ZIB times
Load from line to RBASA register 704-156
Bits 21 and 22 are sent via the ZIB line.
Loaded into RTYP register 704-160. 00 in the TA1 field specifying a 9-bit character
Values are switches 704-178 and 704-17
9 to RTYP registers 704-160.
is coded. Switch 704-174 and 704-1
75, zero is also sent to the RBASA register 704-1.
56. Also, block 704-10
8 and 704-128 are lines.
[Force RDIBUF/ZIB to binary 1. this
is the third word of the edit command (descriptor 2)
Read counter 750 by 1 for reading from
Increment -910. CCS stream via RBIR registers 704-152.
OP code signal given to Tor 704-200
is specified simultaneously with the occurrence of the clocking signal.
The contents of the memory location are sent to the output registers 704-202.
Let it read. As you can see from Figure 3, this content is controlled by the following
Encoded to contain information. That is, CCSO＝000 CCSR=0100, CCSS=11101, and CCSI=anything is fine Since the field CCSO contains zero, the block
Tsuk704-104 FNUM flip-flop
maintains the state of binary zero. CCSR field
is encoded to display a 4-word field.
When the editing command is completed, the appropriate amount of commands are copied.
Used to increment the counter. 10 bits in BRIR register 704-152
The OP code can be obtained from the CCS store 704-200.
suitable for proper sequence control and selection.
Transformed into 6-bit code. CCCS field
is decoded by circuits 704-100, and its
After ensuring a specific sequence and FPOP free
Switch the flip flop to binary 1. Immediately
The CCCS field, when decoded, is the instruction type.
indicates that is an EISEDIT instruction. FPOP flip-flop follows the following logical formula
is set and reset. That is, SET:FPOP=〔・(〔・
FPOA・DEIS・・DIBFRDY+
DESCO・FPOP・DEDIT+DPIPE−
6)＋…… RESET:EPOP= In this case, the descriptor is not needed.
The FPOP state flip-flop is set to
(i.e. NEEDDESC000=1), FPOA flippf
The loop is set (FPOA=1) and the CCS fee is
The command specifies the EIS instruction (DEIS = 1) and the CCS bit
DBIT=0, instruction buffers 750-900 are not used.
available (ie, DIBFRDY=1). During the first FPOP cycle, the address preparation device
704-3 is specified by the first descriptor word.
generates the specified address. That is, R.P.I.R.
Bits 0-20 of registers 704-154 (Y)
switches in response to R29 registers 704-162.
Addition via Tuchi 704-326 and AMD gate
Provided as one input to the device 704-322
(i.e. descriptor address). This value
When switch R29 is binary 1, switch 704-
In the RBASA register given via 328
Contents of address register selected by
will be added to. Since bit R29 is a binary zero,
Therefore, the effective address is this descriptor address.
corresponds to Output of switch 704-328
This switch is used depending on the state of bit 29.
It becomes zero because it is disabled. This valid ad
The response value is RRDXA register 704-158,
RTYP registers 704-160 and block 7
04-104 FNUM flip-flop contents
given via the ZX switch as a function of
given in the address change field (X or AR).
It can be done. These values are zero, so change the address
The field is zero. The resulting value is then set to switch 704-334.
The contents of RDESC registers 704-144 via
stored in TEAO at such location as specified by
Ru. Adders 704-320 add the same result value.
Specified by the contents of RBASB registers 704-144.
base value stored in the temporary base register specified
Add. Assume that this base value is zero.
Thus, the resulting address is
corresponds to a port address. The ZBASE value is also
TBASEO register via Tutu 704-332
is memorized. According to the present invention, under hardware control, the
Sesa 700 is a cutlet device that receives cutlet preread commands.
Issued at 750. For this reason, the cutlet device immediately
loaded with the required data and processed by processor 700.
Ensure that the collection command continues its processing. No.
As can be seen from Figure 9, this command applies to locations 1000~
The beginning of descriptor 1 data stored in 1003
The processor 700 processes this 4-word block.
When you are ready to use such data,
main memory in parallel with the instructions to be processed as if
The data is read from the location 800. That is, the look-ahead command is
The data required to execute the instruction is
retrieved in advance at the same time as the descriptor is processed
allow it. This process begins in the initial operational phase (immediate
specified by the instruction during operand fetch).
Increase the speed at which operations are performed. In this way, the original
The configuration of the
This has the effect of speeding up the process. A look-ahead command is generated as follows. disk
The absolute address of the decoder circuit 704-
124 [in response to SRAAO]
to the RADO register via the ZADOB switch.
is coded. Furthermore, bits 0 and 9 are forced to zero.
During this time, command bits 1-4 and zone bits 5-8 are
Replaces bits 1-8 from switch 704-46
via switch 704-40.
Bit 1 from RMEM register 704-130
~4 is the decoder circuit of block 704-118
is converted to a command code of 0111. this directive
The code specifies a memory read quad operation.
Ru. Zone bits 5 to 8 are input switches 704-
40 to binary 1 for reading.
It is not used for purposes. At the same time, the block
The various circuits 704-108 receive signals [MEMOTB to
[MEM3TB and corresponding "0111" look-ahead code]
generate. These signals follow the following logical formula:
is generated. That is,

【table】 Since the FPOP flip-flop is set,
The instruction has non-zero length (FIGNLEN control flag
DLNNZ established by = 1) Edit disk
the first flip-flop disk
Lipta field (DESCO=1) (FEIIN=
1) or the second descriptor being processed
(DESC1) is not completed (
or 2=1), these signals are binary 1s.
Ru. Obviously, these values are set at the beginning of instruction processing.
All can be binary 1s. These signals are then sent to decoders 704-116.
to RMEM0-3 registers 704-130 via
loaded. RMEM0~3 register 704-1
The contents of 30 are further given to DMEM0 to 3 lines.
Ru. Also, the circuits of blocks 704-108 are as follows:
Forcing RSZ register 704-132 to value “00”
generate a signal. The contents of this register are DSZ times
line to specify a complete word write (first
(not used for generating reading commands). deco
The register 704-120 registers the register 704-130.
At the same time as decoding the DMEM command stored in
Forces the DREQCAC line to binary 1.
BYPCAC line is binary zero in the case
It can be assumed that During the FPOP cycle, the corresponding TA1 field
The signals that are
switch 720-42 of device 720 depending on the situation.
transferred from RTYP registers 704-160 via
It can be done. This signal has the value '00' and is
The data field of data bit 1 consists of 9-bit characters.
Indicates that Also, N1 field indicating length
The signal corresponding to RSIR register 704-15
4 to bank via ZLN switch 722-82
Transferred to RLN1 register of 722-80. child
These signals are connected to the descriptor's data feed.
has a value indicating that the field has 16 characters.
Ru. As can be seen from the figure, RCN1 of the character device 720
Register 720-28 records descriptor 1.
Stored TEAO registers of banks 704-302
From lines ASFA34 to 36 and RAD register 72
of descriptor 1 given via 0-24
CN1 field and corresponding value “10₂” is loaded.
It can be done. This value is the starting statement to start processing.
The first data word of descriptor 1 as a
Specify character #2 of the code. Bank 7 of device 722
The RPO registers at 22-20 are
For your information, lines ASFA33-35 and ZPRA Suite
with the character pointer value "01" via the channel 722-23.
loaded. Then the signal corresponding to the MF2 field is R29
Registers 704-162 and RRDXA register 7
04-158 and FID of block 704-110
and transferred to the FRL flip-flop. Re
and these signals are sent to RBIR register 704-15.
ZIDD switch 70 from bit positions 9 to 17 of 2
4-185. From figure 10
These values are the same as the descriptor 1 descriptor.
All zeros indicate no changes to the data.
Ru. RDESC registers 704-140 are hard
represents the operation of descriptor 2 under software control
Value '01₂” is loaded. At this time, RDESCO pretend
The flop is reset, but
The RDESC1 flip-flop is set to binary 1.
This means that descriptor 1 is processed.
(DESCO=1), cycle is FPOP cycle
(FPOP=1), the instruction is a memory type instruction
(MEN to MEN or MEN to REG−
This is because it is not equal to 1). Again, processor 700 executes an edit command (disk
buffer for reading from the next word of the printer 3).
Read counter 750- of Tsuhua 750-900
To increment 900, limit the line to RDIBUF/ZIB.
Give a signal. Batsufu given ZIB line
The contents of descriptor 2 are RSIR register 7.
04-154 and bits from the ZIB line.
0-2 and 1-22 are RBASA registers respectively.
register 704-156 and TYP register 704-1
60. At this time, RSIR registers 704-154 are
Contains scripter 2, R29 register 704-15
6 has a zero indicating no address register change;
RTYP registers 704-160 are descriptors
2 data fields consist of 9-bit characters
It has a zero indicating that it is. Regarding the cutlet device 750, the signal
Give to lines ZPSWA0~39 in response to DREQCAC
The read-ahead memory command that has been received is sent to the counter 750-
RZA buffer 7 specified by the contents of 106
Written in blank locations 50-102. As mentioned above
The address in this blank space is
Determined by the situation. This entry is a hit or miss.
whether there is a failure condition (i.e., the state of the BPSD).
It is done regardless of the state of affairs). Read ZAC buffer
The contents of the control data will be used for the next cycle.
Addresses written to directories 750-500
give. Next, the cutlet command is sent to the cutlet decoder 75.
0-166, block 750-3
Which of the control state flip-flops is set?
Determine whether In the case of a look-ahead command, the cutoff
The failure results in the directory allocation cycle being
In this cycle, the address is the control delay.
F/E bits are written to
If not set, it will be set and appropriate
The ongoing bit is set and this operation is unfinished at this time.
. As mentioned above, directory allocation
Enters guess cycle and UGCOGTH state flip
The flop is switched to the binary 1 state. Professional
sensor 700 depending on the status of the CPSTOP00 line.
The key is to decide whether or not to continue processing.
It will be seen that it is device 750. Look ahead
For directives, TURNOFE1 and TURNOFF
Both signals are zero and line CPSTOP00 is kept at binary 1.
hold The state of line CPSTOP00 is
Continuous application of clock pulses to circuits
, thereby allowing the processing of processor 700 to
enable the continuation of In contrast, cutlet device 7
50 is a cutlet read command at the same time as failure occurs
In this case, the operation of the processor 700 is stopped. In parallel with decoding the command, the cutter device 750
Directory 750-500, 750-502
and access Katsushi storage devices 750-700.
do. Directory 750-500 and 750-5
02, and cutlet storage devices 750-700
is given via switches 750-702
Address signals from RADO lines 25-33
be accessed. Comparison circuits 750-536 to 75
0-542 is given from the line RADO~ZADO line
Compare the address entered with the directory address.
Ru. The first descriptor data is converted to cutlet.
Since there is no hit/fail signal, circuits 750-560
Keep BSPD in binary zero state. Therefore,
UGCOGTH flip-flop controls direc- tor
When the bird 750-500 is updated, the processor's
For signals BPSD and CPRRD immediately after request
Switched to binary 1 by signal SETCOGTH
Ru. During the directory allocation cycle, the RZAC
The address written to Tsuhua 750-102 is
Passed through ZAC switch 750-530,
data instead of being compared as in the previous cycle.
The information is stored in the directory 750-502. this day
This directive is installed because data is received from main memory.
When placed, TLTHM flips into another state
is set to binary 1. Directory allocation
The cycle has settled down and the data from memory is
Stored in Katsushie, directory exploration and
The allocation cycle is run again. In other words,
Command operation is interrupted and another TLTHM flipflop
It is restarted via the rope. Hit or miss during the Director exploration cycle.
Before deciding on the ZAC command, ZPSWA switch 75
0-110 and ZPSW switch 750-178
to SIU output registers 750-174 through
(The cutlet device takes a failure condition). During the directory allocation cycle, the
The position 750 controls the state flip-flop CAOPR.
against SIU100 for memory operations under
and make a request. That is, CAOPR flip-flop
forces the AOPR line to binary 1 and requests memory
signal to the SIU 100. At this time, the ZAC directive was
Appropriate notes given to lines MITS and SDTS
along with the Lee identification signal and the steering signal.
available. The memory identification signal is switch 750.
-139 from register 750-106
via registers 750-138 loaded into
Given. The steering signal is used as the source of the request.
Means for specifying the processor 700 (not shown)
It is produced by a known method. Using steering signals
For further details regarding U.S. Patent No.
Please check number 4006466. SIU100 forces the ARA line to binary 1
This will allow you to trust the acceptance of Katsushie Memory's request.
issue. The SIU then descriptored this request.
Main memory from which to retrieve the 4-word block of data 1.
Send against. transfer of the first next data word and
At the same time, SIU100 forces the ARDA line to binary 1.
The even words of this pair are used on the DFS line.
Show that it is possible. SIU100 is also DPFS
Force the line to binary 1 and display double word transfer
do. This makes the QATB flip-flop 2
The base number is switched to 1, but this state is not valid for odd number data.
data word is available on the DFS line.
shows. After that, THCFD flip-flop is 2
Switched to base 1. The first data word is RP register 750-
179. In addition, the rotation by SIU100
The memory identification signal given to line MIFS is RSPB
Loaded into registers 750-124. bit
RZAC buffer 750-10 using 2 and 3
Access the ZAC read command in 2. child
The addresses of Katsushi storage devices 750-700
and directories 750-500 and 750
-502 again. Directory and cutlet storage device 750-
In parallel with the 700 accesses, the first data
The code is loaded into RDO registers 750-180.
It can be done. The second word is RP register 750-17
9 and loaded into RD1 registers 750-180.
is coded. At this time, both words are in the ZAC command.
The cutlet storage device 7 is stored at a location specified by
50-700. Also, the first in-use bit
The reset is performed according to the encoding of signals MIFS1~3.
will be played. SIU100 again connects ARDA and DPFS lines.
The following two data by forcing them to binary 1:
to transfer the data to the cutter device 750.
act. This will cause the OATB flip-flop again
Switch the tup to binary 1, and after this switch it again.
Switching THCFD flip-flop to binary 1
Ching continues. Again, MIFS register 750-1
The signals stored in 24 are
Addressing the storage devices 750-700
Therefore, ZAC from ZAC Batsuhua 750-102
Access instructions. Parallel to this access specification
The next two data words are stored in RP register 7.
RDO and RD1 registers via 50-179
Sent to 750-180. then this word
is written to the cutlet storage devices 750-700,
Completed memorization of the first block of descriptor 1.
This allows the processor 700 to use it. this
Since the command is a prefetch command, the cutlet device 75
0 sends the data word to processor 700.
Use ZDI switch 750-720 to enable transfer.
Do not make it usable. Also, this write operation
In parallel, the cutlet device 700 has a second in-use bin.
The device is reset according to the MIFS signal and continues.
The bit indicates completion of the read ahead operation. It can be seen from the flowcharts in Figures 9 and 10.
As shown in FIG.
Run the file. That is, the FPOP flip-flop is
It is maintained in a state of binary 1, which is a disk
Lipta 1 progresses (DESCO=1) and the previous cycle
is an EPOP cycle, (FPOP=1), and this
This is because the command is an edit command (DEDIT=1).
Ru. RSIR register 7 during the first FPOP cycle
Descriptor 2 loaded into 04-154
(RSIR0~20) Y address value and corresponding signal
are for ZX switch 704-58 and controller respectively.
Indicator register from register bank 704-304
data (X) value or address register (AR) value.
Because of the combination by adders 704-322,
Transferred via ZY switch 704-326
Ru. Changing the index register or address register
Because there is no (MF2=0), lines ZAR0 to 23 and
The value given to lines ZX0-20 is zero. This way
uni, the address value of descriptor 2 is
Selected by the contents of RDESC registers 704-144.
For the TEA1 location of selected bank 704-302
and the line ASFA and adder 704-320.
Transfer to RADO register 704-46 via
be done. As previously described for descriptor 1,
An appropriate base value can be created using the same method as described above.
You can see that it is added to the address of Putter 2.
cormorant. As can be seen from Figures 9 and 10, the process
700 is given to RADO/ZADO line
ZAC command word is address of descriptor 2
Another read ahead command with the value 3000 and a memory read
Generate quad operations. This directive is for Katsushi
750 and processed in the same way as other commands.
It can be done. In other words, the data in descriptor 2 is
Since the read-ahead command is not in descriptor 2,
Load the first block of data into Cutsie
Ru. As you can see from Figure 7, this block
Responses 3000 to 3003 contain word data characters.
Ru. During the cutlet device processing of the prefetch command, the process
The server 700 continues processing. 2nd FPOP cycle
During this period, RTF2 registers 720-46 are RTYP registers.
TA2 field via star 704-160
loaded with the corresponding signal. Again, the value '00' is
The data of descriptor 2 is a 9-bit data statement.
Indicates that it consists of letters. Bank 722-80
The RLN2 register connects the RSIR line to the ZLN switch 7.
22-02 to the N2 field and the corresponding signal.
loaded with the number. This value is descriptor 2
The length of the data field is shown in Figure 7.
6 characters. Furthermore, RCN2 register 720-30
Lines 34-36 and RAD register 720-2
Value ``11'' through 4<sub>2</sub>” is loaded. this thing
is the first data word of descriptor 2.
in the field where the third character is to be processed
Indicates that it is the first character. Also, bank 722
-20 RP1 register for its temporary storage.
Meni "11"<sub>2</sub>” is loaded with a character pointer value. MF3 field bits 0-8 and corresponding signals
The number is from RBIR register 704-152 to R29 register.
registers 704-162 and RRDXA register 70
4-158 and ZIDD switch 704-180
transferred to the FID and FRL flip-flops via
It can be done. A zero value is an address for descriptor 2.
Indicates that no changes are required.
RDESC registers 704-140 are disk scripts.
“10” indicates the operation of data 3 (see logical formula).<sub>2</sub>” value.
forced to remember. Again, the line [RDIBUF/ZIB is the read address]
to increment the counter and indicate the next instruction.
is forced to binary 1. given to line ZIB
The descriptor and corresponding signal are in the RSIR register
and is loaded into the R29 register 704-162.
Also, RBASA registers 704-156 are ZIB lines
Loaded with signals from 0-2. Similarly,
RTYP registers 704-160 are connected via the ZIB line.
is loaded with zero and descriptor 3 data file is loaded with zero.
Indicates that the yield consists of 9-bit characters. Microprogram control during EPOP cycle
Below, the first four ASCII characters are
From location 14(8) of Chipad Memory 714-30
RTRH4 (TR4) register of bank 714-10
will be forwarded to. Also, control flag indicator
For FINDA and FINDC testing, also Blotsu
Bit 2 implemented by circuits of block 701-1
Obtained from RSIR registers 704-754 from 1 to 23.
The known vector established by the TA1 field
A signal is generated for the torque branch operation RB2. child
Testing of indicators is not relevant to the present invention;
Therefore, it will be ignored in the main text. As can be seen from the flowchart in Figure 10,
FFS (control state flip-flop to binary 1)
The FESC cycle starts at the same time as switching. this
The FESC flip-flop operates according to the following logical formula:
set and reset. That is, SET:FESC〔(FPOP・) RESET:FESC=0-5 In this case, the FPOP flip-flop is set.
(FPOP=1), this flip-flop is my
Black program control (logical formula - DPIPE file)
Assuming that there is no operation start specified by
is assumed and therefore not set again (
FESC flip-flop is set for =1)
It can be done. This cycle is a microinstruction word cycle.
A micro program where A=1 field of the file is used.
Grams are under control. During this cycle, the second
4 ASCII characters are scratch padded memory 7
14-30 location 158 to bank 714-10
The data is transferred to the RTRH5 (TR5) register. van
Data stored in RPO register of block 722-20
The character pointer of scripter 1 is the ZPA switch.
722-27 and adder 722-92
Temporary storage register RLN3 in bank 722-80
will be forwarded to. Also, the descriptor stored in the RP1 register
2 character pointer is ZPB switch 722-28 or
and ZRPB switch 722-24.
It is transferred to the RP5 register of 722-22. Also included in the branch circuit of block 701-1.
indicator memory (history) register (see diagram)
) is cleared to zero. Use these registers
for testing during subsequent operating cycles.
Bits 136-139 of the second microinstruction word
Remember the state of input group 1 selected via
do. As can be seen from Figure 10, block 701-1
TA1 tested through vector branch circuit of
A value indicating that the field is a 9-bit data character.
Since "00" is stored, the processor 700
Enter the operation cycle. During this cycle, type
A = microinstruction word with 4 fields
Under control, the data feed of descriptor 1
The character number in one word for the word is banked.
722-60's RXPB register.
As can be seen from Figure 10, this value is a 9-bit character
4 for ZXPB switch 722-7
Adder 72 in response to a constant provided via 0
2-72. Descriptor 1 stored in RLN1 register
The data field length of adder 722-92
is transferred to the RLN4 register via Also, bank
Edit insert stored in TR4 register of 714-10
The signals corresponding to the first four characters of the entry table are:
Bank 7 via ZRESA switch 714-36
20-10 table entry 1 register
is coded. Processor 700 then enters the B3 cycle and enters the B3 cycle.
specified by a microinstruction word having the form
Perform the various operations that will be performed. During this cycle, the
stored in the RLN2 register of links 722-80.
The length of the data field of descriptor 2 and
The corresponding signal is provided to adder 722-92.
Tested for zero. Displaying this result is
With auxiliary flip-flop of Tsuku 701-42
given to the object, and if it is zero, the end flippf
Switching one binary digit of the loop (EXH2) to 1
inducing a ng action. This means that the processor 700
Read descriptor 2 during B7 cycles
prohibited. Stored in TR5 register of bank 714-10
The signal corresponding to the next four characters in the edit insert table
is installed via ZRESA switch 714-36.
720-10 Table Entry 2 Register
loaded into. Also, bits 44 to 46 (PIPE
field), the FPOP flip-flop is
Type switched to binary 1 during operation cycle
6 is encoded to specify restart. obey
Then, the processor 700 processes the descriptor 3.
Hard to start the third FPOP operation cycle
A control switch to wear control occurs. During the FPOP(3) cycle, the second FPOP cycle
read into RSIR registers 750-154 during
Descriptor 3 address bits 0-20
(Y) is adder 7 of ZY switch 704-326
04-322 and ZRESB switch 704-334
ICBA registers in banks 704-302 via
will be forwarded to. Index register or address register
(i.e. MF3 file change is not instructed)
(0), the address value is descriptor 3.
corresponds to the value 5000. The same value (Z base = zero) also
Also, the RADO register 704-4 is connected via the ASFA line.
6 is loaded. As can be seen from Figure 10, the RTF flip-flop
Tsupu 720-52 is detected by detector 720-50.
is set to binary 1, and the data in descriptor 3 is
indicates that the data field consists of 9-bit characters.
vinegar. That is, via RTYP registers 704-160.
TA3 field and corresponding value given by
"00" is decoded by the detector 720-50,
Using this detector, flip-flop 720-5
Switch 2 to binary 1. Furthermore, N3 fee
The signal corresponding to the field is RSIR register 750-1.
54 bit positions 30-35 to ZLN switch 7
RLN1 of bank 722-80 via 22-82
sent to the register. bank 722-70
The RPO register receives all zero data via the ASFA line.
Loaded by scripter 3's character pointer and data
Scripter 3's data field is opened with a number of zeros.
(address 5000). As can be seen from Figure 10, the microprogram
The processor 700 under control is RLN4 for zero
The length of descriptor 1 stored in the register
Test the value. This is the result of adder 722-92.
Output is zero or carry out
The status indicator of block 701-1 indicates whether
To test one of the converter flip-flops
It is done by. Each of the above conditions is terminated.
one of the flops (EXH11) for the next test.
Set it to binary 1 first. Next, the processor 700 processes the format of TYPEA=4.
under the control of a microinstruction word using
Character numbers in Cryptor 1 data word and
Corresponding RXPB register value 4 and data file
Specify character #2 as the starting character in the
RLN3 register value (10)<sub>2</sub>Transferring the difference between B5
Start the cycle. By adder 722-72
The generated difference value 2 is stored in the PXP2 register.
in the first data word of descriptor 1.
number of data characters to be read or processed
shows. The data field length of descriptor 3 is
Read from RLN1 register and ZONED write instruction
Adder 722-92 and ZLN switch
stored in the RLN3 register via 722-82.
Ru. Next, the adder AL=0 indicator is tested
selected about. Then the RDESC register
704-140 and RBASB register 704-14
4 is 2 for reading data of descriptor 1
Set to base zero. The B5 cycle is followed by the B6 operation cycle, which
In a cycle, under microprogram control, the
The processor 700 is a disk from the TEAO register.
The sum of the addresses of the first data word of Liptor 1 and
Corresponding signal (value 1000) and adder 740-320
The basis from the TBASEO register generated by
Transfers the value to the RADO register over the ASFA line.
Ru. The control device 704-1 uses the ZAC command code bit.
Set bits 1 to 4 to code 000 for single readout
Specify directive to force DMEM line to code 1000
to specify a single read operation of the cutlet. By the method described above, processor 700 receives a read instruction.
The command is sent to the cutlet device 750. Figure 7 and
As can be seen from Figure 9, this data was previously stored in main memory.
removed from the storage 800 and stored in the cutlet.
It is something that Therefore, the cutlet device 750 is
One read command is decoded and the directory and cut file are deleted.
When accessing the storage devices 750-700,
The hit/failure detection circuit 750-560 connects the BPSD line.
Force the binary number to 1, which indicates the hit state of the cutlet.
Both control state flip-flops
is not set. The cutlet device 750 is
ZDO switch between subsequent cycles in response 1000
Process the data word via the Tuchi 750-9.
signal to enable transfer to the server 700
Condition OPSW0~2. In this way, Katsushi
The processing before the prefetch command by the device 750 is performed by the processor 750.
The operation of sensor 700 is stopped and the required data
This excludes waiting for a code. This is lost
A win occurs in the case of a single read command where a loss is detected.
It is. Also, the processor 700 has the length of descriptor 1.
The value of (16) to the number of characters in the data word (2)
is subtracted through the AL adder 722-92, and the remaining
The value representing the number of characters in descriptor 1 of
Bank 722-60 via Itsuchi 722-62
stored in the RXPD register. During this operation, also
and the RLN4 value is zero (ALZ = 1, that is, carry out).
), the indicator of block 701-1
One of the flip-flops (EXH11) is binary
It is set to the number 1. Furthermore, under the control of the microprogram, the
The sensor 700 is the RDESC register of the control device 704-1.
register 704-140 and RBASB register 704-
144 to the value “01” (i.e. NXTD file
yield). This is the information of descriptor 2.
Specify read. After B6 cycle, set during B5 cycle.
data via the indicator (ALZ) that is supposed to be
Simultaneously with scripter 3 field length test
followed by B7 cycle. ALZ indicator is set
Since the processor 700 is not
Start the cruise. Previously retrieved from address 1000
Descriptor 1 given to ZDI lines 0-35
The first data word of (operand 1) is
RDI register 70 via switches 704-182
4-164. Also, descriptor
The length of 1 is read from the RLN4 register and ZXPB
via switch 722-70 and adder 722-72.
and stored in the RXPA register. Similarly, day
Is the copy of the length of scripter 3 the RLN1 register?
is read from RLN4 through adder 722-92.
stored in a register. As a result, adder 704-320 generates
sum the contents of the TEA1 and BASE1 registers
The address of descriptor 2 generated by
The data is transferred to RADO register 704-46.
The processor 700 sends the data to the cutlet device 750.
Created to generate another cutlet single read command.
use This directive arises in the manner previously described. death
However, in this case, the ZAC command is
Descriptor 2 (operan
2) Address of data (i.e. address 3002)
Specify. This data is the control word in Figure 8.
(MOP) corresponds to a string of characters. Figure 9?
As you can see, and as mentioned earlier, the cutlet
The position 750 performs one block in response to a previously issued read-ahead command.
Lock operand 2/descriptor 2 data
is taken out before. Therefore, the cutlet device 75
0 decodes a single read command and reads the directory and
accessing the cutlet storage devices 750-700.
circuit 750-560 again connects the BPSD line to 2.
Force the base number to 1 and signal "hit". Then this
The circuit is an operand that feeds the ZDI line in the manner described above.
Read the first data word of code 2. Again, ma
Under the control of the microprogram (NXTD field
), the processor 700 descriptor 1
RDESC and
Load the RBASB register with the value '00'. As can be seen from FIG. 10, the processor 700
A microinstruction word with TYPEA=2 style
Starts the B8 cycle to be executed. This psycho
During the process, the descriptor 1 (operand 1)
The first word of data is in RDI register 704-16.
4 to character device register bank 720-10
OP1 register of , ALU714-2 of execution unit
0, ZRESA switch 71 on ZRESA lines 0 to 35
Transferred to 4-36. Then the value 4 is the character read from the RP5 register
subtracted from the pointer value and read from the RLN2 register.
It is added to the given value. This operation
Itsuchi 722-88 ZINA position and ZALB stage
Appropriate via the last position of Itsuchi 722-90
Implemented by an AL adder 722-92 that receives the value
It can be done. Results obtained depending on ALZ status or disk
Carry out indicating the number of characters remaining in Lipta 2
For subsequent testing of the exit condition using the signal
Indicator flip-flop (EXH2) 1
Set one. In addition, it is given to the ZDI line by the Katsushi device 750.
The beginning of descriptor 2 (operand 2)
words are loaded into RDI registers 704-164.
is coded. 120<sub>8</sub>The constant value of AP adder 722-3
4 and the RP3 record in bank 722-20.
written to the register. This value is the second operand
The data word of descriptor 1 is written.
Scratch pad memory 714-3
Scratchpad address indicating location at 0
corresponds to Given to the ZDI line from the cutlet device 750
The first operand 2 data words are in the RDI register.
704-164. CSO adder
704-322 are read from the TEAO register
The descriptor 1 address is 1 (1 word).
increment the sum and store the sum back in the TEAO register.
let Adders 704-320 also perform this increment.
The base value read from the TBASO register
and the resulting address (1001) is RADO
Loaded into registers 704-46. Figure 7
As can be seen from Figure 8, this address is
Operan with four 9-bit characters as shown
Specify the second word of code 1. Again, the processor 700 sends a message to the cutlet device 750.
to generate another Katsushi single read command for
It acts on In this case, the ZAC directive is
Fetch the second word of 1 (descriptor 1)
Therefore, specify address 1001. cutlet device 75
As a result of the lookahead command sent to 0, this second word
Do also exists in ``Katsushie''. As can be seen from FIG.
Testing and vector branching operations via branch circuits
(i.e., RIDW) registers 722-106.
The exit indicator through the selected flip-flop
Test the condition of EXH11. This indicator
Since the data is not set, the processor 700
Enter B13 operation cycle. During this cycle, the
The first word of Pelland 2 is RDI register 704
-164 to the character device via the execution device 714.
Sent to OP2 register of bank 720-10. Next, the AXP adder 722-72 registers the RXPD register.
Length of current descriptor 1 stored in the storage
RXPB register indicating number of characters per word from value
Subtract the value stored in , and send the result (10) to the ZXP switch.
Stored in RXPD register via 722-62
do. The output of the AXP adder 722-72 is not zero.
(i.e. AXPZ indicator or carry signal)
is not zero), the ending flip-flop
EXH11 maintains the reset state. This rhino
During the cycle, the ZDI is read from the cutter device 750.
The operand given to the line /(address
1001) is the second word of RDI register 704-1
64. Also, constant value 117₈is determined by the AP adder 722-34.
is generated and sent via ZRPB switch 722-24.
and loaded into the RP5 register. This value is
In order to transfer the data of land 2 to character device 720,
Acts as the starting scratchpad address for
do. Finally, under the control of the microprogram,
Processor 700 temporarily stores descriptor 1.
RDESC and
RBASB registers 704-140, 704-14
Load 4. As can be seen from FIG.
Two microinstructions containing cycle B14 and B15
Enter sequence. Operate using this sequence.
In the remaining data characters of land/descriptor 1
Load scratchpad memory 714-30
do. Scratch pad memory 714-3
0 can store up to 63 characters. This space
The length of the string is 16 data characters or 4 words.
This sequence is repeated several times. During the first pass of the B14 cycle, processor 700
is a microinstruction with the style AACU=10
operates from RDI registers 750-164 under the control of
ZRESB switch 71 for the second word of land 1
Scratch pad input RSPB input via 4-38.
Transfer to register. Again, adder 704-322
is from the same register that is returned to the TEAO register.
Increment the read content by 1 (word).
Additionally, adder 704-320 adds the incremented value to
Add to the contents of the TBASEO register and get the result.
address is sent to the RADO register via the ASFA line.
704-46. points to the third data word of operand 1
The address (1002) is generated and sent to the Katsushi device.
Included in another single read command sent to 750
There is. This data word is also used in Katsushi storage.
750-700. As can be seen from FIG. 10, the AP adder 722-
34 increments the contents of the RP5 register by 1 and
120 for scripter 1₈The result address is
RP5 register via ZRPB switch 722-24
to the computer, and also via ZSPA switch 722-100.
Scratchpad address RSPA register 7
22-102 again. micro program
Under RAM control (field NXTD), processor 7
00 is the value “10₂” to RDESC and RBASB cashier
Load to the star 704-140, 704-144
Ru. This value is a temporary register of descriptor 3.
(i.e. TBASEA, ICBA) and
Data word is scratch padded memory 71
It is not used until it is loaded in 4-30. this value
generates yet another address for descriptor 1
Temporary register of descriptor 1 to
(value "00") is in cycle B15. As can be seen from FIG. 10, the processor 700
AP adder output is zero or carry out
Adder indicator to detect if there is no
in the previous cycle by examining the state of
end of the data string of operand 1, i.e.
Test for one round. operand 1 date
Because the data string was not finished, the processor
700 starts the B15 cycle. B15 cycle
During this period, AXP adders 722-72 register RXPD
Is the current length value of descriptor 1 stored in the
statements per word value stored in the RXPB register from
Subtract the number of characters and send the result (6) to ZXP switch 72
2-62 to the RXPD switch. So
I tested the resulting length value and found that this is still
If not zero, the ending flip-flop EXH11 is
Maintain reset state. Next, the cutlet device 750 connects to the ZDO line.
The third word of the given operand 1 is the RDI record.
is loaded into the register 750-164, and then
Addresses stored in RSPA registers 722-102
reply 120₈to be written to the location specified by
RSPB Scratchpad Buffer 714-32
loaded into. Again, the AP adder indicator is
selected for RDESC and RBASB registers.
The star selects the temporary register of descriptor 1.
Therefore, it is set to “00”. Processor 700 returns to cycle B14 and displays
repeating the operation that results in the second group of values.
generate. Next, the processor 700 uses the B15 cycle.
A second group illustrating the operations in the group
yields the value of Then B14 and B15 cycles
Another round of is made to yield a third group of values.
Ru. During the third round of the B14 cycle, processor 7
00 is under the control of the microprogram.
A single read command is issued to the device 750 to turn it on.
Fetch the fifth data word of pelando 1. No.
As can be seen from Figure 8, this word is stored in main memory 8.
It exists in 00 and does not exist in Katsushie. cutlet device 750 in response to a single read command.
is written about the prefetch command from the main memory 800.
Pair addresses 1004-1007 in a similar manner as described.
act to retrieve another block of corresponding data.
Ru. However, in this case the directive is
Since the cutlet device 750 is
Forces the CPSTOP00 line to binary zero. this
sets the IHOLD00 and EHOLD00 signals to binary zero.
Forcibly stops the operation of processor 700. In other words, the contents of all processor registers are changed.
Since processor 700 cannot
Tushie device 750 retrieves the required data word
It stays in the same state until the end. That is, the cutlet device 75
Data word containing word addressed by 0
When receiving a code, this device is under DATARECOV control.
Forces the signal to be a binary 1, and this condition further
Reset the RBPSD state flip-flop and
The flip-flop turns off the processor 700.
state. As a result, the cutlet device 750
Forces the CPSTOP00 line to binary 1 to force the processor
700 to continue its operation. Processor 700 requires the required data
At one point in the processing of an EDIT instruction and at another
Processor operations cannot be performed because operations cannot be performed.
changing the efficiency with which instructions are executed by stopping the
There isn't. Processor 700 can initiate another operation
In case, during the execution of B14 and B15 cycles another
It would be advantageous to allow generation of look-ahead directives.
cormorant. The theory is that the data string of operand 1 is
If it is 16 characters or less, it is under hardware control.
, the generation of a single lookahead directive is entirely necessary.
Ru. During the third round of the B15 cycle, AXP addition
Calculator 722-72 calculates the current data stored in RXPD.
From the length value (2) of descriptor 1 to the RXPB register
Subtract the number of characters per word data stored in
When you pull, the result is negative and you carry out.
does not occur. Therefore, the fourth B14 cycle
Outside resulting in distribution to the B16 cycle following completion,
End flip-flop EXH11 switches to binary 1
available. As can be seen from Figure 10, 3 times of B15 cycle
During the eye pass, the cutlet device 750 is transferred from the main memory.
The fifth data word obtained by
704-164. Also, AXP addition
Negative results produced by devices 722-72 terminate
Set flip-flop EXH11 to binary 1.
let RSPB Buffer Register 714-32
The previously stored fourth data word is
Scratch pad memory 71 with space 1003
Written to location 4-30. AXP adder in
indicator selection and RDESC register 704-
140 and RBASB register 704-144 low
Following deing, the processor 700 is B14 cycle
Begin the last pass of the file. During the last B14 cycle, processor 700
By repeating the operations shown in Figure 10,
Resulting in 4 groups of values. In summary, the process
The 5th data word (1004) is RSPB
load into file register 714-32 and
Increment the latchpad address and add this to RP5 and
and stored in the RPSA register. However, it seems like it's over
Because the flop EXH11 was set before
Therefore, processor 700 processes a small number of microinstruction words.
Another single read specified by the CU field
Prohibit the generation of directives. In other words, all termination conditions are zero.
Give the code to the DMEM line. Next,
Under the control of the microprogram, the processor 700
reads from the temporary register of descriptor 3
Preservation value ``10''<sub>2</sub>' to RDESC and RBASB registers.
Set it on the stand. At the end of the B14 cycle, processor 700
branch into a cycle, and in this cycle, the
The accessor stores the first part of the data string for operand 1.
Scratchpad address after word 123<sub>8</sub>to
Write in the location indicated. after this cycle
The lengths of both operands 1 and 2 are AL and
and AXP adders 722-92 and 722-7
operand 1 or operand tested through 2
A zero number of characters indicating the default condition for both
W8 cycle to ensure that there is no field of
ru continues. This was not the case
Therefore, no default display is generated. The processor 700 is a disk of ICBA registers.
Read the contents of the starting address of the printer 3. Adder 7
04-322 decrements the ICBA address value by 1
and the resulting address is stored in the ICBA register again.
is memorized. The same address will be used
Before the processor cycles through common editing routines
is incremented by 1 during execution. This result address
For ZZ Switch 704-328 and ZDO Switch
Execution unit registers are accessed via channels 704-340.
Transferred to RTRH7 register in bank 714-10.
It will be remembered here. At the end of this cycle,
Processor 700 sends the
bit position of RSIR register 704-154
TA3 values stored in 21 to 33 and corresponding R1DW
Vector branch of contents of registers 722-106
conduct. Processor 700 now opens the C2 operation cycle.
start During this cycle, processor 700
RPO register using AP adder 722-34
Start character point of descriptor 3 read from
The value “0” of the data word is assigned to the data word of operand 3.
Subtract from the constant value 4, which specifies the number of characters. So
The result of 4 is stored in the RP2 register. or,
The character pointer read from the RPO register is RP6
written to a register. Next, the AXP adder input
indicator AXPZ is the operand for subsequent cycles.
selected to test the length of 1. Psych
The state of this indicator as secured in the W8
The status is stored in history register HR4 (not shown).
to enable further testing. As can be seen from FIG. 10, the processor 700
Using TA3 contents of R1DW register 722-106
Perform another vector branch operation and MOP set
D1 cycle to start executing the top operation
(9-bit character). During this cycle,
used in execution unit 714 during the down cycle.
section 704-5 of the RAAU register to
Constant value ``0110'' for selection by₂” That is, 6 is Sui.
To the RRDXB register via Tuchi 704-188
loaded. The contents of the OP2 register start from bank 720-10.
The contents of RCN2 register 720-30 are read.
Therefore, the first MOP character selected is ZCV SWITZ.
RMOP register 720- via chip 720-18.
70 and RIF registers 720-63.
It can be done. In this example, the editing command is marked with *.
produces a zero permutation. In this way, the RMOP register
720-70 memorizes the micro OP code*
Specifies the replacement of the character ``0'' to the left by the mark.
Ru. RIF registers 720-63 are
Operand 1 field where OP code operation occurs
Stores information specifying the length of. In this example
, this character processes one character of three operands.
used for Next, it is stored in the RCN2 register 720-30.
The value α=2 is added to the adder 720-30.
By conditioning the same adder to
– Test your flow. The result is RCN2 Regis
data 720-30. RCN2 Regis
Word 3002 statement with data 720-30 as operand 2
Since character #3 is specified, decoder 720-3
8 forces the CN2OVF output to a binary 1. this
This means that a minimum of 4 words can be stored for processing.
At this time, operand 2 must be
This means that another word is required. this
This can be seen from Figure 7. Next, the text of device register bank 720-10 is
The previously stored edition in the table entry 1 register
Bits 0 to 4 of entry 8 in the collection insertion table are
The RTE8 register is read during the operation cycle of
720-68. Also, this cycle
The display of CN2OVF conditions detected during the
History register (Fig.
(not shown). This CN2OVF indicator
The data is also stored in the microprogram during the next branch operation.
Selected for controlled testing. At the end of the D1 cycle, the length of operand 1 is
Tested via AXP Additive Indicator (ZXPZ)
be done. Since this length is not zero, the processor 70
0 starts cycle D2. of this cycle
During the time, the AL adder 722-92 inputs the RLN2 register.
The length value 6 of operand 2 read from
Decrement and put the resulting value 5 back into the RLN2 register.
Write. Next, the constant value 27 is set to the AP adder 722-3.
4, generated via ZRPB switch 722-2
In addition to being written to the RP7 register via RSC
Shift count and
and is loaded. This is execution unit shifter 7
To prepare for the implementation of shift operations by 14-24
It is. Shifter 714-24 has mutually exclusive contents.
It contains two registers that are shifted into each other.
By shifting the 27 bit positions, the nine most
Equals one data character corresponding to the high bit
You can choose the amount. Then, under microprogram control, the processor
700 is the RDESC and RBASB register 704-
140 and 704-144 as part of descriptor 2.
Set to value “01” for hour register selection.
Ru. At the completion of this cycle, processor 700
Based on the state of the CN2 overflow indicator.
Performs conditional vector branching operations. This inji
Since the controller has been set before, processor 7
00 starts the D3 operation cycle. As can be seen from Figure 10, in the D3 cycle
So, is the adder 704-322 the TEA1 register?
The address of descriptor 2 read from
(1 word) and set the resulting address to
Write to TEA1 register again. Also, the result was
Word address 3003 is then in the RADO register
Adder 704-32 loaded into 704-46
Base read from TBASE1 register by 0
added to the value. Next, the processor 700
The second word of land 2 is needed immediately for processing.
cutlet to take out this word
Generates a single read command. As can be seen from Figure 7
, this word containing letters 1-4 is
The cutlet is written in response to the prefetch command generated by the air.
previously loaded into storage devices 750-700.
Ru. Therefore, operation of processor 700 can continue;
The cutter device 750 extracts the required word.
Act and give this to the ZDO line. During the D3 cycle, corresponds to the length of operand 2
The current value of
Tested for zero by adder 722-92.
It can be done. Since this value is “5”, the AL adder
The indicator ALZ is not set to binary 1. child
, this indicator will be tested during the next cycle.
selected for use. The next cycle is D10 cycle and this cycle
In this case, the AL adder 722-92 is connected to the RLN2 register.
The length value 5 of operand 2 read from the
decrements and checks whether operand 2 has declined.
Strike. Since this value is not zero, output AL addition
device indicator ALZ, i.e. no carry out
Set flip-flop EXH2 to binary 1.
It never happens. Katsushi storage device 750-700
second word of operand 2 read from
(3003) is loaded into RDI register 704-164
be done. Next, adder 704-322 registers TEA1 register.
The address of descriptor 2 read from the
Increment by 4 words. Adders 704-320 are
The value read from TBASE1 is added to the incremented address.
and the resulting address is added to the RADO register.
704-46. However, TEA1
The address value in the register remains unchanged.
Ru. Under the control of the microprogram, the processor
700 is a microinstruction word with format 1.
According to MEM field encoding of small CU field.
Then, a look-ahead command (0110) is generated. Auxiliary device 7
For more complete control of 22, use Form 1.
use. However, this look-ahead command also applies to Figure 6b.
also by a microinstruction having a different format as shown in
It will be seen that it can be generated. This look-ahead directive
is the following 4 word block (address 3004 ~
3007). ZAC command points to address 3007
In order to
800, the cutlet device 750:
block the data containing the specified word.
Read out the lock. As mentioned above, the cutter device 750
Processes read-ahead commands generated under program control.
During the process, processor 700 continues executing the editing instructions.
can be done. That is, the cutlet device 750
Keep the CPSTOP00 line in binary 1 state.
This further speeds up the execution of editing commands.
It is. As can be seen from FIG. 10, the processor 700
Conditions based on the state of AL adder indicator ALZ
Execute a vector branch with length of operand 2
Since the value was not zero, processor 700 operated D11.
Start the production cycle. in this cycle
is the value stored in RDI registers 704-164.
The second word of Pelland 2 (address in Figure 7)
3003) is the execution unit on the ZRESA line
Bank 720-10 via ALU714-20
is written to the OP2 register of At the end of the D11 cycle, processor 700:
TA3 stored in RIDW registers 722-106
Performs a conditional vector branching operation based on values.
Ru. This result indicates that character device 720 is in the first MOP
Editing operations of the type specified by the sign of the control character.
Processor 700 executes the E1 operation cycle to execute the operation.
is to start. During this E1 cycle, the format AACU=3
AXP addition under the control of a microinstruction word with
Arithmetic unit 722-72 reads from RXPA register
Decrement the length value of operand 1 by 1 and
The resulting value (15) is written back to the RXPA register.
It can be done. Similarly, AL adder 722-92 is RLN1
The length value of operand 3 read from the register
Decrement by 1 and the resulting value (16) is also RLN1 level.
written to the register again. Also, AP adder 722
-34 is the complement of the CN3 value read from the RP2 register.
Decrement the number by 1, and the result (3) is again RP2 level.
written to the register. Under hardware control, RCN1 register 72
The contents of 0-38 are converted to values via adders 720-34.
Updated by α=2 (010) and the next 9-bit statement
Show character selection. Only the upper 2 bits are used
The remaining bits are ignored. This way
It can be seen that the increment value=1. RCN2 cash register
The contents of register 720-30 are stored in RIF register 720.
-0 state until the value stored in 63 is decremented to zero
maintain. As can be seen from Figure 10, the RIF register 720
-63 by the first MOP control character stored in
The number (3) indicating the remaining characters to be processed is sent to circuit 720-
60 and is decremented by 1 and returned to the register.
be done. Decoders 720-74 decode MOP control characters
and controls the operation of the character device 720.
Generate a signal to During operation, first character
is read from the OP1 register, which is detected by detector 7.
When zero as signaled by 20-82, the
table entry 1 register for link 720-20
The * symbol character read from the second character position of the
will be replaced. The first data character can be determined from Figure 8.
Since it is zero as shown in
Selected via the switch 720-20 and the switch
RAAU register 722- via 722-44
46. Also, under the control of the microprogram, the process
The server 700 displays the MOP indicator for subsequent branching operations.
depending on the status of the digitizer MOPIA and MOPIB.
Set RVBO and RVBZ registers.
The MOPIA indicator signals processor 700
to continue executing the MOP run cycle and then
Process MOP control characters and use the same MOP characters
Decide whether further processing should be done.
The MOPIB indicator is used to complete the welding process.
signal to sensor 700. In addition, some historical records
register (not shown) HRO, 1 and 3 are
Control indicator CN1OVF for testing,
Set according to the state of CN2OVF and END.
Ru. As can be seen from FIG. 10, the processor 700
Starts the E2 operation cycle, during which the RAAU register
The * marked contents of data 722-46 are section 704-
ZEB times via ZXB2 switch 704-59 of 5
given to the line. From here on, *marked characters are ZOPB slots.
Shifter 714-2 via Ituchi 714-17
4 and the contents of the TRO register are
Tsuchi 714-15 and Switch 714-28
given through. Shifter 714-24 is
3 under control of shift count from position 722
Shifts the signal by 27 bit positions. Figure 8
The shifted value corresponding to the first character of operand 3
The result is then ZRESBO switch 714-3
8 into the TRO register. At the end of the E2 cycle, processor 700
Control indicator MOPIA by torque branch operation
Test the condition of. Since the MOPIA value is 00,
Therefore, processor 700 performs an F1 operation cycle followed by an F2 operation cycle.
Start the cycle. During the F1 cycle, the process
The server 700 was executed during the previous E1 operation cycle.
Perform the same operation as the one you just created. As a result,
yields a group of values. That is, RXPA,
RLN1 and RP2 registers have values 14 and 14 respectively
and 2. Also, during the F1 cycle, under hardware control
The character device adder is the RCN1 register 720-
28 by 1, thus for subsequent tests.
The CN1OVF condition is set to history register HRO (see diagram).
) will be memorized. This is operand 1
The second word is scratch padded memory 71
4-30 and stored in the OP1 register.
Indicates that it is necessary to RCN2 register
720-30 maintains zero state and RIF register
stores the value "1" after being decremented by one. Re
and *marked characters are displayed via ZOC switch 720-20.
The zero data statement of the second operand 1 is selected by
Set the character. Vector branch register RVB0 and
and RVB2 according to MOPIB and MOPIA respectively
is set. RVB0 register is set to 010
signaled to test the CN1OVF condition.
The RVB2 register is set to the value 10 and the next operation
MOPIB indicator tested during the cycle
show what should be done. During the F2 cycle, the second * character will appear on the RAAU record.
From register 722-46 to ZXB2 switch 704-
59 to the ZEB line. TRO again
The contents of the register and the * mark character are shifter 714
-24, given as input, 27 bit position
is shifted and the result is written to the TRO register.
be included. This result corresponds to the operand shown in Figure 8.
corresponds to the first two characters of command 3. F2 cycle
At the end of the MOPIA indicator makes a conditional branch
Tested through operation, processor 700 is F4
Start the cycle. Under microprogram control during F4 cycle
The processor 700 performs various functions for subsequent branching operations.
Set up the state of the indicator.
L1 underflow, L3 underflow and
Display regarding CN3 overflow is AXP, AL
and RXPA, RLN1 and AP adder
Reading from the contents of the RP2 register and reading from the history record
Additions in registers HR4, 5 and 7 (not shown)
Calculator output zero indicator (AXP, ALZ and
APZ) state memory.
AXPZ and ALZ indicators are selected,
RVB2 register is R1DW register 722-106
It is set by the contents of TA3. At the end of the F4 cycle, processor 700
Vector branching based on MOPIB indicator state
Perform the operation and enter the J1 cycle. this cycle
CN1OVF storage register (HRO) is
selected for strike. end of this cycle
, processor 700 selects the previously selected adder input.
Executes branching based on the state of indicators AXPZ and ALZ.
give Both operands 1 and 3 are not zero.
Therefore, processor 700 enters the J7 cycle. During this J7 cycle, microprogram control
The processor 700 reads from the RP3 register under
Scratchpad applied to operand 1
RSPA address via AP adder 722-34
Load into register 722-102. processor
700 also displays the END indicator for subsequent tests.
data storage register HR3 (not shown). J7
At the end of the cycle, processor 700
Perform branching based on the memorized state of the indicator.
give This indicator has been set previously.
Therefore, the processor enters the P1 cycle. During this P1 cycle, address 1001 is
The second word of memorized operand 1 is Scrats
Address 120 of chipped memory 714-30₈
is read from bank 72 via the ZRESA line.
Loaded into OP1 registers 0-10. Figure 9
As you can see, this word contains data characters 4060
Contains, in which editing the first character is the first
This is done under the control of the MOP character, but the following three characters
Editing is done under the control of the following MOP control characters in Figure 8.
be exposed. Also, during the P1 cycle, the scrubber of operand 1
Tipped address value is read from RP3 register
is incremented by 1 by AP adder 722-34.
and the resulting address 121₈is ZRPC Suites
Write again to RP3 register via chip 722-32.
be caught. Processor 700 is also used for further testing.
Select history register HR7, this is CN3OVF state
memorize the situation. At the end of the P1 cycle, processor 700
branches based on testing the state of the END indicator
Perform operations. This indicator is set
Therefore, processor 700 enters P2 cycle.
Ru. is stored in the RXPA register during this cycle.
The length of operand 1 is determined due to the detection of omitted conditions.
Tes on zero via AXP adders 722-72.
be struck. Shift settings stored in RP7 register
The number 27 is the shifter 714 during subsequent operating cycles.
-24 RSC register 722-40 for control
loaded into. At the end of the P2 cycle, processor 700
The state of the CN3OVF condition previously selected for
Performs conditional vector branching operations based on
Ru. CN3 overflow condition not detected
Therefore, processor 700 continues another E2 cycle.
Another MOP execution sequence starting with E1 cycle:
Start. During the E1 cycle, the processor 700
RXPA, RLN1 and RP2 registers as shown in the figure
are set to the values 13, 13, and 1, respectively. Har again
Under software control, RCN1 register 720-28
is incremented to the value 01 and the RCN2 register 720-34
remains the same value and is stored in RIF register 720-63.
The stored value is decremented to zero. RIF register
Decrementing the contents to zero takes the value 01 for MOPIA.
Load into RVB2 register. This makes the pro
to the OP2 register during the D11 cycle.
Opera at previously written address 3003
2 characters and the corresponding character to the next MOP control.
and read it out. Since no zero character was detected, the value "4" was set.
The data character with RAAU register 722-4
6 to load ZOC switch 720-20
selected via. Again, MOPIA, MOPIB
and the state of the END indicator.
Specified by the contents of RMOP registers 720-70
The results of the micro-operations performed are
History register for later testing during operation cycle
stored in data registers HR0, 1 and 3. During the second E2 cycle, the data character "4"
To ZEB line via ZXBZ switch 704-58
Given. Given to shifter 714-24
Data characters read from the TRO register and
The contents are shifted left by 27 bit positions and
The result is written back to the TRO register. this
, this register contains the value **4, and the RP2 register
The data contains the value 1. This means that one or more opera
1 data character can be processed and stored in the TRO register.
Indicates that it can be stored. At the end of the E2 cycle, processor 700
Another vector based on the state of the MOPIA indicator
Perform branch operations. This value is "01"
Therefore, the processor 700 starts the F3 cycle at this time.
do. During this cycle, A1 adder 722-9
2 tests the value 5 stored in the RLN2 register
The remaining operand 2 statement for detecting omitted conditions
Indicates the number of characters (L2). Also, AXP adder 722-2
2 is stored in the RXPA register and becomes operand 1.
Number of remaining characters, i.e. descriptor 1 data fee
Test the value 13, which indicates the field (L1). This Tess
The result is that processor 700 will
Which AXPZ indicator state to choose for testing
It is indicated by the state. Stored in R1DW register 722-106
After loading the TA3 value into the RVB2 register, the process
The server 700 performs another vector branch to generate another D1
Begin the operation cycle. Processor 700 is described above.
In order to perform the same operations as in
We will discuss only those results with respect to the previously mentioned cycle.
Ru. In this cycle, it is stored at address 3003.
character #0 of descriptor 2 word is ZCV
Selected by switch 720-18, this
RMOP register when the code is read from DP2 register.
registers 720-70 and RIF registers 720-63.
loaded. Also, RCN2 register 720-30
The value stored in is “00₂” to “01₂”
as the next MOP control character to be read
Display character #1 in the OP2 register. During the D2 cycle, processor 700 processes
There are four more operands to be written, two MOP control characters.
Set the contents of the RLN2 register to 1 to indicate that
Decrement by one. As can be seen from Figure 10, CN2
Since there is no overflow condition, processor 700
starts another E1 cycle. of this cycle
L1 stored in RXPA and RLN1 registers during
and the value for L3 is decremented to 12. Also, RP2
The value stored in the register is decremented to zero,
The TRO register is now operand 3 data file.
A complete 4 to be written in the first position of the yield
Memorize letter words. Under hardware control, the RCN1 register
The value stored in is “10₂” is incremented to the data statement
The character “6” is the next to be selected from the OP1 register.
Indicates that it is a character. RCN2 register 720-
30 stops at "01" and indicates the next MOP control character
However, the contents of the RIF register are decremented from value 3 to value 2.
It can be done. This means that the two operand one data statement
character is processed by the currently stored MOP control character.
Indicate what should be managed. Since the selected data character is zero, the control logic
The logic circuit 720-76 is the ZOC switch 720-2
0 is loaded into RAAU register 722-46.
conditioned to select a different * symbol
be given As a result, the address 1001 in Figure 8 is
resulting in the replacement of character #1 with one * mark. Since the value stored in the RP2 register is zero,
Processor 700 supports MOPIA and MOPIB indicators.
value “01”₂”. next E2 cycle
During this time, the *marked character is loaded into the TRO register.
Ru. At this time, the TRO register stores the value **4*
do. In the method described above, processor 700
Based on the status of MOPIA and MOPIB indicators
Start the second F4 cycle. this cycle
The contents of the RP2 register are tested for zero during
and history register HR7 meets the CN3OVF condition (RP2=
0) is set to indicate the occurrence of 0). Next, the professional
The sensor 700 stores the CN1OVF indicator.
(HRO) will be tested in subsequent cycles.
starts the second J1 cycle selected for
Ru. Processor 700 includes RDESC and RBASA
Jista 704-140, 704-144 is a deis
Value 10 for selection of Cryptor 3 temporary register₂to
It will be set again. Starting the second J7 cycle
Ru. Since there was no CN1 overflow condition, the
Sensor 700 begins the first J8 cycle. this
During the cycle, the data read from the ICBA register
Iscriptor 3 address (4777) is adder 704
-322 by 1 (word) and then
The result (5000) is written back to the ICBA register
Ru. Stored in IBASEA register address 5000
The base values obtained are addressed by adders 704-320.
address 5000 and the resulting address 5000 is
Loaded into RADO registers 704-46. P
The processor 700 is under the control of the microprogram.
Generates a single-write zoning directive. In particular, professional
Sesa 700 forces bits 5-8 to the value 1111,
Writes to address 5000 in response to this write command.
Display the bytes of the word to be written. Also, Mike
Under the control of the program, processor 700
Force command bits 1-4 to code 1000 and ZAC
Indicates that the directive is of single-write zoning type.
Show. The ZAC directive is processed by cutlet device 7.
Sent to 50. Furthermore, the processor 700 also processes a MEMADR file.
Forces DMEM line to code 1100 under control of
This is a single write to the cutlet device 750.
signal that a read operation should be performed. Furthermore, this
The processor forces the DREQCAC line to binary 1.
This command is then signaled to the cutter device 750. P
The processor 700 is connected to the AL adder 722-92.
The length of operand 3 stored in the RLN3 register
Decrement the value by 4 and use the resulting value "12" as RLN3
Write to register again. Next, the processor 700
is stored in RIDW register 722-106.
Perform a vector branch operation based on the value of the TA3 field.
and start the first Q1 cycle. During the Q1 cycle, descriptor 3 (**4
*) is the first data word in the TRO register?
read from ALU714-20 and ZRESB times.
Load into RADO register 704-46 via line
be done. Next, AP adder 722-34 adds TR4
Count of next 4 characters to be written to register
Load the value 4 into the RP2 register used for
do. The RP6 register is loaded with zero as described above.
Ru. At the end of the Q1 cycle, processor 700
Minutes based on memorized END indicator state
carry out the This indicator is not set.
, the processor 700 registers the RIDW register.
In the TA3 field stored in 722-106
Return to E1 cycle by vector branch operation based on
Ru. During the processing of the read command, the cutlet device 750
Processing single write commands similar to the method used
Ru. In particular, the DREQCAC line is set to binary 1.
In response to J8, the cutlet device 750
The RADO register is set by processor 700 during the cycle.
ZAC command word sent to star 704-46
Locator at the first location of WZAC Batsuhua 750-100
code. Write address counter 750-1
The contents of 04 are incremented by one. TRO register
RADO register during Q1 cycle.
The data word loaded into 704-46 is
Write to the second location of WZAC Batsuhua 750-100.
be included. Create the directory and Katsushi storage using the method described above.
Locations 750-700 are given via RADO line.
accessed by a signal. Contains address 5000
Assuming that the block does not exist in the cutlet,
Hit/failure detector circuits 750-560 are BPSD
Do not force the line to binary 1s. Single read command by decoder 750-166
UGCOGTH and CAOPR control while decoding
State flip-flop switches to binary 1 state
It will be done. UGCOGTH flip-flop set
When the block containing the processor data word is
When Lock exists in Katsushie, this word is
To be written to the storage device 750-700
is allowed. CAOPR flip-flops are set
Forces the AOPR line into a binary 1 state when
do. At this time, the first ZAC command word is the ZIU output
Loaded into registers 750-174. Furthermore, cutlet device 750 is available from SIU100.
As soon as a binary 1 signal is received on the ARA line
, the UGCOGTH control state flip-flop is set to 2.
Switch to base 1. The cutlet device 750 has the following functions.
exists on the DIS line until the clock pulse occurs.
Loads a data word into a readable SIU output register.
Complete this operation by typing Since the cutlet command was a write command, the program
The sensor 700 completes the transfer of the data portion of this command.
The execution of editing commands can continue after the
Ru. As can be seen from FIG. 10, the processor 700
Begin the fourth E1 cycle. This results in device 7
22 sets the RXPA, RLN1 and RP2 registers to it.
Set to values of 11, 11 and 3 respectively. or,
RCN1 register 720-28 has value 11₂set to
The RCN2 register 720-30 has the value 01.₂to se
Maintain the current state. RIF register 720-63
stores the value 1 following the subtraction. o with value 6
Peland 1 data character #2 is in the OP2 register.
RAAU register 722-4 at the same time as reading the contents.
To ZOC switch 720-20 to transfer to 6
selected from. During the fourth E2 cycle, the ZEB line is given
The selected data characters are shifted by shifter 714-24.
As a result, “6” is shifted by the TRO register.
written to the register again. Processor 700 is the fourth
branches to start an F1 cycle, followed by
and start F4, J1, J7 and P1 cycles. During the F1 cycle, the registers are set as follows:
will be played. That is, RXPA=10, RLN1=10, RP2
=10, RCN1=00・RCN2=01 and RIF=0.
CN1 overflow event caused by RCN1 = 0
The status of the indicator is determined by the history register HRO (see diagram).
). END event caused by RIF=0
The status of the indicator is recorded in history register HR3 (not shown).
). Also, the data statement of operand 1 with the value "0"
Character #3 is read simultaneously with the contents of the OP2 register.
To transfer to RAAU register 722-46
Selected by ZOC switch 720-20.
The character ``0'' occurs to the right of a non-zero data character.
Therefore, the * mark character is replaced with the “0” data character.
It won't happen. During the F2 cycle, the character “0” is in the TRO register
The content of the result is "60". J7
In the cycle, the scratchpad address
value 121<sub>8</sub>is loaded into RSPA register 722-102.
descriptor at address 1002
The third word of 1 is scratched during cycle P1.
Addressing of padded memory 714-30
(121<sub>8</sub>) is loaded into the OP1 register from
Ru. Also, during the P1 cycle, the scratchpad
The address is incremented by 1 and the resulting address
122<sub>8</sub>is written to the RP3 register again. As can be seen from Figure 10, the END indicator
was not set during the previous cycle, so
Rosesa 700 begins its first P4 cycle.
Branch out. In this cycle, the processor
700 is an option for zero to detect omitted conditions.
Test the length of Pellend 2 (L2). This service
For the rest of the cycle, the operation is the same as in cycle P2.
The same operation is performed. Next, processor 700 performs another
Start a D1 cycle, which includes D2, E1, E2,
Followed by F1, F2, F4, J7, J8 and Q1. In short, during the D1 cycle, the next MOP statement
characters (characters #1 to 3003) are RMOP and RIF registers
The RCN2 register has a value of 10.<sub>2</sub>increment up to
be done. During the D2 cycle, processor 700 is turned off.
Test for the end of the Pelland 2 field,
Decrement the RLN2 register to the value 3. to cycle E1
In this case, the registers are set to the following values:
That is, RXPA, RLN1=1, RP2=1, RCN1=
01<sub>2</sub>, RCN2=10<sub>2</sub>, and RIF=2. Also, set the value 1 to
Data character #0 of operand 1 with is RAAU
Selected to be loaded into a register. During the E2 cycle, the data character now has a value
Written to the TRO register which stores "601".
In the F1 cycle, the above registers are as follows:
It is set as follows. That is, RXPA, RLN1=
8, RP2=0, RCN1=10<sub>2</sub>, RCN2=10<sub>2</sub>and
RIF=1. Also, operand 1 data with value 2
Character #1 to load into RAAU register
selected. During the F2 cycle, the data character is
TRO register with complete word "6012" when
written to. Therefore, during cycle J7, RDESC and
The RBASB register is a temporary register for descriptor 3.
Set to the value ``10'' for star selection. J8sa
During the cycle, processor 700 uses address 5001 as
Loads ICBA and RADO registers.
Ru. Another single write zoning directive is generated and
It is sent to the tsushier device 750. Also RLN3 register
The contents are decremented to the value 8. During the Q1 cycle, the
The second word F3 of descriptor 3 and the corresponding descriptor
The data word is sent to the cutlet device 750.
Loaded into RADO register. As a result, the ad
The value 6012 is written to the location with the response 5001. After the Q1 cycle, E1, E2, F3, D1 and
and D2 cycle continues. In summary, the E1 cycle
During this time, different registers are set to the following values:
Ru. i.e. RXPA, RLN1=7, RP=2, RCN1
=11₂, RCN2=10₂and RIF=0. Also, value
Operand 1 data word #2 with '0'
is selected to be loaded into the RAAU register.
It can be done. During the E2 cycle, this data character is TRO
written to a register. During the F3 cycle, L1
and L2 indicator tests for value “0”
be done. The next MOP character (character #2 to 3003) is D1 cycle
loaded into the RMOP and RIF registers during the
Ru. Also, the RCN2 register has a value of 11.₂is incremented to
In cycle D2, the RLN2 register has a value of 2.
will be decremented. After D2 cycle, E1, E2, F4,
Followed by J1, J7 and P1 cycles. During the E1 cycle, the registers are set to the following values:
will be played. That is, RXPA, RLN1=6, RP2=
2, RCN1=00₂(Signal CN1OVF condition) RCN2=
11₂, and RIF=2. Also, data with a value of zero
in the RAAU register instead of character #3 (1002)
Since it will be loaded, the * mark character will be selected. E2 sa
During the cycle, this * mark character will have the value "0〓" at this time.
Written to the TRO register to store. Operand 1 with value 1357 during P1 cycle
The next data word is a scratchpad memo.
Lee 714-30 location 122₈to the OP1 register
Read. Also, the scratchpad address is
incremented by 1, resulting in 123₈is in the RP3 register
written again. After P1 cycle, E1, E2, F1, F2,
Followed by F4, J1, J7, J8, Q1 and Q2 cycles.
During the E1 cycle, the registers are set as follows:
will be played. That is, RXPA, RLN1=5, RP2=
1, RCN1=01₂, RCN2=11₂, and RIF=1.
Also, data character #0 of operand 1 with value 1
(1003) is selected because it is loaded into the RAAU register.
selected. During the E2 cycle, this character is
Written to the TRO register that stores the value “0〓”
Ru. During the F3 cycle, the register has the following value:
is set. That is, RXPA, RLN1=4, RP2
=0, RCN1=10₂, RCN2=11₂, and RIF=0
(signaling that it ended with a MOP character). It also has the value 3.
data character #1 is loaded into the RAAU character
Selected for Additionally, the status of the indicator
is stored in history register HR3. F2 cycle
During this time, this data character contains the value “0〓13”.
written to the TRO register. During the J7 cycle, RDESC and RBASB registers
The descriptor is set to ``10'' and the descriptor is set to ``10''.
Select register. In cycle J8,
Address 5002 of scripter 3 is ICBA register
and loaded into the RADO register. At this time,
The processor 700 runs the cutter device 750 to
The third word of the scripter 3 is stored in the main memory 80.
Another single write zoning directive to write to 0
Generate a command. Also, the RLN3 register stores the value 4.
is decremented to During the Q1 cycle, the TRO
The contents of the register are transferred to the Katsushi device 750.
loaded into the RADO register. Also, RP2 cash register
The star is loaded again with the value 4. in Q2 cycle
The length of operand 2 (L2) is tested. After Q2 cycle, D1, D2, D3, D10,
D11, E1, E2, F1, F2, F4, J1, J7 and P1
The cycle continues. During the D1 cycle, the following
MOP control character #3 (3003) is RMOP and RIF
Loaded into registers 720-70, 720-63
It can be done. Also, RCN2 register 720-30 has a value
Incremented to '00', this is the CN2OVE indicator
is set to binary 1. In cycle D2, the RLN2 register has a value of 1.
and RDESC and RBASB registers 70
4-140 and 704-144 set to value 01
is selected and selects the temporary register of descriptor 2.
Ru. During cycle D3, processor 700
3004 to TEA1 register and RADO register 7
Load on 04-46. Again, microprogram
Under RAM control, processor 700 at address 3004
A single read command is executed to retrieve a data word.
It is generated for the Tsushier device 750. The block of 4 words including the word is the cutting destination.
The cutting device 750 responds to the reading command.
Because of this, the cutlet device 750 is operated directly.
Binary BPSD line upon completion of reprobing cycle
Force it to 1 and show "hit". Therefore,
The CPSTOP00 line maintains the binary 1 state and
Enables processor 700 to continue processing edit instructions.
Ru. Stored in RLN2 register during D10 cycle.
value is decremented by 4, resulting in a value of -2.
Ru. This is a carry out no indicator
Force EXH2 indicator to binary 1
Switch to 1. ZDI times by cutlet device 750
Address 3004 containing the value "90" given to the line
The data word to be entered is RDI register 704-1.
64. Processor 700 is a disk
Increment the address of Lipta 2 by 4 (words),
The resulting address 3008 is stored in the RADO register 704.
-46. Next word block (A
Separate cutlet to specify readout of dresses 3008 to 3011)
The prefetch command is under the control of the microprogram.
Generated by processor 700. From the above, by using the lookahead directive,
The processor 700 stores the data of the required operands.
always in advance in the cutlet storage device 750-700.
Can be used in the processor 700 as needed.
To perform editing operations more quickly so as to enable
You will find that it is possible. In this way, the professional
The processor 700 is capable of continuing uninterrupted processing operations.
It is possible to do this. During the D11 cycle, the cutter device 750
The retrieved data word is stored in RDI register 70.
4-164 to the OP2 register of character device 720
be transferred. In the next E1 cycle, the register
The data is set as follows. That is, RXPA,
RLN1=3, RP2=3, RCN1=11₂, RCN2=
00₂, and RIF=2. Also, the value “5” is
Data character #2 of pelando 1 is in RAAU register
622-46. rhinoceros
In Cruise E2, this data character is the TRO register.
shifted and written to the star. The above register goes down by executing the F1 cycle.
This results in the value being set to the value shown below. That is,
RXPA, RLN1=2, RP2=2, RCN1=00₂
(Signal CNIOVF condition), RCN2=00₂, and RIF
=1. Also, the data of operand 1 with the value "7"
character #3 is transferred to RAAU register 722-46.
selected to be sent. Cycle F2 smell
, the data character is written to the TRO register.
Ru. Finally, in the P1 cycle, the data character
Operation at address 1004 in Figure 8 containing “90”
Land 1's data word is at address 123₈have
OP1 is read from the scratchpad location
loaded into a register. After the P1 cycle there is another series of E1, E2,
Followed by F3, D1, D2, E1, E2 and F4 cycles
ing. At the completion of the E1 cycle, the register
contains the following values: i.e. RXPA, RLN1
=1, RP2=1, RCN1=01₂, RCN2=00₂, and
and RIF=0 (a new MOP character is required)
signal). During the E1 cycle, it has the value "9".
Data word #0 (address) of operand 1
1004) sends to RAAU register 722-46.
selected for. In cycle E2, the data
The TRO register whose data character now stores the value “579”
written to the star. During the D1 cycle, the next MOP control character in Figure 8
are RMOP and RIF registers 720-70, 72
0-63. Also, RCN2 register 7
20-30 is the value “01₂” is incremented. D2 Psych
During the process, the RLN2 register is decremented to the value 0. child
This means that the operand 2 string has declined.
(L2=0). In cycle E1, the end of operand 1
characters (characters at address 1004 in Figure 8)
#1) is processed by character device 720. child
The character is stored in RMOP register 7 in cycle D1.
Control of MOP control characters loaded into 20-70
Its zero value because it is the first character processed under
is detected and the * mark character is RAAU register 722-
46. cycle
At the completion of E1, the register values are as follows:
Become. That is, RXPA, RLN1=0, RP2=0,
RCN1=10₂, RCN2=01₂, and RIF=0
(The MOP character is encoded to specify the processing of character 1.
). In cycle E2, the character marked * is at this point.
TRO register containing the complete word (i.e. “5790”)
written to the star. In cycle F4, addition
The calculator is in RXPA, RLN1 and RP2 registers.
When testing the value of AXPZ, ALZ and
and setting the APZ indicator to binary 1
It becomes gu. The status of these indicators is
Recorded in registers HR4, HR5 and HR7 (not shown)
be remembered. Also, the zero value in the RP2 register is RP5
stored in a register. Next, processor 700 displays the CNIOVF indicator.
status (HRO) of the data in subsequent cycles.
Execute the J1 cycle selected for the test. JI
At the end of the cycle, the AXPZ and AL indicators
The state of the data is tested. both are set
In order to
To do so. In cycle J2, processor 700
ALZ indicator for testing in the cycle of
(HR5) to start cycle J3. No.
As can be seen from Figure 10, the temporary register for operand 3
Value 10 for star selection₂is RDESC and RBASB
Load into registers 704-140, 704-144
is coded. Also, if the END indicator is
selected for testing during the cruise. At the end of the J3 cycle, processor 700
Conditional vector minutes based on the state of the indicator
Perform branch operations. This indicator is set
Because the processor 700 did not register the R1DW register, the
Cycle based on TA3 content of Star 722-106
Branch to Q7. During cycle Q7, processor 7
00 is the disk read from the ICBA register
Increment the address of Lipta 3 by 1 (word)
Ru. The resulting address 5003 is placed in the ICBA register.
written again. Also, this address is the adder 70
Added to TBASEA address by 4-320
and the resulting address (5003) is stored in the RADO register.
704-46. As can be seen from FIG.
The last single write zone sent to the Tsusier device 750
generates a turn command. At this time, the processor 700
sets the EXH3 indicator to binary 1.
Additionally, the AP adder 722-34 receives the constant value 36 from
RSC register from the value (0) stored in the RP5 register of
Subtract the result loaded in register 722-40
This generates a shift count value. Next, processor 700 begins the Q8 cycle.
In this case, the contents of the TRO register are
Shift by 36 bit positions via -714-24
be done. The resulting data work with value 579〓
The code has address 5003 as shown in Figure 8.
to RADO register 704-46 to write to location.
loaded. As can be seen from Figure 10, the process
The server 700 begins cycle Q9, in which
The processor has a second mode shown in Figure 6b.
instruction pipeline in response to a microinstruction word
restart. More specifically, the microinstruction word
The PIPE field specifies type 1 restart.
It is encoded. At the same time as the decryption, the process
The sensor 700 [sets the END signal to binary 1,
This starts the beginning of the next instruction. As can be seen from the previous description, the structure of the present invention is
of various instructions to be executed by the data processor.
This can speed up execution. the fruit
Look-ahead instructions for types of instructions that can facilitate rows
to have a processor execution sequence containing instructions.
The overall efficiency of the processor is thus increased. The subject of the invention is a microprogramming of certain instructions.
is not intended for any particular method of
You will understand. Rather, a microprogrammer
This should be encoded to include a lookahead directive.
Since the equicycle can be freely selected,
Ru. According to the teachings of the present invention, the data
Preliminary calls to the Tsusier device can be made, but the process
If the server performs an operation that does not require immediate use of the data.
The read cycle should include a look-ahead directive.
Ru. For example, as illustrated, this
generates an address or performs an editing or translation operation
It is possible if Thus, the teaching of the present invention
According to the contents, the address of a certain descriptor
and create addresses for other descriptors.
Multiple word instructions that proceed in parallel when generating
In the early part of the instruction, the look-ahead instruction is
It is generated under the control of the operator. There are many details about the system of the preferred embodiment.
Obviously, modifications are possible. Do not include statements regarding matters within the knowledge of a person skilled in the art.
To avoid overcomplicating the process, we will explain it using a block diagram.
A detailed functional explanation is given for each of the circuits, and the circuit is
The identification was carried out qualitatively. Each reader has their own background.
Fritz and standard literature available
Components such as flop circuits and shift registers
You are free to choose. Also, accurate encoding for all microinstructions
Although the pattern was not presented in the main text, this
To be able to change its form freely
It is understood that this is because of the This encoding
technical details and further information regarding this system.
For more information on the above, please refer to Chu's ``Computer Setup''.
Fundamentals of Metering” (Mc Graw-Hill Book Co.,
Inc. 1962 edition) and S.S. Husson, Microprop.
"Programming, its principles and applications" (Prentice-
Hall, Inc. (1970 edition). The best form of the present invention in light of current regulations
Although the patent claims in the header were illustrated and explained,
without departing from the gist of the invention as stated in the scope.
Changes to this system are possible and may be subject to change.
Therefore, only some of the features of the present invention may be explained without corresponding to others.
It can also be used advantageously.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system implementing the principles of the present invention, and FIG. 2 is a block diagram of the upper processor 700 of FIG.
Block diagram of Katsushi Memory 750, No. 3
Figures a through 3i are block diagrams showing the block diagram of Figure 2 in more detail, Figure 4 is a more detailed block diagram of the cashier memory 750 of Figure 2i, and Figures 5a through 5e are block diagrams showing the block diagram of Figure 2 in more detail. FIG. 6a is a diagram showing the form of the control storage device of FIG. 1; FIG. 6b is a diagram showing the configuration of the execution control storage device of FIGS. FIG. 7 is a diagram showing the format and symbols of editing commands used in explaining the operation of the present invention; FIG. 8 is a diagram showing the format of the editing commands used in explaining the operation of the present invention; FIG. Figures 3i and 4 are diagrams used to illustrate the operation of the systems; Figure 9 is a diagram defining the cycles required to process the instructions of Figure 8 according to the present invention; and Figure 10 is a diagram according to the present invention. The processor 7 required to process the instructions of FIG.
1 is a flow chart showing a sequence of 00. 100...System interface unit (SIU), 200...Input/output processor (IOPP), 3
00...High speed multiplexer (HSMX), 400
...Low speed multiplexer (LSMX), 500...
Local memory module, 600-604...
Interface, 700...Upper processor, 7
50...Katsushie memory, 800...Remote memory module.

Claims (1)

Claims: 1. Addressable main memory having a plurality of word storage locations for storing information including data and instructions; and immediate access to data and instructions retrieved and stored from said main memory. a buffer storage controller coupled to the main memory to provide a buffer storage controller having a plurality of addressable storage locations and for retrieving the information from the main memory in response to a storage command; a high speed buffer storage device; and an apparatus for processing instructions of the usual type, each having an operation code portion and a plurality of descriptor address portions, the device being coupled to the high speed buffer storage device and having a plurality of descriptor address portions; a processing device including a control device for generating a signal including the storage command necessary for the execution of a plurality of descriptor addresses specified by the plurality of descriptor address portions that can be processed simultaneously; decoder circuitry responsive to a signal indicative of said operation code portion of each type of instruction of said general type encoded to specify an operation relating to an operand data string of said decoder circuitry; and prefetching one predetermined segment of data of a first operand string specified by an address expanded from the first of the plurality of instruction descriptor address portions. the buffer storage controller is operative to generate a storage command signal with a set of encoded instructions specifying that the predetermined segment specified by the storage command said one generating a signal for sending said storage command to said main memory for retrieving said segment of data and pre-storing it in said buffer storage when not stored in said buffer storage; responsive to a set of encoded command signals to continue processing another one of the plurality of descriptor address portions of each of the types of instructions, thereby executing each of the predetermined types of instructions; A data processing system comprising: enabling a plurality of signals for conditioning said processing controller to increase the efficiency of said processing controller.