JPS6226185B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate for mounting a semiconductor device, and more particularly to an external lead lead-out structure in a thick film or thin film substrate having required conductive wiring on its surface.

Ceramics, which have good electrical, mechanical, and thermal properties, are often used as materials for semiconductor device mounting substrates, supporting the high reliability of these semiconductor devices.
Predetermined conductive wiring is formed on the surface of this substrate for mounting semiconductor devices, and except for the parts that should be connected to semiconductor devices and other circuit elements, the upper surface is used to protect the conductive wiring and provide electricity. A surface insulating layer made of alumina, glass, or the like is provided to ensure insulation and prevent the brazing material from flowing during bonding. A surface insulating layer of alumina, glass, or the like is not provided on the external lead lead-out portion of the conductive wiring to which the external lead is soldered and connected to an external circuit. After the external leads are brazed to the substrate, a predetermined plating is applied, and a plating layer is formed on the portions not covered with the surface insulating layer such as glass.

By the way, such boards with external leads connected to them are exposed to various environments.
One example is a high temperature and high humidity environment. Under such an environment, corrosion of untreated portions by moisture becomes a problem. Test methods are specified for this environment, and tests are typically conducted at 65°C and 95% relative humidity. Under such an environment, if the plating structure is normally made of Ni plating and Au plating, some rust will occur even after 1000 hours have passed, but no fatal defects leading to loss of electrical continuity will occur. In the above-mentioned external lead lead-out structure, the boundary between the surface-treated part and the plated part is selectively eroded, even though no foreign matter such as rust is observed in other parts. It was found that this resulted in the fatal defect of wire breakage. This phenomenon can be understood as follows. In other words, conductive wiring on a ceramic substrate is usually obtained by firing Mo, Mo-Mu, and W, but these metal wiring layers are porous due to degassing during firing, so they have poor corrosion resistance against moisture. is known to be low. Normally, this metal is protected by Ni plating and then Au plating, but at the boundary between the surface-treated part, that is, the part with a surface insulating layer such as alumina, and the plated part. The plating will not adhere to the surface-treated side, resulting in poor adhesion. As a result, moisture in a high-temperature, high-humidity environment can easily infiltrate through the boundary portion, reach the conductive wiring, and corrode the wiring portion.

The present invention provides an effective substrate that eliminates the drawbacks of the prior art, that is, a substrate for mounting semiconductor devices that has an external lead lead-out structure that does not cause fatal defects such as disconnections in conductive wiring even under high temperature and high humidity environments. be.

A feature of the present invention is that the surface-treated portion is extended and the selectively eroded portion is moved below the brazed portion of the external lead.

The present invention will be explained below using examples. 1st
The figure is a sectional view of a conventional external lead lead-out portion.
That is, conductive wiring 2 is provided on an alumina substrate 1,
Surface treatment, that is, alumina coating 3 is applied except for the brazed parts. Next, after firing this substrate 1, Ni plating 4 is applied to the exposed conductive wiring layer, and external leads 6 are connected using Ag--Cu brazing material 5. And Ni plating 1 on the entire exposed metal surface.
4 was applied, and on top of that, Au plating 7 was applied.

However, at the boundary 10 between the exposed metal part (in this case, the Au-plated surface 7) and the alumina coating layer 3, in a high temperature and high humidity environment, the conductive wiring 2 metalized with W is selectively eroded and eluted. This will cause a disconnection accident.

FIG. 2 shows an embodiment of the invention. In the present invention, the alumina coating layer 13 is applied to the entire surface except for the through hole 8 provided directly below the external lead 6 and a predetermined portion, and the upper conductive wiring 30 to which the external lead 6 is to be brazed is coated on this surface insulating layer. It is also formed on a part of 13. If you do this,
Even if the metallization is slightly eroded at the end portion 20 of the upper conductive wiring 30 for brazing of the external lead 6, it will not lead to disconnection and will not be a fatal defect.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an external lead lead-out portion of a conventional semiconductor device mounting board. FIG. 2 is a sectional view of an external lead lead-out portion in one embodiment of the present invention. In addition, in the figure, 1... alumina substrate, 2...
conductive wiring, 3... alumina coating layer, 4,
14...Ni plating layer, 5...Ag-Cu brazing material layer,
6... External lead, 7... Au plating layer, 8...
Through holes 10, 20...boundary between exposed metal portion and alumina coating layer, 30...upper conductive wiring.

Claims (1)

[Claims] 1 a surface insulating substrate, a conductive wiring provided on the surface insulating substrate, a surface insulating layer covering the conductive wiring and having a through hole exposing the conductive wiring at a predetermined portion; It is characterized by having an upper conductive wiring layer that extends from the conductive wiring through the through hole onto the surface insulating layer, and an external lead that covers the through hole and is attached to the upper conductive wiring layer. A substrate for mounting semiconductor devices.