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JPS6226186B2 - - Google Patents
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JPS6226186B2 - - Google Patents

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Publication number
JPS6226186B2
JPS6226186B2 JP53143037A JP14303778A JPS6226186B2 JP S6226186 B2 JPS6226186 B2 JP S6226186B2 JP 53143037 A JP53143037 A JP 53143037A JP 14303778 A JP14303778 A JP 14303778A JP S6226186 B2 JPS6226186 B2 JP S6226186B2
Authority
JP
Japan
Prior art keywords
halves
input
output
lines
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53143037A
Other languages
Japanese (ja)
Other versions
JPS5568668A (en
Inventor
Yoshitaka Kitano
Makoto Terajima
Hiroshi Egawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14303778A priority Critical patent/JPS5568668A/en
Publication of JPS5568668A publication Critical patent/JPS5568668A/en
Publication of JPS6226186B2 publication Critical patent/JPS6226186B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10Integrated device layouts

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は、半導体ウエハを有効に利用した大規
模な半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a large-scale semiconductor device that effectively utilizes semiconductor wafers.

従来の半導体装置は、所要の回路を形成した数
mm2乃至10mm2の四角形の半導体チツプの単数又は複
数個が実装担体上に実装されてなる構成を有して
いた。此処に半導体チツプは、通常、1インチか
ら数インチの直径をもつ円形の半導体ウエハ上に
所要の回路を、多数、半導体集積加工技術を用い
て形成した後、半導体ウエハを小さく切断して得
られるものである。又、半導体チツプの実装担体
上での実装態様は、斯る半導体チツプが予め配線
の施された実装担体(例えばセラミツク板)上の
所定の位置に固定され、そして半導体チツプ上の
配線端子と実装担体上の配線とが電気的に接続さ
れてなる態様を有するものである。
Conventional semiconductor devices have a number of required circuits formed.
It had a configuration in which one or more rectangular semiconductor chips of mm 2 to 10 mm 2 were mounted on a mounting carrier. Semiconductor chips here are usually obtained by forming a large number of required circuits on a circular semiconductor wafer with a diameter of 1 inch to several inches using semiconductor integrated processing technology, and then cutting the semiconductor wafer into small pieces. It is something. Furthermore, in the mounting mode of the semiconductor chip on the mounting carrier, the semiconductor chip is fixed at a predetermined position on the mounting carrier (for example, a ceramic board) on which wiring has been applied in advance, and the wiring terminals on the semiconductor chip and the mounting It has an aspect in which the wiring on the carrier is electrically connected.

従つて、従来の半導体装置の場合、それが複雑
な多くの回路からなる場合、半導体ウエハの切
断、実装担体上への半導体チツプの固定、配線接
続等の実装に多くの工数を要するという問題があ
つた。又、半導体ウエハがそれに形成される回路
に要する面積の外、切断の為の大なる切りしろ面
積を有するものでなければならなかつた。因み
に、切りしろとしては、80μm程の幅が必要であ
るので、例えば5mm角の半導体チツプを半導体ウ
エハより100個切り出す場合、半導体ウエハは、
3個の半導体チツプ相当分の面積を切りしろ面積
として必要とするものであつた。
Therefore, in the case of conventional semiconductor devices, when the devices consist of many complex circuits, there is a problem that it takes a lot of man-hours to cut the semiconductor wafer, fix the semiconductor chips on the mounting carrier, and connect the wiring. It was hot. Furthermore, in addition to the area required for the circuits formed on the semiconductor wafer, it must also have a large margin for cutting. By the way, the width of the cutting allowance is about 80 μm, so if, for example, 100 5 mm square semiconductor chips are cut from a semiconductor wafer, the semiconductor wafer will have a width of about 80 μm.
This required an area equivalent to three semiconductor chips as a margin area.

一方、半導体集積加工技術、マスク製作技術の
著しい進歩により、数10mm2以上の大きな半導体チ
ツプの製作が可能となり、この為、斯る大きな半
導体チツプの使用により、大規模な半導体装置の
実現の可能性が生じてきた。然し乍ら、半導体チ
ツプを従来のように四角形に整形されたものとす
る場合、円形の半導体ウエハの周辺部には、回路
形成に利用できない無駄な部分が生じる欠点を有
していた。例えば、半導体チツプが正方形で、そ
の対角線が半導体ウエハの半径を越えるような場
合、1個の半導体チツプしか形成できなくなり、
この場合、半導体ウエハの回路形成に利用できる
面積は16〜63%に過ぎす、残りの面積は利用でき
ないで捨てられることになるものであつた。この
ことは、四角形の半導体チツプを使用した半導体
装置を経済的に得るのに大きな障害になるもので
あつた。
On the other hand, significant advances in semiconductor integrated processing technology and mask manufacturing technology have made it possible to manufacture large semiconductor chips of several tens of mm 2 or more. Therefore, by using such large semiconductor chips, it is possible to realize large-scale semiconductor devices. Gender has emerged. However, when a semiconductor chip is shaped into a rectangular shape as in the prior art, there is a drawback that there is a wasted area around the circular semiconductor wafer that cannot be used for circuit formation. For example, if the semiconductor chip is square and its diagonal exceeds the radius of the semiconductor wafer, only one semiconductor chip can be formed.
In this case, only 16 to 63% of the area of the semiconductor wafer can be used for circuit formation, and the remaining area cannot be used and is wasted. This has been a major hindrance to economically producing semiconductor devices using rectangular semiconductor chips.

又、上述せる従来の半導体装置とは異なつた形
態として、半導体ウエハを切らずそのまま用いて
なる半導体装置が提案されている。然し乍ら、半
導体装置としては半導体ウエハ全面を使う程の大
規模なものではなく、半導体ウエハ面積の1/2
あるいは1/4程度の集積化ですむ様なものも多
くあり得、その様な場合は当然利用されない無駄
な面積が半導体ウエハに残されることとなるもの
である。
Further, as a different form from the conventional semiconductor device described above, a semiconductor device has been proposed in which a semiconductor wafer is used as is without being cut. However, the semiconductor device is not large enough to use the entire semiconductor wafer, but only 1/2 of the semiconductor wafer area.
Alternatively, there may be many cases in which only about 1/4 of the integration is required, and in such a case, a wasted area that is not used will naturally remain on the semiconductor wafer.

依つて、本発明は上述せる欠点のない新規な半
導体装置を提案せんとするもので、以下図面を伴
つて詳述する所より明らかとなるであろう。
Therefore, the present invention aims to propose a novel semiconductor device free from the above-mentioned drawbacks, which will become clear from the detailed description below with reference to the drawings.

第1図は本発明による半導体装置の1つの実施
例を示し、トランジスタ、抵抗、容量素子等の所
要の回路機能を有する回路ブロツクAの複数をA
11〜A15,A16〜A18及びA19として
形成してなる円形の半導体ウエハの2等分されて
なる2等分片Bと、同様の回路ブロツクAの複数
をA21〜A25,A26〜A28及びA29と
して形成してなる半導体ウエハの2等分されてな
る2等分片Bとが、一対の2等分片B11及びB
21として、実装担体1上に装架されてなる構成
を有する。
FIG. 1 shows one embodiment of a semiconductor device according to the present invention, in which a plurality of circuit blocks A having required circuit functions such as transistors, resistors, capacitors, etc.
11 to A15, A16 to A18, and A19, and a plurality of similar circuit blocks A are designated as A21 to A25, A26 to A28, and A29. The semiconductor wafer thus formed is divided into two equal halves B, and a pair of halves B11 and B
21 has a configuration in which it is mounted on the mounting carrier 1.

この場合、2等分片B11に形成された回路ブ
ロツクA11〜A15,A16〜A18、及びA
19は、それ等の入力線が2等分片B11上に形
成された配線を介してそれ等に共通の入力端子1
1に接続され、また、出力線が同様に2等分片B
11上に形成された配線を介してそれ等に共通の
出力端子O1に接続され、さらに、制御線が同様
に2等分片B11上に形成された配線を介してそ
れ等に共通の制御端子G1に夫々接続されてい
る。
In this case, the circuit blocks A11 to A15, A16 to A18, and A
19 is an input terminal 1 whose input lines are common to them via wiring formed on the bisecting piece B11.
1, and the output wire is also connected to the bisecting piece B
The control line is connected to the output terminal O1 common to them via a wiring formed on the bisecting piece B11, and the control line is also connected to the common control terminal O1 through a wiring formed on the bisecting piece B11. G1 respectively.

又、2等分片B21に形成された回路ブロツク
A21〜A25,A26〜A28及びA29も、
それ等の入力線、出力線及び制御線が、2等分片
B21上に形成された配線を介して同様に共通の
入力端子I2、出力端子O2及び制御端子G2に
夫々接続されている。
In addition, the circuit blocks A21 to A25, A26 to A28 and A29 formed on the bisected piece B21 are also
These input lines, output lines, and control lines are similarly connected to the common input terminal I2, output terminal O2, and control terminal G2, respectively, via wiring formed on the bisecting piece B21.

さらに、入力端子I1及びI2;出力端子O1
及びO2;及び制御端子G1及びG2が、夫々実
装担体1上に形成された共通の入力線I12;出
力線O112;及び制御線G12に夫々接続さ
れ、而して、2等分片B11及びB21上に夫々
形成された回路ブロツクA11及びA21;A1
2及びA22;………A19及びA29の組が、
制御線G12に供給される制御信号に基き、順
次、各組に関し同じ態様を以つて制御され、そし
て、回路ブロツクA11及びA21;A12及び
A22;………A19及びA29の組が、入力線
I12に供給される入力信号を、順次、各組に関
し同じ態様を以つて処理して、その処理出力を出
力線O12に順次導出する様なされている。
Furthermore, input terminals I1 and I2; output terminal O1
and O2; and control terminals G1 and G2 are respectively connected to the common input line I12; output line O112; and control line G12 formed on the mounting carrier 1, and thus the bisecting pieces B11 and B21 Circuit blocks A11 and A21 formed thereon; A1
2 and A22;...The set of A19 and A29 is
Based on the control signal supplied to the control line G12, each set is sequentially controlled in the same manner, and the sets of circuit blocks A11 and A21; A12 and A22;...A19 and A29 are connected to the input line I12. The input signals supplied to each set are sequentially processed in the same manner for each set, and the processed outputs are sequentially derived to the output line O12.

以上が、本発明による半導体装置の実施例の構
成である。
The above is the configuration of the embodiment of the semiconductor device according to the present invention.

このような本発明の実施例の構成によれば、そ
れが、半導体ウエハの2等分されてなる2等分片
B11及びB21が実装担体1上に実装されてな
る構成を有し、そして、それら半導体ウエハの2
等分されてなる2等分片B11及びB12が、半
導体ウエハをたゞ1回切断するだけで直ちに得ら
れるので、半導体装置を、少ない実装上の工数
で、大規模なものとして容易に得ることが出来る
と共に、2等分片B11及びB12に形成してい
る回路ブロツクAの数を、図示のように9個とす
るように、十分大なるものとすることによつて、
2等分片B11及びB12の全面積を有効に利用
できるので、半導体ウエハの利用効率が従来の場
合に比し格段的に増大することとなる大なる特徴
を有するものである。
According to the configuration of the embodiment of the present invention, it has a configuration in which two equal pieces B11 and B21 obtained by dividing a semiconductor wafer into two are mounted on the mounting carrier 1, and, Two of those semiconductor wafers
Since the two equal parts B11 and B12 can be obtained immediately by cutting the semiconductor wafer once, it is possible to easily obtain a large-scale semiconductor device with a small number of mounting steps. By making the number of circuit blocks A formed in the bisecting pieces B11 and B12 sufficiently large to nine as shown in the figure,
Since the entire area of the bisecting pieces B11 and B12 can be effectively utilized, the semiconductor wafer utilization efficiency is significantly increased compared to the conventional case.

また、第1図に示す本発明の実施例の構成によ
れば、一方の2等分片B11上の回路ブロツクA
11及び他方の2等分片B21上の回路ブロツク
A21の組、A12及びA22の組、A13及び
A23,………A19及びA29の組が、上述せ
る如く、順次、但し各組に関し同じ態様を以つ
て、入力信号を処理し、その処理出力を出力線O
12に順次導出する様になされているので、2等
分片B11、及びB21に関し、その回路ブロツ
クA11〜A19、及びA21〜A29中に、
夫々不良回路ブロツクがあるとしても、例えば第
1図中、斜線で施されている如く、2等分片B1
1に関し、回路ブロツクA13,A15及びA1
8が、2等分片B21に関し回路ブロツクA2
2,A24及びA29が不良回路ブロツクである
如くに2等分片B11及びB21に不良回路ブロ
ツクがあるとしても、それら不良回路ブロツクの
不良箇所が互に相補関係を有していさえすれば
(但し、この場合、不良回路ブロツクの存在によ
つて不良でない回路ブロツクの動作が影響を受け
ることのない様に各回路ブロツクが構成されてい
るものとする)、半導体装置との全体としての所
期の機能が失なわれることはないものである。
Further, according to the configuration of the embodiment of the present invention shown in FIG.
11 and the other bisected piece B21, the set of circuit blocks A21, the set of A12 and A22, the set of A13 and A23, . Thus, the input signal is processed and the processed output is sent to the output line O.
12, the circuit blocks A11 to A19 and A21 to A29 of the bisectors B11 and B21 are
Even if there is a defective circuit block, for example, as shown by diagonal lines in FIG.
1, circuit blocks A13, A15 and A1
8 is the circuit block A2 regarding the bisecting piece B21.
Even if there are defective circuit blocks in the bisecting pieces B11 and B21, such as A24 and A29 being defective circuit blocks, as long as the defective parts of these defective circuit blocks have a mutually complementary relationship (provided that In this case, it is assumed that each circuit block is configured so that the operation of non-defective circuit blocks is not affected by the existence of a defective circuit block), and the intended relationship with the semiconductor device as a whole is maintained. It never loses its functionality.

従つて、第1図にて上述せる本発明の実施例に
よれば、複数の半導体ウエハの夫々につき、それ
を2等分して第1図に示すごとき2等分片の多数
を得た場合に、その多数の2等分片が不良回路ブ
ロツクを有するものとして得られていたとして
も、それ等中、不良回路ブロツク位置の互に重な
らない、即ち、不良箇所に関し互に相補関係を有
する2つの2等分片を選択して、これ等を実装担
体上に実装することにより、所期の機能の得られ
る半導体装置を構成し得、依つて、半導体ウエハ
を有効に利用して大規模な半導体装置を高歩留り
で得ることが出来る大なる特徴を有するものであ
る。
Therefore, according to the embodiment of the present invention described above with reference to FIG. 1, when each of a plurality of semiconductor wafers is divided into two halves to obtain a large number of halves as shown in FIG. Even if a large number of bisected pieces are obtained as having defective circuit blocks, among them, the defective circuit block positions do not overlap with each other, that is, the two halves have a mutually complementary relationship with respect to the defective locations. By selecting two halves and mounting them on a mounting carrier, it is possible to construct a semiconductor device that provides the desired function. It has a great feature that semiconductor devices can be obtained with high yield.

尚、第1図にて上述せる実施例に於ては不良箇
所が互に相補関係にある、半導体ウエハの2等分
されて得られた一対の2等分片B11及びB21
が実装担体1上に実装されている場合につき例示
したものであるが、詳細説明はこれを省略する
も、第2図に示す如く、不良箇所が互に相補関係
にある、半導体ウエハの2等分されて得られた対
の2等分片の組の複数がB11及びB21,B1
2及びB22,………として実装担体1上に実装
されてなる構成とすること、第3図に示す如く、
不良箇所が互に相補関係にある、半導体ウエハの
4等分されて得られた対の4等分片の組の複数が
C11及びC21,C12及びC22,………と
して実装担体1上に実装されてなる構成とするこ
とも出来、斯くしても、第1図にて上述せると同
様の特徴が得られることが明らかであろう。
In the embodiment described above with reference to FIG. 1, a pair of bisected pieces B11 and B21 obtained by dividing the semiconductor wafer into two halves, whose defective locations are in a complementary relationship with each other, are used.
Although the detailed explanation is omitted, as shown in FIG. A plurality of pairs of bisected pieces obtained by dividing are B11, B21, B1
2 and B22, . . . are mounted on the mounting carrier 1, as shown in FIG.
A plurality of sets of pairs of quarter pieces obtained by dividing the semiconductor wafer into quarters, in which the defective parts have a mutually complementary relationship, are mounted on the mounting carrier 1 as C11 and C21, C12 and C22, etc. It will be clear that the same features as those described above with reference to FIG. 1 can be obtained even in this case.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明による半導体装置の1つの実
施例を示す略線的平面図である。第2図、第3図
は、夫々本発明の他の実施例を示す略線的平面図
である。 1…実装担体、B11,B12………,B2
1,B22…半導体ウエハの2等分片、C11,
C12………,C21,C22…半導体ウエハの
4等分片、A11〜A19,A21〜A29…回
路ブロツク、I1,I2…入力端子、O1,O2
…出力端子、G1,G2…制御端子、I12…入
力線、O12…出力線、G12…制御線。
FIG. 1 is a schematic plan view showing one embodiment of a semiconductor device according to the present invention. FIGS. 2 and 3 are schematic plan views showing other embodiments of the present invention. 1... Mounting carrier, B11, B12......, B2
1, B22...Half piece of semiconductor wafer, C11,
C12......, C21, C22... Quarter piece of semiconductor wafer, A11-A19, A21-A29... Circuit block, I1, I2... Input terminal, O1, O2
...output terminal, G1, G2...control terminal, I12...input line, O12...output line, G12...control line.

Claims (1)

【特許請求の範囲】 1 円形の半導体ウエハの2等分又は4等分され
て得られた、複数の回路ブロツクが形成されてい
る少なくとも1対の第1及び第2の2等分片又は
4等分片が、実装担体上に実装され、 上記第1及び第2の2等分片又は4等分片が、
内部の不良箇所に関し互に相補関係を有し、 上記一対の2等分片中の第1の2等分片又は4
等分片に形成されている複数の回路ブロツクの入
力線、出力線、及び制御線が、それぞれ当該第1
の2等分片又は4等分片上に形成された配線を介
して共通の第1の入力端子、第1の出力端子、及
び第1の制御端子に接続され、 上記一対の2等分片中の第1の2等分片又は4
等分片に形成されている複数の回路ブロツクの入
力線、出力線、及び制御線が、それぞれ当該第2
の2等分片又は4等分片上に形成された配線を介
して共通の第2の入力端子、第2の出力端子、及
び第2の制御端子に接続され、 上記第1及び第2の入力端子、第1及び第2の
出力端子、及び第1及び第2の制御端子が、それ
ぞれ上記実装担体上に形成された共通の入力線、
出力線、及び制御線に接続されている構成を有す
る事を特徴とする半導体装置。
[Scope of Claims] 1. At least one pair of first and second halves or four halves in which a plurality of circuit blocks are formed, obtained by dividing a circular semiconductor wafer into halves or quarters. The equal pieces are mounted on a mounting carrier, and the first and second halves or quarter pieces are
The first two halves of the pair of halves or the four halves have a mutually complementary relationship with respect to internal defective parts
The input lines, output lines, and control lines of a plurality of circuit blocks formed in equal pieces are connected to the first circuit block, respectively.
connected to a common first input terminal, a first output terminal, and a first control terminal via wiring formed on the halves or quarters of the pair of halves, the first two halves of or 4
The input lines, output lines, and control lines of a plurality of circuit blocks formed in equal pieces are connected to the second circuit block, respectively.
connected to a common second input terminal, a second output terminal, and a second control terminal via wiring formed on a bisecting piece or a quarter piece of the first and second input terminals; a common input line in which a terminal, first and second output terminals, and first and second control terminals are respectively formed on the mounting carrier;
A semiconductor device characterized by having a configuration in which it is connected to an output line and a control line.
JP14303778A 1978-11-20 1978-11-20 Semiconductor device Granted JPS5568668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14303778A JPS5568668A (en) 1978-11-20 1978-11-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14303778A JPS5568668A (en) 1978-11-20 1978-11-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5568668A JPS5568668A (en) 1980-05-23
JPS6226186B2 true JPS6226186B2 (en) 1987-06-08

Family

ID=15329427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14303778A Granted JPS5568668A (en) 1978-11-20 1978-11-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5568668A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2516403B2 (en) * 1988-06-01 1996-07-24 富士通株式会社 Wafer scale memory
US5016080A (en) * 1988-10-07 1991-05-14 Exar Corporation Programmable die size continuous array

Also Published As

Publication number Publication date
JPS5568668A (en) 1980-05-23

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