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JPS6226574B2 - - Google Patents
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JPS6226574B2 - - Google Patents

Info

Publication number
JPS6226574B2
JPS6226574B2 JP55027538A JP2753880A JPS6226574B2 JP S6226574 B2 JPS6226574 B2 JP S6226574B2 JP 55027538 A JP55027538 A JP 55027538A JP 2753880 A JP2753880 A JP 2753880A JP S6226574 B2 JPS6226574 B2 JP S6226574B2
Authority
JP
Japan
Prior art keywords
nitride film
silicon nitride
film
electrode
platinum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55027538A
Other languages
Japanese (ja)
Other versions
JPS56124232A (en
Inventor
Yasumi Hamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP2753880A priority Critical patent/JPS56124232A/en
Publication of JPS56124232A publication Critical patent/JPS56124232A/en
Publication of JPS6226574B2 publication Critical patent/JPS6226574B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs

Landscapes

  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に係り、特に半
導体基板表面の絶縁膜と電極金属との密着力を向
上せしめることを目的としたものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and is particularly aimed at improving the adhesion between an insulating film on the surface of a semiconductor substrate and an electrode metal.

従来、高信頼度高品質を要求されるトランジス
タに於いては、電極金属として白金シリサイド―
チタン―白金―金より成る多重構造の電極が採用
されてきた。
Conventionally, platinum silicide has been used as the electrode metal for transistors that require high reliability and high quality.
Multilayer electrodes made of titanium-platinum-gold have been used.

しかし、チタンは半導体基体表面および表面に
達するPN接合の保護のためのシリコン酸化膜と
の密着が悪い理由で、シリコン酸化膜とチタンと
の界面で電極金属が剥れるという欠点があつた。
そこで最近は、シリコン酸化膜上に気相成長によ
りシリコン窒化膜を形成し、そのシリコン窒化膜
上にチタン―白金―金の電極金属を形成する方法
が採用されている。
However, titanium has a drawback that the electrode metal peels off at the interface between the silicon oxide film and titanium because titanium does not adhere well to the surface of the semiconductor substrate and the silicon oxide film that protects the PN junction that reaches the surface.
Therefore, recently, a method has been adopted in which a silicon nitride film is formed by vapor phase growth on a silicon oxide film, and an electrode metal of titanium-platinum-gold is formed on the silicon nitride film.

すなわち、半導体素子形成後の電極形成前に半
導体基板全面にシリコン窒化膜を形成し、半導体
基板の表面と裏面との間に降伏電圧以上の逆電圧
を長時間印加する。そうすると、半導体素子の電
極接触部となるべきシリコン表面上のシリコン窒
化膜が化成膜となる。その化成膜は、弗酸系の蝕
刻液で容易に取り除くことができ、その上に金属
電極を形成すれば清浄な窒化膜上に電極を形成し
たことになり、前記シリコン窒化膜と電極との密
着性も向上させることができる。
That is, after semiconductor elements are formed and before electrodes are formed, a silicon nitride film is formed over the entire surface of the semiconductor substrate, and a reverse voltage equal to or higher than the breakdown voltage is applied for a long time between the front and back surfaces of the semiconductor substrate. Then, the silicon nitride film on the silicon surface, which is to become the electrode contact portion of the semiconductor element, becomes a chemically formed film. The chemically formed film can be easily removed with a hydrofluoric acid-based etchant, and if a metal electrode is formed on it, the electrode is formed on a clean nitride film, and the silicon nitride film and electrode are formed on a clean nitride film. The adhesion can also be improved.

しかし、前記半導体素子部の開孔部上のシリコ
ン窒化膜を化成するときの印加電圧、時間等の指
定条件が容易ではなく、ともすれば、化成膜にな
りきれず、シリコン窒化膜残りが発生していた。
さらに、窒化膜の化成が進みすぎてシリコン面内
部までが化成され、このため、電極とのオーミツ
クコンタクトのために白金シリサイド層を形成す
ると、特に高周波用トランジスタの如く浅いエミ
ツタ領域をもつものでは、白金がより浅くなつた
エミツタ領域を貫通してベース領域まで達してエ
ミツタ・ベース短絡がおこつてしまう。このよう
に、従来の方法では電極通電不良又は接合破壊と
いう欠点があり、歩留および信頼性の低下が問題
となつていた。
However, when forming the silicon nitride film on the opening of the semiconductor element part, it is not easy to specify conditions such as applied voltage and time, and in some cases, the chemical formation film cannot be completely formed and the remaining silicon nitride film remains. It was occurring.
Furthermore, the formation of the nitride film progresses so much that the inside of the silicon surface is formed, and for this reason, when a platinum silicide layer is formed for ohmic contact with the electrode, it is difficult to form a platinum silicide layer, especially for devices with shallow emitter regions such as high frequency transistors. , the platinum penetrates the shallower emitter region and reaches the base region, causing an emitter-base short circuit. As described above, the conventional method has drawbacks such as poor electrode energization or bond breakdown, resulting in problems of reduced yield and reliability.

よつて本発明の目的は、歩留り向上と共に高信
頼性で、かつ多層電極の密着性を改善した製造方
法を提供することにある。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a manufacturing method that has improved yield, high reliability, and improved adhesion of multilayer electrodes.

本発明によれば、半導体素子の電極接触のため
の開孔部を形成したのち、その露出した半導体面
に白金シリサイドを形成し、そののちシリコン窒
化膜で被い、それから開孔部上の余分なシリコン
窒化膜を化成膜に換えて取り除き、そしてそのう
えで多層電極を形成することを特徴とする半導体
装置の製造方法をえる。
According to the present invention, after forming an opening for contacting an electrode of a semiconductor element, platinum silicide is formed on the exposed semiconductor surface, and then covered with a silicon nitride film, and then the excess on the opening is formed. A method for manufacturing a semiconductor device is provided, which is characterized in that a silicon nitride film is removed by replacing it with a chemically formed film, and then a multilayer electrode is formed thereon.

本発明の製造方法によれば、開孔部の半導体界
面は安定しているので特性上何ら影響を与えず、
しかも清浄なシリコン窒化膜上多層電極が形成さ
れるのでその密着性も向上させる事ができる。
According to the manufacturing method of the present invention, since the semiconductor interface at the opening is stable, it does not affect the characteristics in any way.
Moreover, since a multilayer electrode is formed on a clean silicon nitride film, its adhesion can also be improved.

以下、図面を参照しながら本発明をより詳細な
説明する。
Hereinafter, the present invention will be described in more detail with reference to the drawings.

第1図乃至第3図は、上述した従来の製造方法
である素子形成後全面にシリコン窒化膜を形成
し、半導体素子部の開孔部上のシリコン窒化膜を
化成膜にするときの工程断面図である。
Figures 1 to 3 show the steps of the conventional manufacturing method described above, in which a silicon nitride film is formed on the entire surface after the element is formed, and the silicon nitride film on the opening of the semiconductor element is converted into a chemical film. FIG.

すなわち、半導体基板1上にベース領域2及び
エミツタ領域3を形成したのち、基板上のシリコ
ン酸化膜4に電極引出用の開孔部を写真蝕刻法に
より形成し、そして、全面にシリコン窒化膜5を
形成せしめる(第1図)。
That is, after forming a base region 2 and an emitter region 3 on a semiconductor substrate 1, an opening for leading out an electrode is formed in a silicon oxide film 4 on the substrate by photolithography, and then a silicon nitride film 5 is formed on the entire surface. (Figure 1).

次に、半導体基板1の表面と裏面との間に逆電
圧(NPNトランジスタであるので裏面に正、表
面に負の電圧)を印加すると、ベース領域2およ
びエミツタ領域3と接触するシリコン窒化膜5が
化成されて化成膜6が形成される(第2図)。
Next, when a reverse voltage is applied between the front surface and the back surface of the semiconductor substrate 1 (positive voltage on the back surface and negative voltage on the front surface since it is an NPN transistor), the silicon nitride film 5 in contact with the base region 2 and emitter region 3 is applied. is chemically converted to form a chemically formed film 6 (FIG. 2).

そして、半導体基板1に形成された化成膜6を
除去する(第3図)。しかし、このとき化成膜6
を形成するための化成条件が一様でも、窒化膜5
の厚さばらつき等によりすべてが化成されずシリ
コン窒化膜残り7が生じたり、化成がすすみすぎ
て基板1の表面に歪み8が発生していた。このた
め、エミツタ領域3と電極との接触がなされず、
又ベース領域2の表面歪8のために特性面で悪影
響を与えていた。
Then, the chemically formed film 6 formed on the semiconductor substrate 1 is removed (FIG. 3). However, at this time, the chemical film 6
Even if the chemical formation conditions for forming the nitride film 5 are uniform, the nitride film 5
Due to variations in the thickness of the substrate 1, not all of the silicon nitride film was formed, leaving a silicon nitride film 7, or the formation progressed too much, causing distortions 8 on the surface of the substrate 1. For this reason, there is no contact between the emitter region 3 and the electrode,
Furthermore, the surface strain 8 in the base region 2 had an adverse effect on the characteristics.

そこで、本発明はかかる欠点を解消せしめるた
めに、まず、ベース領域12およびエミツタ領域
13が形成された半導体基板1上のシリコン酸化
膜14に開孔を施し、各領域12および13の電
極取り出し部を形成し、そして、その部分に白金
シリサイド層15を形成する(第4図)。この方
法として、シリコン基板1全面に蒸着もしくはス
パツタ法等により白金を約100Å被着し、約450℃
のアルゴン雰囲気中で30分程度熱処理を行なう。
そして、シリコン酸化膜14上の余分な白金は、
王水中に数分程度浸漬すると溶解除去され白金シ
リサイド15が形成できる。
Therefore, in order to eliminate such drawbacks, the present invention first makes holes in the silicon oxide film 14 on the semiconductor substrate 1 on which the base region 12 and the emitter region 13 are formed, and makes electrode extraction portions in each region 12 and 13. Then, a platinum silicide layer 15 is formed in that portion (FIG. 4). In this method, approximately 100 Å of platinum is deposited on the entire surface of the silicon substrate 1 by vapor deposition or sputtering, and the temperature is approximately 450°C.
Heat treatment is performed for about 30 minutes in an argon atmosphere.
Then, the excess platinum on the silicon oxide film 14 is
When immersed in aqua regia for several minutes, it is dissolved and removed, forming platinum silicide 15.

次に、全面にシリコン窒化膜16を厚さ300Å
程度気相成長法で形成し、半導体基板1の表面に
負、裏面に正の電圧、例えばその電位差130V、
100mAで50分間逆バイアスし、白金シリサイド
層15上の窒化膜16を化成膜17にする(第5
図)。このとき、白金シリサイド層15は基板1
に比して著しい硬く、又この層15は化成されな
いので、窒化膜16を充分化成しても、半導体表
面に歪を発生させない。
Next, a silicon nitride film 16 is applied to the entire surface to a thickness of 300 Å.
A negative voltage is applied to the front surface of the semiconductor substrate 1 and a positive voltage is applied to the back surface of the semiconductor substrate 1, for example, a potential difference of 130 V,
Reverse bias is applied at 100 mA for 50 minutes to turn the nitride film 16 on the platinum silicide layer 15 into a chemically formed film 17 (fifth
figure). At this time, the platinum silicide layer 15 is
Furthermore, since this layer 15 is not chemically formed, even if the nitride film 16 is sufficiently formed, no strain will be generated on the semiconductor surface.

その後、弗酸:純水=1:50の混合液に約1分
間浸たして、化成膜17を除去する(第6図)。
Thereafter, the chemical film 17 is removed by immersing it in a mixed solution of hydrofluoric acid and pure water at a ratio of 1:50 for about 1 minute (FIG. 6).

そして、清浄なシリコン窒化膜16上にチタン
―白金―金の多層電極18を形成する(第7
図)。
Then, a titanium-platinum-gold multilayer electrode 18 is formed on the clean silicon nitride film 16 (seventh
figure).

かかる製造方法によれば、シリコン窒化膜16
を化成するとき、白金シリサイド層15がベース
領域12およびエミツタ領域13への化成進行を
防ぐので、窒化膜残りを解消するに充分な量だけ
窒化膜16を化成でき、しかも、シリコン表面内
部までの化成も発生しない。従つて、安定な半導
体表面を有し、かつ清浄なシリコン窒化膜16上
に多層電極18を形成するので、歩留りが高く高
信頼性の良好な密着性をもつ多層電極18を有す
る半導体装置を提供できる。
According to this manufacturing method, the silicon nitride film 16
When forming the silicon, the platinum silicide layer 15 prevents the formation from proceeding to the base region 12 and emitter region 13. Therefore, the nitride film 16 can be formed in an amount sufficient to eliminate the remaining nitride film, and moreover, the platinum silicide layer 15 prevents the formation of the base region 12 and the emitter region 13. No chemical formation occurs either. Therefore, since the multilayer electrode 18 is formed on the silicon nitride film 16 which has a stable semiconductor surface and is clean, a semiconductor device having the multilayer electrode 18 with high yield, high reliability, and good adhesion is provided. can.

尚、本発明は上記実施例に限定されず、例え
ば、シリコン窒化膜16の化成は陽極酸化でもよ
く、又コレクタ電極も同一面から取り出してもよ
い。さらにPNP型でもそのバイアス電圧を本実施
例と逆にすればよい。又、白金シリサイド層15
上の窒化膜16をすべて化成する必要はなく、一
部を残しておいてもかまわない。
It should be noted that the present invention is not limited to the above-mentioned embodiment. For example, the silicon nitride film 16 may be formed by anodic oxidation, and the collector electrode may also be taken out from the same surface. Furthermore, even in the case of the PNP type, the bias voltage may be reversed to that of this embodiment. Moreover, platinum silicide layer 15
It is not necessary to chemically form all of the upper nitride film 16, and a portion may be left.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は従来の製造方法を示す工程
断面図、第4図乃至第7図は本発明の一実施例を
示す製造工程断面図である。 1,11…半導体基板、2,12…ベース領
域、3,13…エミツタ領域、4,14…シリコ
ン酸化膜、5,16…シリコン窒化膜、6,17
…化成膜、7…窒化膜残り、8…表面内部、15
…白金シリサイド層、18…チタン―白金―金の
多層電極。
1 to 3 are process sectional views showing a conventional manufacturing method, and FIGS. 4 to 7 are manufacturing process sectional views showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1, 11... Semiconductor substrate, 2, 12... Base region, 3, 13... Emitter region, 4, 14... Silicon oxide film, 5, 16... Silicon nitride film, 6, 17
...Chemical film, 7...Nitride film remaining, 8...Inside surface, 15
...Platinum silicide layer, 18...Titanium-platinum-gold multilayer electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板上のシリコン酸化膜の電極取り出
し部を開孔する工程と、該電極取り出し部の半導
体基板に白金との合金層を形成する工程と、全面
にシリコン窒化膜を形成する工程と、前記合金層
上の少なくとも一部の該シリコン窒化膜を化成し
て除去する工程と、前記合金層と電気的接続をな
する電極を形成する工程とを含むことを特徴とす
る半導体装置の製造方法。
1. A step of opening an electrode extraction portion of a silicon oxide film on a semiconductor substrate, a step of forming an alloy layer with platinum on the semiconductor substrate at the electrode extraction portion, a step of forming a silicon nitride film on the entire surface, and a step of forming a silicon nitride film on the entire surface. A method for manufacturing a semiconductor device, comprising the steps of chemically converting and removing at least a portion of the silicon nitride film on the alloy layer, and forming an electrode electrically connected to the alloy layer.
JP2753880A 1980-03-05 1980-03-05 Manufacture of semiconductor device Granted JPS56124232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2753880A JPS56124232A (en) 1980-03-05 1980-03-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2753880A JPS56124232A (en) 1980-03-05 1980-03-05 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS56124232A JPS56124232A (en) 1981-09-29
JPS6226574B2 true JPS6226574B2 (en) 1987-06-09

Family

ID=12223863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2753880A Granted JPS56124232A (en) 1980-03-05 1980-03-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56124232A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2579826B1 (en) * 1985-03-26 1988-04-29 Radiotechnique Compelec METHOD FOR PRODUCING METAL CONTACTS OF A TRANSISTOR, AND TRANSISTOR THUS OBTAINED

Also Published As

Publication number Publication date
JPS56124232A (en) 1981-09-29

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