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JPS6226601B2 - - Google Patents
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JPS6226601B2 - - Google Patents

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Publication number
JPS6226601B2
JPS6226601B2 JP15660979A JP15660979A JPS6226601B2 JP S6226601 B2 JPS6226601 B2 JP S6226601B2 JP 15660979 A JP15660979 A JP 15660979A JP 15660979 A JP15660979 A JP 15660979A JP S6226601 B2 JPS6226601 B2 JP S6226601B2
Authority
JP
Japan
Prior art keywords
output
amplitude
signal
delay time
equalizer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15660979A
Other languages
Japanese (ja)
Other versions
JPS5679512A (en
Inventor
Toshihiko Ryu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP15660979A priority Critical patent/JPS5679512A/en
Priority to US06/212,164 priority patent/US4333063A/en
Priority to CA000365984A priority patent/CA1152166A/en
Priority to EP80107562A priority patent/EP0030037B1/en
Priority to DE8080107562T priority patent/DE3070477D1/en
Publication of JPS5679512A publication Critical patent/JPS5679512A/en
Publication of JPS6226601B2 publication Critical patent/JPS6226601B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/02Details
    • H04B3/04Control of transmission; Equalising
    • H04B3/14Control of transmission; Equalising characterised by the equalising network used
    • H04B3/143Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers
    • H04B3/145Control of transmission; Equalising characterised by the equalising network used using amplitude-frequency equalisers variable equalisers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Filters And Equalizers (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】 本発明は信号伝送系において使用される可変、
振幅等化器に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable
It concerns an amplitude equalizer.

一般に伝送路の特性、歪み等は、固定されたも
のでなく、ある種の変動を伴なう場合が多い。例
えば、無線伝送路における選択性フエージングの
ために振幅歪が発生し、変動する。このような歪
を自動的に除去し、伝送される信号品質を維持す
るためには、例えば、自動振幅等化器が必要であ
る。この種の等化器は、デイジタル信号伝送方式
に多く用いられており、一般には、ベース・バン
ト帯で信号の伝送速度の逆数に等しい遅延線を数
個、直列に接続し、その各接続点(タツプ)よ
り、一定の重みづけを行つて、信号を合成し、受
信信号の波形を最適に等化するトランスバーサル
フイルタに依る等化器(「Principles of Data
Commnnications」1968,Mc Graw―Hill社発行
(第6章))が、良く知られている。しかし、この
等化器は各タツプの利得を可変して、制御を行う
ために、タツプ数の増大に伴ない、回路規模が膨
大なものとなることや、遅延量をデータの伝送速
度の逆数と同一に選定しなければならない。従つ
て、伝送速度がこの遅延量の逆数に近い方式に対
しては、そのままでは適用不可能となり、汎用性
を欠いていた。
Generally, the characteristics, distortion, etc. of a transmission path are not fixed and often involve some kind of variation. For example, amplitude distortion occurs and fluctuates due to selective fading in a wireless transmission path. For example, an automatic amplitude equalizer is required to automatically remove such distortion and maintain the transmitted signal quality. This type of equalizer is often used in digital signal transmission systems, and generally consists of several delay lines connected in series that are equal to the reciprocal of the signal transmission speed in the baseband band, and each connection point (tap), the equalizer (Principles of Data
``Communications'' 1968, published by Mc Graw-Hill (Chapter 6)) is well known. However, since this equalizer performs control by varying the gain of each tap, as the number of taps increases, the circuit size becomes enormous, and the amount of delay is the reciprocal of the data transmission speed. The same selection must be made. Therefore, it cannot be applied as is to a system in which the transmission speed is close to the reciprocal of this delay amount, and it lacks versatility.

本発明の目的は、これらの欠点を除去し、回路
規模が小さく伝送速度によらない無遅延歪振幅等
化器を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate these drawbacks and provide a delay-free distortion amplitude equalizer that has a small circuit scale and is independent of transmission speed.

以下、図面を参照しながら本発明を詳細に説明
する。
Hereinafter, the present invention will be explained in detail with reference to the drawings.

第1図は本発明による振幅等化回路の一実施例
のブロツク図である。第1図において、1,3は
信号を分岐する回路、4,7は信号を合成する回
路、2,5は同一の遅延量を持つ遅延回路、6は
可変減衰回路である。ここで、入力端子101に
供給される入力信号をejtとし、遅延回路2,
5での遅延時間をτ.回路6での減衰量をα、接
続点104および105における信号をそれぞれ
A1およびB1とすれば A1=α{ejt+ej(t-2)} …(1) B1=ej(t-) …(2) と表わせるから、接続点106における信号は C1=A1+B1=ej(t-) ×{1+α(ejt+e-jt)} =ejt×e-jt{1+2αcosωt} …(3) となる。
FIG. 1 is a block diagram of one embodiment of an amplitude equalization circuit according to the present invention. In FIG. 1, 1 and 3 are signal branching circuits, 4 and 7 are signal combining circuits, 2 and 5 are delay circuits having the same amount of delay, and 6 is a variable attenuation circuit. Here, the input signal supplied to the input terminal 101 is e jt , and the delay circuit 2,
The delay time at 5 is τ. α is the attenuation amount in circuit 6, and the signals at connection points 104 and 105 are respectively
If A 1 and B 1 , then A 1 = α{e jt + e j(t-2) } …(1) B 1 = e j(t-) …(2) , the signal at the connection point 106 is C 1 =A 1 +B 1 =e j(t-) × {1+α(e jt +e -jt )} = e jt ×e -jt { 1+2αcosωt} …(3).

従つて、入力から出力までの伝送特性(伝達関
数)T1(ω)は T1(ω)=(1+2αcosωτ)e-j〓〓…(4) となる。ここで、振幅、位相および遅延時間の特
性関数をそれぞれS1(ω),θ(ω)およびD1
(ω)とすれば T1(ω)=S1(ω)・ej1() …(5) S1(ω)=1+2αcosωτ …(6) θ(ω)=−ωτ …(7) D1(ω)=−αθ(ω)/αω=τ(一定) …(8) となり、αを変化させればS1(ω)は変化する
が、θ(ω)はα,ωによらないので、D1
(ω)は常に一定となり遅延歪を生じさせない。
換言すれば、全く遅延歪を発生させずに、振幅対
周波数特性のみを等化することができる。設計例
として、周波数から)の周
波数領域(帯域)で使用可能な振幅等化器を設計
する場合、正の1次傾斜を発生させる等化器とし
ては、τ=1/2、負の1次傾斜を発生さ
せる等化器としては、τ=1/2、正の2
次曲率分を発生させる等化器としては、τ
1/()となる3種類の等化器を設計
すれば良い。
Therefore, the transmission characteristic (transfer function) T 1 (ω) from the input to the output is T 1 (ω)=(1+2αcosωτ)e −j 〓〓 (4). Here, the characteristic functions of amplitude, phase and delay time are S 1 (ω), θ 1 (ω) and D 1
(ω), then T 1 (ω)=S 1 (ω)・e j1() …(5) S 1 (ω)=1+2αcosωτ …(6) θ 1 (ω)=−ωτ …( 7) D 1 (ω) = −αθ 1 (ω) / αω = τ (constant) ...(8) Therefore, if α changes, S 1 (ω) will change, but θ 1 (ω) will change to α , does not depend on ω, so D 1
(ω) is always constant and does not cause delay distortion.
In other words, only the amplitude versus frequency characteristics can be equalized without causing any delay distortion. As a design example, when designing an amplitude equalizer that can be used in the frequency domain (band) of frequencies 1 to 2 ( 2 > 1 ), an equalizer that generates a positive first-order slope should have τ 1 = 1 /2 1 , as an equalizer that generates a negative first-order slope, τ 2 = 1/2 2 , positive 2
As an equalizer that generates the next curvature component, τ 3 =
It is sufficient to design three types of equalizers that are 1/( 1 + 2 ).

第2図は、減衰率αを変化させた場合のS1
(ω)の動きを示す図である。0〜πおよびπ〜
2πの領域ではそれぞれ負および正の1次傾斜、
−π/2〜π/2およびπ/2〜3π/2の領域
ではそれぞれ正および負の2次、若しくは高次曲
率等化装置として、使用可能な範囲である。図か
ら明らかなように、αを可変するだけで、本発明
は自動振幅等化回路に容易に拡張できる。
Figure 2 shows S 1 when changing the attenuation rate α.
It is a figure showing the movement of (ω). 0~π and π~
negative and positive first-order slopes in the 2π region, respectively;
The ranges of -π/2 to π/2 and π/2 to 3π/2 are ranges that can be used as positive and negative second-order or high-order curvature equalizers, respectively. As is clear from the figure, the present invention can be easily extended to an automatic amplitude equalization circuit by simply varying α.

第3図はその実施例である。21,22および
23は、それぞれ第1図と同じ構成であり、τを
選定することにより、正の1次傾斜、負の1次傾
斜および正の2次曲率の振幅等化器として、設定
されたものである。8はAGC増幅器、9は受信
した信号のスペクトラムの形を検出することによ
り、伝送歪を検出し、等化器21〜23を制御す
る回路、201は入力端子、202は出力端子で
ある。
FIG. 3 shows an example of this. 21, 22, and 23 each have the same configuration as in FIG. 1, and by selecting τ, they can be set as amplitude equalizers for a positive first-order slope, a negative first-order slope, and a positive second-order curvature. It is something that 8 is an AGC amplifier; 9 is a circuit that detects transmission distortion by detecting the shape of the spectrum of the received signal and controls the equalizers 21 to 23; 201 is an input terminal; and 202 is an output terminal.

第4図は、制御回路9の具体的な回路のブロツ
ク図である。10,11および12はそれぞれ中
心周波数を(),(),
とする狭帯域波器(ここでは信号帯域の中
心周波数、は適当な周波数)、13,14お
よび15はそれぞれレベル検波器、16,17は
差動増幅器、18〜20は抵抗器である。
FIG. 4 is a block diagram of a specific circuit of the control circuit 9. 10, 11, and 12 have center frequencies of ( 0 + 1 ), ( 0 - 1 ), and 0, respectively.
(where 0 is the center frequency of the signal band and 1 is an appropriate frequency), 13, 14 and 15 are level detectors, 16 and 17 are differential amplifiers, and 18 to 20 are resistors. be.

第5図は、波器13,14,15の振幅対周
波数特性である。ただしBは信号帯域幅である。
差動増幅器16はレベル検出器13,14の出力
すなわち周波数の低域側と高域側の信号成分
(信号電力)を比較して、その差を取り出し、1
次傾斜分とその極性に応じて、出力Xを出力す
る。一方、差動増幅器17は、レベル検出器1
3,14の出力の平均値と、レベル検出器15の
出力、すなわち周波数近傍の信号成分を比較
し、その差を取り出すことにより、2次、高次の
曲率分とその極性に応じて、出力Yを出力する。
なお、1次傾斜分だけを等化する場合は波器1
2、検出器15、差動増幅器17は必要でなく、
又、2次、高次の曲率分のみを等化する場合は、
差動増幅器16は必要ではない。差動増幅器1
6,17の出力信号X,Yは選択的にそれぞれ、
制御すべき可変減衰器(第1図)に供給される。
FIG. 5 shows the amplitude versus frequency characteristics of wave generators 13, 14, and 15. However, B is the signal bandwidth.
The differential amplifier 16 compares the outputs of the level detectors 13 and 14, that is, the signal components (signal power) on the low frequency side and the high frequency side of frequency 0 , extracts the difference, and outputs 1
An output X is output according to the next slope and its polarity. On the other hand, the differential amplifier 17 is connected to the level detector 1
By comparing the average value of the outputs of 3 and 14 with the output of the level detector 15, that is, the signal component near frequency 0 , and extracting the difference, depending on the second-order and higher-order curvature components and their polarities, Outputs output Y.
In addition, when equalizing only the first-order slope, use wave generator 1.
2. Detector 15 and differential amplifier 17 are not required;
Also, when equalizing only the second-order and higher-order curvatures,
Differential amplifier 16 is not required. Differential amplifier 1
The output signals X and Y of 6 and 17 are selectively, respectively,
A variable attenuator (FIG. 1) to be controlled is supplied.

以上、説明したように、本発明によれば、遅延
時間(τ)を適当に選ぶことにより、減衰率
(α)を可変すれば、所要の周波数領域と最大等
化振幅を任意に設定し得る振幅等化回路が得られ
る。また、必要に応じて等化領域、等化特性を自
動的に選択できる自動振幅等化装置をも得ること
ができる。しかも、全帯域で遅延平担であるため
に、2次、高次の曲率を等化するのにも、適して
いる。
As explained above, according to the present invention, by appropriately selecting the delay time (τ) and varying the attenuation rate (α), the required frequency range and maximum equalized amplitude can be arbitrarily set. An amplitude equalization circuit is obtained. Furthermore, it is also possible to obtain an automatic amplitude equalization device that can automatically select an equalization region and equalization characteristics as necessary. Moreover, since the delay is flattened over the entire band, it is also suitable for equalizing second-order and higher-order curvatures.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による可変等化器部の実施例の
ブロツク図、第2図は遅延量を一定として、減衰
率を変化させた時の振幅特性図、第3図は、本発
明による自動等化装置の実施例のブロツク図、第
4図は、第3図における制御回路の一実施例のブ
ロツク図、第5図は、第4図における波器10
〜12の特性図である。 なお、図において、1,3は信号分岐回路、
4,7は信号合成回路、2,5は遅延回路、6は
可変減衰器、8は自動利得制御増幅器、9は制御
回路、10〜12は波器、13〜15はレベル
検出回路、16,17は差動増幅器、18〜20
は抵抗器、21〜23は等化器である。
FIG. 1 is a block diagram of an embodiment of the variable equalizer section according to the present invention, FIG. 2 is an amplitude characteristic diagram when the delay amount is constant and the attenuation rate is varied, and FIG. 3 is an automatic equalizer according to the present invention. 4 is a block diagram of an embodiment of the equalizer, FIG. 4 is a block diagram of an embodiment of the control circuit in FIG. 3, and FIG. 5 is a block diagram of an embodiment of the control circuit in FIG.
It is a characteristic diagram of ~12. In addition, in the figure, 1 and 3 are signal branch circuits,
4 and 7 are signal synthesis circuits, 2 and 5 are delay circuits, 6 is a variable attenuator, 8 is an automatic gain control amplifier, 9 is a control circuit, 10 to 12 are wave generators, 13 to 15 are level detection circuits, 16, 17 is a differential amplifier, 18-20
is a resistor, and 21 to 23 are equalizers.

Claims (1)

【特許請求の範囲】 1 一定の周波数帯域内である振幅歪特性を有す
る信号を等化する可変振幅等化器において、前記
信号を2分岐する第1の手段と、前記第1の手段
の一方の出力に接続され前記周波数帯域で決まる
遅延時間を有する第2の手段と、前記第2の手段
の出力信号を2分岐する第3の手段と、前記第3
の手段の一方の出力に接続され前記遅延時間と同
じ遅延時間を有する第4の手段と、前記第1の手
段の他方の出力と前記第4の手段の出力とを合成
する第5の手段と、前記第5の手段の出力を可変
減衰する第6の手段と、前記第3の手段の他方の
出力と前記第6の手段の出力を合成し等化された
信号を発生する第7の手段とを含むことを特徴と
する振幅等化器。 2 一定の周波数帯域内である振幅歪特性を有す
る信号の供給を受ける入力信号端子と、出力端子
と、前記振幅歪特性を等化する振幅対周波数特性
を有する振幅等化器において、第1および第2の
振幅等化手段を前記入力信号端子と前記出力信号
端子との間に直列に設け、前記振幅等化手段の
各々を信号を2分岐する第1の手段と、前記第1
の手段の一方の出力に接続され前記周波数帯域で
決まる遅延時間を有する第2の手段と、前記第2
の手段の出力を2分岐する第3の手段と、前記第
3の手段の一方の出力に接続され前記遅延時間と
同じ遅延時間を有する第4の手段と、前記第1の
手段の他方の出力と前記第4の手段の出力とを合
成する第5の手段と、前記第5の手段の出力を可
変減衰する第6の手段と、前記第3の手段の他方
の出力と前記第6の手段の出力を合成しこの振幅
等化手段の出力とする第7の手段とで構成し、最
終段の前記振幅等化手段の出力に接続され前記信
号の電力スペクトラムの形状により前記振幅歪特
性の極性および振幅を検出し前記第6の手段を制
御する第8の手段を含むことを特徴とする振幅等
化器。
[Scope of Claims] 1. A variable amplitude equalizer that equalizes a signal having amplitude distortion characteristics within a certain frequency band, comprising a first means for branching the signal into two, and one of the first means. a second means connected to the output of the second means and having a delay time determined by the frequency band; a third means for branching the output signal of the second means into two;
a fourth means connected to one output of the means and having the same delay time as the delay time; and a fifth means for synthesizing the other output of the first means and the output of the fourth means. , a sixth means for variably attenuating the output of the fifth means, and a seventh means for synthesizing the other output of the third means and the output of the sixth means to generate an equalized signal. An amplitude equalizer comprising: 2. An amplitude equalizer having an input signal terminal that receives a signal having an amplitude distortion characteristic within a certain frequency band, an output terminal, and an amplitude versus frequency characteristic that equalizes the amplitude distortion characteristic; A second amplitude equalization means is provided in series between the input signal terminal and the output signal terminal, and each of the amplitude equalization means is connected to a first means for branching the signal into two;
a second means connected to one output of the means and having a delay time determined by the frequency band;
a third means for branching the output of the means into two; a fourth means connected to one output of the third means and having a delay time equal to the delay time; and the other output of the first means. and the output of the fourth means, a sixth means for variably attenuating the output of the fifth means, and the other output of the third means and the sixth means. and a seventh means for synthesizing the outputs of the amplitude equalizing means and outputting the output of the amplitude equalizing means, and the seventh means is connected to the output of the amplitude equalizing means at the final stage, and is connected to the output of the amplitude equalizing means at the final stage, and is configured to determine the polarity of the amplitude distortion characteristic according to the shape of the power spectrum of the signal. and eighth means for detecting the amplitude and controlling the sixth means.
JP15660979A 1979-12-03 1979-12-03 Amplitude equalizer Granted JPS5679512A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP15660979A JPS5679512A (en) 1979-12-03 1979-12-03 Amplitude equalizer
US06/212,164 US4333063A (en) 1979-12-03 1980-12-02 Amplitude equalizer
CA000365984A CA1152166A (en) 1979-12-03 1980-12-02 Amplitude equalizer
EP80107562A EP0030037B1 (en) 1979-12-03 1980-12-03 Amplitude equalizer, particularly for use in a signal transmission system
DE8080107562T DE3070477D1 (en) 1979-12-03 1980-12-03 Amplitude equalizer, particularly for use in a signal transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15660979A JPS5679512A (en) 1979-12-03 1979-12-03 Amplitude equalizer

Publications (2)

Publication Number Publication Date
JPS5679512A JPS5679512A (en) 1981-06-30
JPS6226601B2 true JPS6226601B2 (en) 1987-06-10

Family

ID=15631471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15660979A Granted JPS5679512A (en) 1979-12-03 1979-12-03 Amplitude equalizer

Country Status (1)

Country Link
JP (1) JPS5679512A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0681077B2 (en) * 1984-07-27 1994-10-12 松下電器産業株式会社 Signal correction processor

Also Published As

Publication number Publication date
JPS5679512A (en) 1981-06-30

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