JPS6227734B2 - - Google Patents
Info
- Publication number
- JPS6227734B2 JPS6227734B2 JP56044556A JP4455681A JPS6227734B2 JP S6227734 B2 JPS6227734 B2 JP S6227734B2 JP 56044556 A JP56044556 A JP 56044556A JP 4455681 A JP4455681 A JP 4455681A JP S6227734 B2 JPS6227734 B2 JP S6227734B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- silicon nitride
- nitride film
- buffer layer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の構造、特にボンデイング
電極下がボンデイング工程に破壊されることのな
い半導体装置の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a semiconductor device, and particularly to a structure of a semiconductor device in which the area under a bonding electrode is not destroyed during a bonding process.
最近の高周波用バイポーラトランジスタの素子
パターンは、性能指数を上げる為にきわめて微細
化されている。これに伴ないエミツタ、ベースコ
ンタクト窓を覆う金属電極の幅が狭くなり、耐水
性が著しく悪くなり、直流増幅率及び雑音指数を
悪くしている。この耐水性の悪化を補償するた
め、陽極酸化法を用いてペレツト全面を窒化シリ
コン膜で覆う構造も採用されている。 The element patterns of recent high-frequency bipolar transistors have been extremely miniaturized to increase the figure of merit. As a result, the width of the metal electrode covering the emitter and base contact windows has become narrower, resulting in significantly poor water resistance and poor DC amplification and noise figure. In order to compensate for this deterioration in water resistance, a structure has been adopted in which the entire surface of the pellet is covered with a silicon nitride film using an anodic oxidation method.
しかし組立工程においては、省力化が進み、ボ
ンデイングは高速化されており、このペレツト構
造ではボンデイング中にボンデイング電極下のシ
リコンが衝撃力により剥離するというような不具
合が生じた。 However, in the assembly process, labor savings have progressed and bonding has become faster, but this pellet structure has caused problems such as the silicon under the bonding electrode peeling off due to impact force during bonding.
本発明の目的は高速ボンデイングに適した高周
波用トランジスタの構造を提供するものである。 An object of the present invention is to provide a high-frequency transistor structure suitable for high-speed bonding.
本発明によれば、電極パツドと半導体基板との
間に比較的軟かい絶縁物からなる緩衝層を設けた
半導体装置を得る。 According to the present invention, a semiconductor device is obtained in which a buffer layer made of a relatively soft insulator is provided between an electrode pad and a semiconductor substrate.
以下に、図面を用いて、この発明をより詳細に
説明する。第1図a〜cは従来の半導体装置とそ
の欠点を説明するもので、第1図aは半導体素子
が不純物拡散により形成された半導体基板1の表
面酸化膜2上に陽極酸化法により全面に300Å程
度の厚さの窒化シリコン膜3を形成し、その後ボ
ンデイング電極4を形成した従来の半導体装置の
断面図である。第1図bはこのボンデイング電極
4に金線5を用いてボンデイングすることにより
ボンデイング電極4、窒化シリコン膜3、酸化シ
リコン膜2、半導体基板1にボンデイング衝撃力
6が加わり、歪み6′がこれらに入ることを表わ
した部分断面図である。このようなボンデイング
衝撃力6によつて、窒化シリコン膜3、酸化シリ
コン膜2、半導体基板1は第1図cに示すように
剥離し、穴7が形成される。このような剥離が起
こる原因としては、窒化シリコン膜3が非常にう
すい為にボンデイング衝撃力6を緩衝する力が非
常に弱く、ストレスが直接ボンデイング電極4の
下に集中するからであると推定される。 The present invention will be explained in more detail below using the drawings. Figures 1a to 1c illustrate conventional semiconductor devices and their drawbacks. Figure 1a shows a semiconductor element formed by anodizing the entire surface of a surface oxide film 2 of a semiconductor substrate 1 formed by impurity diffusion. 1 is a cross-sectional view of a conventional semiconductor device in which a silicon nitride film 3 with a thickness of about 300 Å is formed, and then a bonding electrode 4 is formed. FIG. 1b shows that by bonding the bonding electrode 4 with a gold wire 5, a bonding impact force 6 is applied to the bonding electrode 4, the silicon nitride film 3, the silicon oxide film 2, and the semiconductor substrate 1, and a strain 6' is caused to these. FIG. Due to such a bonding impact force 6, the silicon nitride film 3, the silicon oxide film 2, and the semiconductor substrate 1 are separated as shown in FIG. 1c, and a hole 7 is formed. It is presumed that the reason why such peeling occurs is that the silicon nitride film 3 is very thin and has a very weak ability to buffer the bonding impact force 6, and the stress is directly concentrated under the bonding electrode 4. Ru.
本発明の一実施例によれば、第2図に示すよう
に、不純物拡散によつて半導体素子が形成された
シリコン基板11上を酸化シリコン膜12でおお
い、拡散領域からの電極取出部には開孔を設け、
ここから金属の配線電極15を導出するととも
に、酸化シリコン膜12上でボンデイング電極1
4を設ける部分には厚さ1000〜1500Åの窒化シリ
コン膜18を設けさらにその上に全面に窒化シリ
コン膜13を設け、しかる後に例えば金やアルミ
ニウムのボンデイング電極14が設けられる。 According to one embodiment of the present invention, as shown in FIG. 2, a silicon oxide film 12 is covered on a silicon substrate 11 on which a semiconductor element is formed by impurity diffusion, and an electrode extraction portion from a diffusion region is covered with a silicon oxide film 12. Provide an opening,
A metal wiring electrode 15 is led out from here, and a bonding electrode 1 is formed on the silicon oxide film 12.
A silicon nitride film 18 with a thickness of 1,000 to 1,500 Å is provided on the portion where 4 is provided, and a silicon nitride film 13 is provided on the entire surface, and then a bonding electrode 14 of, for example, gold or aluminum is provided.
このボンデイング電極14に金細線をボンデイ
ングすると、ボンデイング衝撃力は比較的軟かく
かつ厚い窒化シリコン膜18で緩衝されて下の酸
化シリコン膜12やシリコン基板11に加わるこ
とがない。このように、第2図に示す構造の半導
体装置によれば、緩衝層としての窒化シリコン膜
18によつて、剥離不良率が5%から0.1%迄に
改善することが出来る。したがつて、やむを得
ず、ボンデイング衝撃力を大きくしなければなら
ないような場合にも、緩衝層を設けることによつ
て安全で確実なボンデイング作業が行えることに
なる。 When a thin gold wire is bonded to this bonding electrode 14, the bonding impact force is buffered by the relatively soft and thick silicon nitride film 18 and is not applied to the underlying silicon oxide film 12 or silicon substrate 11. As described above, according to the semiconductor device having the structure shown in FIG. 2, the peeling defect rate can be improved from 5% to 0.1% by using the silicon nitride film 18 as a buffer layer. Therefore, even if it is unavoidable to increase the bonding impact force, by providing a buffer layer, safe and reliable bonding work can be performed.
なお、緩衝層としての窒化シリコン膜18は、
少なくともボンデイング電極14の下にあれば、
他の部分にあつても良いが、酸化シリコン膜12
の開口周辺にまで設けると、絶縁膜の全体の厚さ
が厚くなりすぎ、配線金属を断線なしに取り出す
ことが困難になる。又金属は比較的軟かいので緩
衝層としては適しているが、浮遊容量が大きくな
るので、使用に際しては注意を要する。 Note that the silicon nitride film 18 as a buffer layer is
If it is at least under the bonding electrode 14,
Although it may be present in other parts, the silicon oxide film 12
If the insulating film is provided around the opening, the overall thickness of the insulating film becomes too thick, making it difficult to take out the wiring metal without breaking the wire. Also, since metal is relatively soft, it is suitable as a buffer layer, but it has a large stray capacitance, so care must be taken when using it.
第1図a〜cは従来の半導体装置の構造および
剥離の様子を示した断面図である。第2図は緩衝
層をもうけた本発明の一実施例を示す断面図であ
る。
1,11……シリコン基板、2,12……酸化
シリコン膜、3,13……窒化シリコン膜、4,
14……ボンデイング電極、5……ボンデイング
ワイヤー、6……ボンデイング衝撃力、6′……
ボンデイング歪み、7……剥離した部分、15…
…配線電極、18……緩衝層(窒化シリコン
膜)。
FIGS. 1a to 1c are cross-sectional views showing the structure and delamination of a conventional semiconductor device. FIG. 2 is a sectional view showing an embodiment of the present invention with a buffer layer. 1, 11... Silicon substrate, 2, 12... Silicon oxide film, 3, 13... Silicon nitride film, 4,
14... Bonding electrode, 5... Bonding wire, 6... Bonding impact force, 6'...
Bonding distortion, 7...Peeled part, 15...
...Wiring electrode, 18...Buffer layer (silicon nitride film).
Claims (1)
る絶縁層と、この絶縁層上に選択的に形成され無
機絶縁材からなる緩衝層と、この緩衝層および前
記絶縁層の表面を覆い前記コンタクトホールまで
延在形成されたシリコン窒化膜と、前記緩衝層上
を覆うシリコン窒化膜上に形成されたボンデイン
グ電極と、前記コンタクトホールを介して前記半
導体基板の一部に接触し前記シリコン窒化膜上に
延在形成された電極配線層とを含む半導体装置。1. An insulating layer covering a semiconductor substrate and having a contact hole; a buffer layer made of an inorganic insulating material selectively formed on the insulating layer; and a buffer layer covering the surface of the buffer layer and the insulating layer and extending to the contact hole. a silicon nitride film formed, a bonding electrode formed on the silicon nitride film covering the buffer layer, and a bonding electrode formed extending on the silicon nitride film and contacting a part of the semiconductor substrate through the contact hole. A semiconductor device including an electrode wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56044556A JPS57159035A (en) | 1981-03-26 | 1981-03-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56044556A JPS57159035A (en) | 1981-03-26 | 1981-03-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57159035A JPS57159035A (en) | 1982-10-01 |
| JPS6227734B2 true JPS6227734B2 (en) | 1987-06-16 |
Family
ID=12694768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56044556A Granted JPS57159035A (en) | 1981-03-26 | 1981-03-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57159035A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5886733A (en) * | 1981-11-18 | 1983-05-24 | Nec Corp | Semiconductor device |
| JPS6237934U (en) * | 1985-08-27 | 1987-03-06 | ||
| JP2527457B2 (en) * | 1988-02-29 | 1996-08-21 | シャープ株式会社 | Electrode structure of semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5239378A (en) * | 1975-09-23 | 1977-03-26 | Seiko Epson Corp | Silicon-gated mos type semiconductor device |
| JPS54107260A (en) * | 1978-02-10 | 1979-08-22 | Nec Corp | Semiconductor device |
| JPS56105670A (en) * | 1980-01-28 | 1981-08-22 | Mitsubishi Electric Corp | Semiconductor device |
-
1981
- 1981-03-26 JP JP56044556A patent/JPS57159035A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57159035A (en) | 1982-10-01 |
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