JPS6228588B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device in which the base and emitter portions of a transistor are separated from each other by selective oxidation of polycrystalline silicon. It is something.

The semiconductor device of the above method and its manufacturing method are
IEEE, JOURNAL OF SOLID STATE
Published by CIRCUITS, 1978, Oct. Vol. Sc-13, No. 5. This method will be explained below with reference to the drawings.

In FIG. 1, for example, an N-type silicon substrate 1
After forming a silicon dioxide insulating film 2 on the surface of the silicon dioxide insulating film 2 and forming windows 2a and 2b in a portion thereof, a P-type base region 3 is formed by diffusing P-type impurities.

In the manufacturing process related to FIG. 2, a polycrystalline silicon (hereinafter referred to as polysilicon) film 4 is deposited on the entire upper surface of the substrate 1, and a silicon nitride film 5 is grown thereon.

In the manufacturing process related to FIG. 3, windows 5a and 5b are selectively formed in the silicon nitride film 5, and then polysilicon exposed within the windows is selectively oxidized to form a silicon oxide film 6a. , 6b.
At this time, the surface of the silicon substrate 1 is also partially oxidized.

In the manufacturing process related to FIG. 4, the silicon nitride film 5 is selectively left, and N-type impurities are injected into the silicon substrate through the removed polysilicon film using phosphosilicate glass (not shown) or by ion implantation. Dope the surface of 1. As a result, an N-type emitter region 7 and collector region 8 are formed.

In the manufacturing process related to FIG. 5, the remaining silicon nitride film 5 is removed and electrode patterns 9a, 9b, 9c made of silicon-platinum alloy or the like are provided to complete a semiconductor device including a transistor.

The above method has the advantage that the emitter can be positioned by selective oxidation of polysilicon. However, the conventional method described above has drawbacks as described below. This point will be explained based on the schematic diagram of the transistor shown in FIG. The base region 3 of the transistor consists of a portion called an internal base directly below the emitter region 7, and a portion called an external base below the base contact in contact with the electrode. The main portion of the transistor's current 10 passes from the emitter region 7 directly below the internal base and is collected by the collector region 8.
On the other hand, a small portion 11 of the current passes through the external base and flows to the base electrode. External base passing current 11
The ratio of the current passing through the internal base to the current passing through the internal base becomes the amplification factor, and a resistor 12 can be assumed at the external base. Incidentally, in order to increase the speed of a transistor, it is necessary to make the width of the internal base layer, that is, the distance through which current passes, as small as possible and/or to reduce the resistance 12 of the external base. Furthermore, the smaller the base width, the higher the cutoff frequency ( _T ) of the transistor becomes. As mentioned above, it is necessary to lower the resistance of the external base in order to increase the speed of the transistor or improve _{the T} , but since the internal base and external base are made at the same time in the process shown in Figure 2, the base region is Conventional transistors suffer from the inability to reduce base resistance. Furthermore, in order to increase the speed of transistors, it is necessary to reduce the width of the internal base layer, but when diffusing the emitter region into the once formed base region 3 (Fig. 4), It is extremely difficult to adjust the width to a small value.

^According to Japanese Unexamined Patent Publication No. 54-7879, especially FIG. A portion 15 of the type region forms a rectifying barrier with the N ⁺ type collector contact region, and the other portion 14 extends on the surface of the N type semiconductor substrate 11, and the silicon oxide film 12'' forms the P type region 14. , 15 as an insulator, and the portion 15 has a lower impurity concentration than the other portion 14. When the semiconductor device is embodied as a transistor, One part of the base (forming the PN rectifying junction) is the internal base and the other part is the external base.Generally, to improve the performance of a transistor, the width of the internal base is reduced or the amount of impurities is increased. This causes an emitter-collector short circuit, but in the semiconductor device of the above publication, the emitter-collector short circuit occurs because the external base contains a high concentration of impurities.
Collector short circuit does not occur. However, this device has the drawbacks of a complicated manufacturing process and a deep internal base depth.

The inventor of the present invention has focused on the fact that such drawbacks are caused by the structure of conventional semiconductor devices, and has conducted research with the aim of providing a method for manufacturing semiconductor devices with a novel structure.

Furthermore, the drawbacks of the conventional transistor manufacturing method shown in FIGS. 1 to 6 are due to the manufacturing process shown in FIG. 3, in which the polysilicon film 4 is selectively oxidized after the base region 3 is diffused. To,
Boron, which is a P-type impurity, diffuses from the base region 3 into the silicon oxide (SiO ₂ ) film 6a, and as a result, the surface resistance of the base region 3 and the base resistance 12 (sixth
In the course of the above research, the present inventors discovered that (Fig.) increases.

Furthermore, the method described in the above-mentioned publication is also basically subject to this drawback. By the way, when the base region 3 is deep, the increase in base resistance is not significant, but on the other hand, the speed increase of the transistor is hindered. The present invention solves these problems and also provides a method for preventing impurity diffusion during the selective oxidation step of polysilicon.

The method according to the present invention includes a first region having an opposite conductivity type formed on one surface of a semiconductor substrate having one conductivity type, and a second region having the one conductivity type, and the first region is formed on a surface of a semiconductor substrate having one conductivity type. In order to manufacture a semiconductor device consisting of a shallow first portion forming a rectification barrier with the second region below two regions, a deep second portion extending to the surface of the semiconductor substrate, and a shallow third portion,
depositing a conductive material on the surface of the semiconductor substrate; implanting ions at a high concentration from selected portions of the conductive material film using a mask to form a second portion of the first region; After converting the conductive material in the selected portion into an insulator using a mask, ions are implanted at a low concentration through the conductive material in the non-selected portion to form a first portion and a third portion of the second region;
Then, ion implantation is performed through a part of the non-selected portion to form the second region.

In the method of the present invention, the second part is created by ion implantation using a mask, and the conductive material is selectively made into an insulator by oxidation or nitridation using this mask, so the mask process is only one time. Furthermore, since ions are implanted into the internal base (first portion) using this insulating film as a mask, self-alignment of the base and emitter is possible.

Hereinafter, the present invention will be explained in more detail with reference to specific examples shown in the drawings.

Silicon is grown in a vapor phase on the entire upper surface of the N-type silicon substrate 1 (FIG. 7) selectively exposed by the SiO ₂ film 2 to form a polysilicon film 4 with a thickness of 0.1 to 0.3 microns. on polysilicon film 4
Using the nitride film 5 as a mask, it is grown to a thickness of 1000 to 2000 microns by a conventional CVD method using SiH ₄ +NH ₃ gas or the like. Next, a window 5a is provided in the nitride film 5 at a portion separating the base contact portion from the emitter contact portion. Subsequently, B ⁺ ions are implanted into the silicon substrate 1 at an energy of 40 to 60 keV using the nitride film 5 as a mask. That is, the window 5a provided to separate the base contact portion from the emitter contact automatically defines the position of the ion implantation region 20. This area 20 serves as an external base (second part of the base). At the same time as the window 5a for base-emitter isolation is formed, a window 5b for emitter-collector contact isolation is also formed.

After the ion implantation, selective oxidation of polysilicon is performed through the windows 5a and 5b, using the nitride film 5 at the time of ion implantation as a mask. Oxidation may be performed in an oxidizing atmosphere at 1000 to 1100°C for 60 to 150 minutes. FIG. 8 shows a state in which the nitride film 5 is removed after performing such selective oxidation.

Since the external base 20 has been formed by ion implantation through the above steps, the upper surface of the polysilicon film 4 is first covered with a photoresist 21 in order to selectively form the external base on the silicon substrate.
This photoresist 21 is used to mask the silicon substrate where the collector will be formed later.
Dimensional accuracy does not need to be high. Photoresist 21
(FIG. 9) and using the SiO ₂ film 6a as a mask, B ⁺ ions are implanted shallowly and thinly. That is, the energy of the ion beam is adjusted to 30 to 40 keV so that the implantation depth into the silicon substrate becomes shallow, and the dose is adjusted to 10 ¹³ to 10 ¹⁴ /cm ² to implant boron in the silicon substrate region 22. Ion implantation is performed under conditions such that the concentration is lower than that of the external base 20. This results in a very thin internal base (first part 22 of the base) and third part 27 as shown in FIG. Note that, since the heat treatment for forming the insulator has been completed before this step, the impurity diffusion in the internal base will not cause it to become deeper.

Through the above steps, the base regions 20, 22, 27
is made, and then the process of making emitters and collectors is carried out as shown in FIG. That is, the photoresist 21 is removed leaving only a portion, and the remaining photoresist 21 is used as a mask to apply As or P.
Perform ion implantation. The energy of the ion beam is 40 to 60 keV, and the dose is 10 ¹⁵ to 10 ¹⁶ /cm ²
is preferred. As a result of the ion implantation, an emitter region 7 and a collector region 8 are formed.

Finally, the photoresist 21 is removed again, and aluminum is deposited on the entire upper part of the silicon substrate.
This is patterned into electrode patterns 9a and 9b.
and 9c (Fig. 11). Note that the electrode pattern may be formed by vapor depositing platinum on polysilicon.

Semiconductor device manufactured as above (11th
Figure) shows that the thickness of the first portion 22 and third portion 27 of the first region (base region) having opposite conductivity types is
It can be made extremely thin, less than 0.3 microns. in general,
In order to make the emitter shallower, the base had to be made shallower, and as a result, if an attempt was made to increase the impurity concentration in the base, there was a risk of an emitter-collector short circuit. The present invention does not take measures to make the emitter and base shallow as a whole, but deepens the second part (external base) of the base and makes the first part (internal base) and third part shallow, so that One of the features is that the SiO ₂ film 6a is formed in advance so as to be located at . In other words, the SiO ₂ film 6a
is first formed, and then the first portion 22 and the third portion 27 are formed.
Since these parts are formed by self-alignment, these parts can be made thinner. As mentioned above, the first part (internal base) has a relatively lower amount of impurities than the second part (external base), so even if it is thin, there is less risk of collector-emitter short circuit, and the thinness increases the speed of the transistor. can be achieved. The width (thickness in the vertical direction) of such a first portion (internal base) is less than or equal to 0.3 microns, preferably less than or equal to 0.2 microns.

If the external base (the first part of the base) is doped with a high concentration of impurities as described above, the base resistance can be lowered, and the thickness of the internal base (the second part) is not particularly critical. ) will be thicker. The impurity concentration is 10 ¹⁹ to 10 ²⁰ /cm ³ in the external base (second part) and 10 ¹⁸ to 10 ¹⁹ /cm ³ in the internal base (first part) and third part.
It is preferable to adjust within the range of . As a result,
The base resistance of the transistor of the present invention is 50-100Ω
decreases to

According to the semiconductor device as described above, the cutoff frequency ( _T ) is increased to 4 GHz or more compared to the conventional 1.5 to 3 GHz, and as a result, the speed can be increased.

[Brief explanation of the drawing]

1 to 5 are cross-sectional views of a semiconductor device for explaining the conventional method, FIG. 6 is a schematic diagram of a transistor, and FIGS. 7 to 11 are for explaining specific examples of the method according to the present invention. FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1... Semiconductor substrate, 2... Insulating film, 4... Conductive film,
5... Nitride film, 6... Insulating material, 9... Electrode pattern, 10, 11... Current, 12... Base resistance,
20... Second part (external base) of first region (base), 22... First part (internal base), 27... Third part
part.

Claims (1)

[Claims] 1 A first region having an opposite conductivity type formed on one surface of a semiconductor substrate having one conductivity type, and a second region having the one conductivity type, and the first region is formed below the second region. In order to manufacture a semiconductor device comprising a shallow first portion forming a rectifying barrier, a deep second portion extending to the surface of the semiconductor substrate, and a shallow third portion extending to the semiconductor surface, depositing a conductive material on the conductive material film, performing ion implantation at a high concentration from a selected portion of the conductive material film using a mask to form a second portion of the first region; After converting the conductive material into an insulator, ions are implanted at a low concentration through the conductive material in the non-selected portion to form the first and third portions of the second region, and then the first and third portions of the second region are formed. A method of manufacturing a semiconductor device, characterized in that the second region is formed by performing ion implantation through a portion.