JPS6228618B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing circuit used in a receiving section of a relay device or the like used in optical and coaxial relay transmission systems.

A receiving section of a relay device used in optical and coaxial relay transmission systems usually uses a self-timing system that extracts a timing component from a received waveform. The clock signal thus obtained is supplied to an identification/regeneration circuit or other unit.
The configuration of the relay device is shown in FIG. 1, and the configuration of the timing circuit is shown in FIG. 2.

In FIG. 1, a transmitter SND sends a data signal to a transmission line L from an output circuit OUT.

In the relay device RP, the data signal from the transmission line L is amplified by the equalization amplifier circuit EAM, and the data signal from the transmission line L is amplified by the equalization amplifier circuit EAM.
Input to DIS and timing circuit T.

The timing circuit is a clock signal identification and regeneration circuit.
Input to DIS and other circuits.

The identification and reproduction circuit DIS reproduces and outputs the data signal in synchronization with the clock signal. As shown in Figure 2, the timing circuit T includes a timing extraction circuit TEX that extracts timing components from the received waveform, a tank circuit TN that extracts a specific frequency component from the output of the timing extraction circuit, and a timing extraction circuit TN that slices the output from the tank circuit TN and calculates the amplitude. It consists of a limiter amplifier LM that obtains a constant clock signal.

Now, ideally, the pulse width of the clock signal at the output of the limiter amplifier in FIG. 2 should have an occupation rate of 50%, but in reality, the pulse width fluctuates due to various fluctuation factors. If the pulse width fluctuates too much, the operation of the identification/reproduction circuit, other units, etc. that use it will deteriorate, which is undesirable. Particularly due to integration, when a limiter amplifier is configured using a differential amplifier circuit, this pulse width variation occurs due to drift of both base potentials due to changes in power supply, temperature, element values, etc., but it is said that adjustment is difficult with integration. There was a problem.

The present invention aims to eliminate such drawbacks, and the purpose is to provide a timing extraction circuit that extracts a timing signal component from an input signal, and a tank circuit that extracts a specific signal component from the timing signal component. In a timing circuit having a limiter amplifier that slices the output from the tank circuit, the difference between the two outputs from the limiter amplifier is obtained, the average DC level of the difference is detected, the slice level of the limiter amplifier is controlled, and the limiter amplifier output pulse is detected. This is achieved by a timing circuit characterized by a constant width.

The present invention will be explained below based on examples.

FIG. 3 shows an embodiment of the present invention, and FIG. 4 shows a third embodiment of the present invention.
An example of the average value detection circuit in the figure is shown.

In the present invention, as shown in FIG. 3, V ₀₂ of the outputs V ₀₁ and V ₀₂ of the limiter amplifier LM is outputted as a clock signal, and V ₀₁ and V ₀₂ are outputted to an average value detection circuit.
Input to AV.

The average value detection circuit AV calculates the average DC level (average value) of the difference between these two outputs by taking the difference between V ₀₁ and V ₀₂ , converts it to a current I ₀ , and then converts it to a voltage using the current-voltage conversion circuit IVC. Convert to limita amplifier
Feedback to LM and control slice level Vi ₂ . In this case, only the output V ₀₂ may be input to the average value detection circuit, and the difference from the reference level (level equal to the center of the amplitude of the output V ₀₂ ) may be obtained.
As shown in FIG. 4, the average value detection circuit AV is composed of a Miller integration circuit MI and a voltage/current conversion circuit VIC. The Miller integration circuit MI integrates V ₀₁ and V ₀₂ and outputs integral signals V _M1 and V _M2 , and the voltage/current conversion circuit VIC takes the difference and converts it into a current I _{0 and} outputs it.

Next, a specific example of the limiter amplifier and the average value detection circuit will be explained with reference to FIGS. 5 and 6.

FIG. 5 shows a limiter amplifier and a current-voltage conversion circuit, and in the figure, Tr ₁ to _{Tr 9} are transistors R ₁ to _{R 9} are resistors.

In the figure, the signal V _i1 from the tank circuit is input to the terminal T ₁ and is input to the base of the transistor Tr ₁ via the transistor Tr ₃ .

On the other hand, the slice level Vi ₂ is input to the base of the transistor Tr ₂ via the transistor Tr ₄ .

The base voltage of the transistor Tr ₂ changes depending on the value of I ₀ inputted from an average value detection circuit, which will be described later, via a terminal T ₅ . The collectors of transistors Tr ₁ and Tr ₂ output V ₀₁ according to the difference in base voltage,
V ₀₂ is output to terminals T ₃ and T ₄ .

V ₀₂ is also output as a clock from terminal T ₂ . Terminals T ₃ and T ₄ are connected to an average value detection circuit described later. In addition, resistors R ₄ , R ₉ , transistor Tr ₆
constitutes the current/voltage converter IVC.

Next, the average value detection circuit will be explained with reference to FIG.
In the figure, Tr ₁₀ to Tr ₂₁ are transistors, R ₁₀ to
R ₁₃ is a resistor, C ₁ , C ₂ are capacitors, T ₆ , T ₇ , T ₈
is a terminal.

V ₀₁ from the limiter amplifier is connected to terminals T ₆ and T ₇ ,
V ₀₂ is input and applied to the bases of transistors Tr ₁₀ and Tr ₁₁ via resistors R ₁₂ and R ₁₃ .

From the collectors of transistors Tr ₁₀ and Tr ₁₁
Signals V _M1 and V _M2 obtained by integrating V ₀₁ and V ₀₂ are output,
Transistor Tr ₁₂ and Tr ₁₃
Input to the base of Tr ₁₄ and Tr ₁₅ .

Transistors Tr ₁₄ and Tr ₁₅ are transistors Tr ₁₆ ,
Since it is connected to Tr ₁₇ , the difference between V _M1 and V _M2 is taken, voltage/current conversion is performed, and the result is input to terminal T ₅ of the limiter amplifier via terminal T ₈ .

The operation of the limiter amplifier and average value detection circuit is explained in the seventh section.
This will be further explained using FIG.

FIG. 7 shows a case where the pulse occupancy rate of V ₀₁ and V ₀₂ from the limiter amplifier is 50%. V ₀₁ and V ₀₂ are opposite in phase, and by mirror integration, V _M1 and V _M2 that are symmetrical with respect to the reference are obtained as shown in figure b. The difference between V _M1 and V _M2 is taken and converted into a current as shown in figure c.

The median amplitude of this current I ₀ is constant, in this example zero amperes.

Therefore, even if _I0 is fed back to the limiter ampere to the terminal _T5 , there is no change in operation because the increase or decrease in the current to the current-voltage converter IVC is small.

However, as shown in FIG. 8a, when the pulse occupancy η of the signals V ₀₁ and V ₀₂ is different from 50% (in the example,
(V ₀₂ occupancy η = 37.5%), when integrated, a waveform like b is obtained, and the center value of the voltage-current conversion circuit I ₀ is not constant, and in this example, for example, gradually decreases in the negative direction. Therefore, when this is fed back to the limiter amplifier, the feedback loop works to keep the center value of I ₀ constant, and the pulse width occupation of the clock signal becomes constant. The rate η will be 50%.

That is, the current I ₀ is input to the terminal T ₅ of the limiter amplifier, but if the center value is negative, the current flows into the average value detection circuit as shown by the arrow, so the voltage Vi ₂ at the point A decreases. This voltage Vi ₂ changes until it matches the center value of Vi ₁ . At this time, the center value of the current I ₀ remains constant.

Here, the current I ₀ (converted to voltage and becomes Vi ₂ ) and the output Vi ₁ of the tank circuit TN shown in Figures 7 and 8
The relationship between the two is shown in FIGS. 9 and 10.

As shown in a of both figures, the amplitude of Vi ₂ is significantly smaller than the amplitude of Vi ₁ , and can be regarded as almost a straight line.

FIG. 9 shows a case where the pulse occupancy rate of V ₀₁ and V ₀₂ is 50%, and at this time Vi ₂ coincides with the center value of Vi ₁ . Figure 10 shows the case where the pulse occupancy rate of V ₀₁ and V ₀₂ is 37.5%, and at this time Vi ₂ is the center value of Vi ₁ (shown by the dotted line).
The value gradually deviates from the value shown by the solid line, and the value becomes larger as shown by the solid line.

Note that in FIGS. 9b and 10b, the dotted lines are waveforms obtained when linear amplification is performed without limiting, and the solid lines are waveforms that are limited.

In addition, if there are drifts, element value fluctuations, etc. other than the drifts of Vi ₁ and Vi ₂ , Vi ₁
It goes without saying that the central value of Vi ₂ does not necessarily match, but becomes stable at a certain appropriate difference, and the pulse occupancy rate η = 50%. As described above, according to the circuit of the present invention, the pulse occupancy rate of the limiter amplifier output clock signal is always 50%.
Unaffected by element value fluctuations. This method is particularly effective when applied to integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a transmitter and a relay device,
Figure 2 is a diagram showing the configuration of a conventional timing circuit.
Figure 3 is a diagram showing the configuration according to the present invention, Figure 4 is a diagram showing the configuration of the average value detection circuit, Figure 5 is a diagram showing the specific configuration of the limiter amplifier and current-voltage conversion circuit, and Figure 6 is the average value detection circuit. 7 and 8 are time charts showing the operation of the average value detection circuit, and FIGS. 9 and 10 are time charts showing the operation of the limiter amplifier. In the figure, TEX is a timing extraction circuit, TN is a tank circuit, LM is a limiter amplifier, AV is an average value detection circuit, MI is a Miller integration circuit, and VIC is a voltage/current detection circuit.

Claims (1)

[Scope of Claims] 1. A timing system that includes a timing extraction circuit that extracts a timing signal component from an input signal, a tank circuit that extracts a specific signal component from the timing signal component, and a limiter amplifier that slices the output from the tank circuit. In the circuit, the two outputs from the limiter amplifier have opposite polarities.
A timing circuit characterized in that a difference in output is obtained, an average DC level of the difference is detected, a slice level of a limiter amplifier is controlled, and the output pulse width of the limiter amplifier is kept constant. 2. The limiter amplifier is configured with a differential amplifier, and the two outputs of the differential amplifier are input to an integrating circuit to detect the average level of the difference, and the two outputs output from the integrating circuit with opposite polarities are converted into a voltage. 2. The timing circuit according to claim 1, wherein the timing circuit is input to a current conversion circuit to obtain a difference between the two outputs to control a slice level of the differential amplifier. 3. The timing circuit according to claim 2, wherein a Miller integrating circuit is used as the integrating circuit.