JPS6228620B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital synchronous circuit suitable for high-speed digital transmission.

A block diagram of a conventional digital synchronous circuit is shown in FIG.

2A and 2B are time charts showing the waveforms at points a and b in FIG. 1, where A is the clock waveform and B is the output pulse waveform of the comparator circuit 4 in the case of a 1-bit shift.

In the figure, 1 is an inhibition gate circuit (OR circuit), 2 is a counter, 3 is a reference data generation circuit, 4 is a comparison circuit,
5 is a clock input terminal, 6 is a data input terminal, τ
is the sum of the delay times caused by the counter 2 and the comparison circuit 4. To bring the counter 2 into a synchronous state in the digital synchronous circuit, a clock signal as shown in FIG. 2A is applied to the counter 2 through the inhibit gate 1.
For example, when one frame consists of N bits and the frame synchronization signal is a signal such as 1010, an output signal is sent to the reference data generator 3 when the counter 2 counts N bits of the clock signal. The reference data generator 3 uses the output signal from the counter 2 to compare the reference data having the same pattern as the 1010 frame synchronization signal with the input data input from the terminal 6 in the comparator circuit 4, and compares the input data input from the terminal 6 to find out whether it matches the reference frame synchronization signal. If not, a 1-bit pulse as shown in FIG. Shifting the reference frame synchronization signal generated by 1 bit by 1 bit and comparing it again,
If they match, the comparator circuit 4 will not generate a pulse.
This brings the counter 2 into a synchronous state.

In the case of FIG. 2B, a state is shown in which the synchronization state has been reached by shifting one bit. However, in this circuit, the output pulse from the comparator circuit 4 is delayed from the clock pulse by the sum of the delay times by the counter 2 and the comparator circuit 4. If this delay time is within half a period of the clock pulse, A will occur as shown in Figure 2.
If the comparator circuit 4 cannot output the signal shown in B by the time the clock shown in falls, the number of clocks cannot be decreased by one via the inhibition gate circuit 1, and the output of the counter 2 described above cannot be shifted by one bit. , it can only be used for digital transmission up to the same transmission speed as a clock pulse with delay time τ as a half cycle; for higher-speed digital transmission, it becomes difficult to realize the circuits of counter 2 and comparison circuit 4. There are drawbacks.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital synchronization circuit that can be applied even in high-speed digital transmission in order to eliminate the above-mentioned drawbacks.

To achieve the above object, the present invention provides a digital synchronization circuit comprising a counter, a comparison circuit for comparing input data and reference data, and a gate circuit for inhibiting the input signal of the counter by the output of the comparison circuit. This digital synchronous circuit is characterized in that a register circuit is inserted at the front stage to read the output signal of the input inhibit gate circuit of the counter as a clock signal.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of a digital synchronous circuit according to an embodiment of the present invention, and FIGS. 4A to 4H are c to g of FIG.
This is a case where the counter 2 is brought into a synchronized state by one bit shift in the time chart of the pulse waveform at point d.

Components in the figure that have the same functions as those in FIG. 1 are designated by the same numbers. 7 and 8 are D-flip-flops (hereinafter referred to as D-
FF), 9 is NOT circuit, τo is counter 2
τcomp is the delay time caused by the comparator circuit 4, h to m are symbols for explanation.

This circuit is obtained by inserting a register circuit consisting of D-FFs 7 and 8 into the circuit shown in FIG.

When a clock signal as shown in FIG. 4A is supplied to the counter 2 via the inhibit gate circuit 1, the counter 2 counts this clock, and at point e, a 1-bit signal as shown in B is output at point e, which corresponds to the beginning position of the frame synchronization pulse. Generates a pulse. If the input data does not match the frame synchronization signal, the comparison circuit 4 outputs a signal as shown in FIG. 4E, as in the case of FIG. 1.

The clock signal shown at A and the output signal shown at B of the comparator circuit 4 are connected to the c terminal of the D-FF7, and the signal shown at H via the inhibition gate circuit 1 is connected to the NOT circuit 9.
Since the inverted signal is input at point f, the pulse waveform C at point f becomes 1 at the falling point of h, remains unchanged at the falling point of j, and becomes 0 at the falling point of l. The pulse waveform D at point g is generated by the rising edge of i because the clock signal shown at A is input to C of D-FF8, and the signal shown at H is inputted to the output signal shown at E of comparator circuit 4 via the inhibit gate circuit 1. It becomes 1 at the rising point of k, remains unchanged at the rising point of k, and becomes 0 at the rising point of m. If frame synchronization is achieved and the pulse shown in FIG. 4E is not output, this will become 0 at the rising point of point h, but compared to this, it is shifted by 1 bit. Then, based on the output of the D-FF 8, the reference data generator 3 outputs a frame synchronization pattern of 1010 (indicated by F). At this time, if the input data is inputted to the comparator circuit 4 with a delay of 1 bit from F, as shown in G, F and G do not match at the 1st bit of the frame synchronization pattern output from the reference data generator 3, and the comparison Circuit 4 outputs a signal as shown in E. The signal obtained by ORing the output signal E of the comparator circuit 4 and the clock signal A becomes H, which becomes the output signal of the inhibit gate circuit 1. As can be seen from FIG. 4, the output H of the inhibition gate circuit 1
converts two clocks of the clock signal into one clock, so that counter 2 interrupts counting for one clock. Therefore, the frame synchronization pattern outputted from the reference data generator 3 is outputted with a one clock delay in the next frame, and is in phase with the frame synchronization signal of the input data. That is, the reference frame synchronization signal generated from the reference data generator 3 is shifted by one bit by the output signal of the comparison circuit 4 shown at E.

The comparison circuit 4 compares the reference frame synchronization signal shifted by 1 bit with the input data input from the terminal 6, and if they match the reference frame synchronization signal, the comparison circuit 4 outputs nothing. If they do not match, the comparison circuit 4 outputs nothing. A 1-bit pulse as shown at E is generated in the same manner as in the explanation of FIG.

With this pulse, as explained above, the reference frame synchronization signal is shifted by one bit, shifted one after another until it matches the frame synchronization signal of the input data, and the counter 2 is brought into synchronization. However, the pulse shown at B is delayed by a delay time τo from the clock pulse by the counter 2. If this delay time .tau.o is not within half a period of the clock pulse, the reference frame synchronization signal will be lost, but since this is the delay time of only the counter circuit 2, it can be reduced to about 1/2 compared to the case of FIG. Also, the delay time τcomp by the comparator circuit 4 is the rise time of the pulse shown in D, that is, the delay time from the clock pulse i shown in A, and unless this is within half a period of the clock pulse, the reference frame synchronization signal cannot be delayed by one pulse. Since the delay time is only for comparator circuit 4, it is approximately
It can be reduced to 1/2. Therefore, in the case of the present invention, the delay time of the counter 2 and the comparator circuit 4 may be approximately twice that of the conventional case. That is, in the conventional case, the sum of the delay times of the counter 2 and the comparator circuit 4 must be within half a clock cycle, but in the case of the present invention, the delay times of the counter 2 and the comparator circuit 4 must each be within a half cycle of the clock. It is fine if
It can also be used for digital transmission that is approximately twice as fast as the conventional field, and is suitable for digital synchronization circuits for high-speed digital transmission.

As explained in detail above, according to the present invention, the delay time of the counter and comparator circuit may be approximately twice that of the conventional case, so that it is possible to provide a digital synchronization circuit that can be fully realized even in the case of high-speed digital transmission. be.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional digital synchronization circuit, and Fig. 2 A and B are time charts showing waveforms at points a and b in Fig. 1, where A is a clock waveform and B is a clock waveform.
The output pulse waveform of the comparator circuit 4 in the case of bit shift, FIG. 3 is a block diagram of the digital synchronization circuit according to the embodiment of the present invention, and FIGS.
This is a case where the counter 2 is brought into synchronization by shifting one bit in the time chart of the pulse waveform at points g and d. In the figure, 1 is an inhibition gate circuit (OR circuit), 2 is a counter, 3 is a reference data generation circuit, 4 is a comparison circuit,
5 is a clock input terminal, 6 is a data input terminal,
7 and 8 are D-FF, 9 is NOT circuit, τ, τo, τ
comp is the sum of the delay times of the counter and comparison circuit,
Counter delay time, comparison circuit delay time, h~
m is a symbol for explanation.

Claims (1)

[Scope of Claims] 1. A counter that counts clock signals and sends out an output signal when a specific count value is reached; a reference data generation circuit that outputs frame synchronization reference data based on the output signal of the counter; and the reference data. A digital synchronizer comprising a comparison circuit that compares input data to determine the frame synchronization state, and a gate circuit that prohibits clock signal input to the counter when the comparison circuit detects that the frame synchronization is out. The circuit operates using the output signal of the gate circuit as a clock signal, reads the output signal of the counter,
A digital synchronous circuit comprising a register circuit for outputting to the reference data generation circuit.